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| author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2010-10-22 17:53:39 +0200 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2010-10-26 11:32:48 +0200 |
| commit | 8aeeda822fbfe7da2d4ea391a9757e9532796598 (patch) | |
| tree | 04b001427ac194ad070c7cd6ee89c23af0f125cc /arch/arm/mach-at91/pm.h | |
| parent | bb413db591d53c29292868577068fa822b84da82 (diff) | |
| download | linux-stable-8aeeda822fbfe7da2d4ea391a9757e9532796598.tar.gz linux-stable-8aeeda822fbfe7da2d4ea391a9757e9532796598.tar.bz2 linux-stable-8aeeda822fbfe7da2d4ea391a9757e9532796598.zip | |
AT91: pm: use plain cpu_do_idle() for "wait for interrupt"
For power management at91_pm_enter() routine, use the cpu_do_idle() for a
rock solid "wait for interrupt" implementation.
For AT91SAM9 ARM 926 based chips, we can exceed the cache line length as
we can access RAM even while in self-refresh mode.
We keep plain access to CP15 for at91rm9200 as this feature is not
available: instructions have to be in a single cache line.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/pm.h')
| -rw-r--r-- | arch/arm/mach-at91/pm.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 8c87d0c1b8f8..2c4424bfa6c4 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -21,6 +21,7 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) +#define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4") #elif defined(CONFIG_ARCH_AT91CAP9) #include <mach/at91cap9_ddrsdr.h> @@ -38,6 +39,7 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) +#define wait_for_interrupt_enable() cpu_do_idle() #elif defined(CONFIG_ARCH_AT91SAM9G45) #include <mach/at91sam9_ddrsdr.h> @@ -74,6 +76,7 @@ static inline u32 sdram_selfrefresh_enable(void) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ } while (0) +#define wait_for_interrupt_enable() cpu_do_idle() #else #include <mach/at91sam9_sdramc.h> @@ -98,5 +101,6 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) +#define wait_for_interrupt_enable() cpu_do_idle() #endif |