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| author | Arnd Bergmann <arnd@arndb.de> | 2013-01-25 22:44:17 +0000 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-04-18 16:31:02 +0200 |
| commit | f5fa4098c3fcc0e504fbc0682dccd331dbbcf197 (patch) | |
| tree | f409c2b7fea4d220a6e0682f09c1133f208fe97b /arch/arm/mach-at91/pm.h | |
| parent | 13ab6aeb49663b0ca0f0eed3560fbaecacf4858f (diff) | |
| download | linux-stable-f5fa4098c3fcc0e504fbc0682dccd331dbbcf197.tar.gz linux-stable-f5fa4098c3fcc0e504fbc0682dccd331dbbcf197.tar.bz2 linux-stable-f5fa4098c3fcc0e504fbc0682dccd331dbbcf197.zip | |
ARM: at91: suspend both memory controllers on at91sam9263
For the past three years, we have had a #warning in
mach-at91 about the sdram_selfrefresh_enable or
at91sam9_standby functions possibly not working on
at91sam9263. In the meantime a function was added
to do the right thing on at91sam9g45, which looks like
it should also work on '9263.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: remove paragraph in commit message]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'arch/arm/mach-at91/pm.h')
| -rw-r--r-- | arch/arm/mach-at91/pm.h | 30 |
1 files changed, 24 insertions, 6 deletions
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 38f467c6b710..2f5908f0b8c5 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -70,13 +70,31 @@ static inline void at91sam9g45_standby(void) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } -#ifdef CONFIG_SOC_AT91SAM9263 -/* - * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; - * handle those cases both here and in the Suspend-To-RAM support. +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. */ -#warning Assuming EB1 SDRAM controller is *NOT* used -#endif +static inline void at91sam9263_standby(void) +{ + u32 lpr0, lpr1; + u32 saved_lpr0, saved_lpr1; + + saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); + lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; + lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + + saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); + lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; + lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); + at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); + at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); +} static inline void at91sam9_standby(void) { |