diff options
author | Mikael Pettersson <mikpe@it.uu.se> | 2009-10-29 11:46:54 -0700 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2009-10-29 11:46:54 -0700 |
commit | 469d30448dad13600cdd246024f9db8e80614c45 (patch) | |
tree | a610e9dd4b40dd540376eba7aaaed2538298f828 /arch/arm/mach-iop13xx/include/mach/time.h | |
parent | a91549a8f27e63e0e537fe1c20d4845581de894f (diff) | |
download | linux-stable-469d30448dad13600cdd246024f9db8e80614c45.tar.gz linux-stable-469d30448dad13600cdd246024f9db8e80614c45.tar.bz2 linux-stable-469d30448dad13600cdd246024f9db8e80614c45.zip |
iop: clockevent support
This updates the IOP platform to expose the interrupting
timer 0 as a clockevent object. The timer interrupt handler
is changed to call the clockevent ->event_handler() instead
of timer_tick(), and ->set_next_event() and ->set_mode()
operations are added to allow the mode of the timer to be
updated (required for ONESHOT/NOHZ mode).
Timer 0 must now be properly initialised, which requires
a new write_tcr0() function from the mach-specific code.
The mode of timer 0 must be read at the start of ->set_mode(),
which requires a new read_tmr0() function from the mach-
specific code.
Initial setup of timer 0 is also rewritten to be more robust.
Tested on n2100, compile-tested for all plat-iop machines.
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch/arm/mach-iop13xx/include/mach/time.h')
-rw-r--r-- | arch/arm/mach-iop13xx/include/mach/time.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h index 9fb2768c84bb..b2fb17b35423 100644 --- a/arch/arm/mach-iop13xx/include/mach/time.h +++ b/arch/arm/mach-iop13xx/include/mach/time.h @@ -66,6 +66,13 @@ static inline unsigned long iop13xx_xsi_bus_ratio(void) return 2; } +static inline u32 read_tmr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val)); + return val; +} + static inline void write_tmr0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); @@ -83,6 +90,11 @@ static inline u32 read_tcr0(void) return val; } +static inline void write_tcr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val)); +} + static inline u32 read_tcr1(void) { u32 val; |