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| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2006-09-18 23:21:38 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-25 10:25:45 +0100 |
| commit | 38ce73ebd74a9a1738b73619557f2397c59ba628 (patch) | |
| tree | 02c812c665d0bb9c6872f81ad64328306fa3157f /arch/arm/mach-iop32x | |
| parent | 0b29de4a6ac0936f56b974a3c19bd9c24ac5b5d7 (diff) | |
| download | linux-stable-38ce73ebd74a9a1738b73619557f2397c59ba628.tar.gz linux-stable-38ce73ebd74a9a1738b73619557f2397c59ba628.tar.bz2 linux-stable-38ce73ebd74a9a1738b73619557f2397c59ba628.zip | |
[ARM] 3825/1: iop3xx: use cp6 enable/disable macros
Add CP6 enable/disable sequences to the timekeeping code and the IRQ
code. As a result, we can't depend on CP6 access being enabled when
we enter get_irqnr_and_base anymore, so switch the latter over to
using memory-mapped accesses for now.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop32x')
| -rw-r--r-- | arch/arm/mach-iop32x/irq.c | 23 |
1 files changed, 5 insertions, 18 deletions
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 76f2d561dbc1..cdd6943ce768 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -27,12 +27,16 @@ static u32 iop321_mask /* = 0 */; static inline void intctl_write(u32 val) { + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static inline void intstr_write(u32 val) { + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static void @@ -61,24 +65,7 @@ struct irq_chip ext_chip = { void __init iop321_init_irq(void) { - unsigned int i, tmp; - - /* Enable access to coprocessor 6 for dealing with IRQs. - * From RMK: - * Basically, the Intel documentation here is poor. It appears that - * you need to set the bit to be able to access the coprocessor from - * SVC mode. Whether that allows access from user space or not is - * unclear. - */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, %1\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - /* The action is delayed, so we have to do this: */ - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4" - : "=r" (tmp) : "i" (1 << 6) ); + unsigned int i; intctl_write(0); // disable all interrupts intstr_write(0); // treat all as IRQ |