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author | Paul Walmsley <paul@pwsan.com> | 2009-01-28 12:35:03 -0700 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 17:50:44 +0000 |
commit | 439764cc18beb20ef409991e75e29b460db71d33 (patch) | |
tree | 6ae4c648bfe34c3f511fef89282f10efe69ca48b /arch/arm/mach-omap2/clock.c | |
parent | de07fedd79999668c4c112a2ba3eaf3d7434235c (diff) | |
download | linux-stable-439764cc18beb20ef409991e75e29b460db71d33.tar.gz linux-stable-439764cc18beb20ef409991e75e29b460db71d33.tar.bz2 linux-stable-439764cc18beb20ef409991e75e29b460db71d33.zip |
[ARM] OMAP2xxx clock: consolidate DELAYED_APP clock commits; fix barrier
Consolidate the commit code for DELAYED_APP clocks into a subroutine,
_omap2xxx_clk_commit(). Also convert the MPU barrier wmb() into an
OCP barrier, since with an MPU barrier, we have no guarantee that the
write actually reached the endpoint device.
linux-omap source commit is 0f5bdb736515801b296125d16937a21ff7b3cfdc.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 33 |
1 files changed, 24 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 0803c8c811f4..7f12230fef73 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -74,6 +74,28 @@ u8 cpu_mask; * OMAP2/3 specific clock functions *-------------------------------------------------------------------------*/ +/** + * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware + * @clk: struct clk * + * + * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes + * don't take effect until the VALID_CONFIG bit is written, write the + * VALID_CONFIG bit and wait for the write to complete. No return value. + */ +static void _omap2xxx_clk_commit(struct clk *clk) +{ + if (!cpu_is_omap24xx()) + return; + + if (!(clk->flags & DELAYED_APP)) + return; + + prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); + /* OCP barrier */ + prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); +} + /* * _dpll_test_fint - test whether an Fint value is valid for the DPLL * @clk: DPLL struct clk to test @@ -685,11 +707,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) clk->rate = clk->parent->rate / new_div; - if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { - prm_write_mod_reg(OMAP24XX_VALID_CONFIG, - OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); - wmb(); - } + _omap2xxx_clk_commit(clk); return 0; } @@ -772,10 +790,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) __raw_writel(v, clk->clksel_reg); wmb(); - if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { - __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); - wmb(); - } + _omap2xxx_clk_commit(clk); if (clk->usecount > 0) _omap2_clk_enable(clk); |