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authorSebastian Reichel <sebastian.reichel@collabora.co.uk>2017-06-13 11:28:45 +0200
committerTony Lindgren <tony@atomide.com>2017-06-14 00:51:35 -0700
commit9a9ded89ad9ca46382a4ea63f36f830bccfab4ec (patch)
treea8da49185dca023b4c5a730ca7f88aa2ef884bef /arch/arm/mach-omap2
parent67d00470accf5c58abbb23a44c867c5f15437976 (diff)
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ARM: OMAP4: hwmod data: add aes1
This fixes the following error during kernel boot: platform 4b501000.aes: Cannot lookup hwmod 'aes1' Unfortunately the AES module is only documented partly in the OMAP4430 TRM. I found an old patch from Joel, which I took over and updated for currently mainline. Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0855434773fa..7833caf277b6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -961,6 +961,46 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
};
/*
+ Crypto modules AES0/1 belong to:
+ PD_L4_PER power domain
+ CD_L4_SEC clock domain
+ On the L3, the AES modules are mapped to
+ L3_CLK2: Peripherals and multimedia sub clock domain
+*/
+static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
+ .rev_offs = 0x80,
+ .sysc_offs = 0x84,
+ .syss_offs = 0x88,
+ .sysc_flags = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
+ .name = "aes",
+ .sysc = &omap44xx_aes_sysc,
+};
+
+static struct omap_hwmod omap44xx_aes1_hwmod = {
+ .name = "aes1",
+ .class = &omap44xx_aes_hwmod_class,
+ .clkdm_name = "l4_secure_clkdm",
+ .main_clk = "l3_div_ck",
+ .prcm = {
+ .omap4 = {
+ .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
+ .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_aes1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
* 'fdif' class
* face detection hw accelerator module
*/
@@ -4801,6 +4841,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_abe__wd_timer3_dma,
&omap44xx_mpu__emif1,
&omap44xx_mpu__emif2,
+ &omap44xx_l3_main_2__aes1,
NULL,
};