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| author | Dmitry Osipenko <digetx@gmail.com> | 2020-03-13 12:01:04 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-06 18:43:24 +0200 |
| commit | 35509737c8f958944e059d501255a0bf18361ba0 (patch) | |
| tree | 08e54f009af1643ca6e322760165c84242a100a2 /arch/arm/mach-tegra/sleep-tegra30.S | |
| parent | 38743e414e7cc6d23f41276f298ad4781890a89f (diff) | |
| download | linux-stable-35509737c8f958944e059d501255a0bf18361ba0.tar.gz linux-stable-35509737c8f958944e059d501255a0bf18361ba0.tar.bz2 linux-stable-35509737c8f958944e059d501255a0bf18361ba0.zip | |
ARM: tegra: Correct PL310 Auxiliary Control Register initialization
The PL310 Auxiliary Control Register shouldn't have the "Full line of
zero" optimization bit being set before L2 cache is enabled. The L2X0
driver takes care of enabling the optimization by itself.
This patch fixes a noisy error message on Tegra20 and Tegra30 telling
that cache optimization is erroneously enabled without enabling it for
the CPU:
L2C-310: enabling full line of zeros but not enabled in Cortex-A9
Cc: <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-tegra30.S')
0 files changed, 0 insertions, 0 deletions