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authorArnd Bergmann <arnd@arndb.de>2014-03-27 02:10:57 +0100
committerArnd Bergmann <arnd@arndb.de>2014-03-27 02:19:41 +0100
commit32adc19d4b2f2d9a26fbbd0c1744d5b313106d6a (patch)
tree5e034ff3b39b6495a4d1d2cc3839b985b2e711d0 /arch/arm/mach-zynq/common.c
parent22673b71689a65a89335d0f3e42ce952efb3e7e1 (diff)
parent1a259251f3638b04c1dbe07220958af9572c95bb (diff)
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Merge tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx into next/cleanup2
Merge "arm: Xilinx Zynq cleanup patches for v3.15" from Michal Simek: - Redesign SLCR initialization to enable driver developing which targets SLCR space * tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx: ARM: zynq: Add waituart implementation ARM: zynq: Move of_clk_init from clock driver ARM: zynq: Introduce zynq_slcr_unlock() ARM: zynq: Add and use zynq_slcr_read/write() helper functions ARM: zynq: Make zynq_slcr_base static ARM: zynq: Map I/O memory on clkc init ARM: zynq: Hang iomapped slcr address on device_node ARM: zynq: Split slcr in two parts ARM: zynq: Move clock_init from slcr to common arm: dt: zynq: Add fclk-enable property to clkc node [Arnd: remove SOC_BUS support from pull request] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-zynq/common.c')
-rw-r--r--arch/arm/mach-zynq/common.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 8c09a8393fb6..dca60d5ba756 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -19,6 +19,7 @@
#include <linux/cpumask.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/clk/zynq.h>
#include <linux/clocksource.h>
#include <linux/of_address.h>
@@ -72,11 +73,16 @@ static void __init zynq_init_machine(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
platform_device_register(&zynq_cpuidle_device);
+
+ zynq_slcr_init();
}
static void __init zynq_timer_init(void)
{
- zynq_slcr_init();
+ zynq_early_slcr_init();
+
+ zynq_clock_init();
+ of_clk_init(NULL);
clocksource_of_init();
}