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| author | YH Huang <yh.huang@mediatek.com> | 2015-10-06 15:40:43 +0800 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2015-11-20 13:42:29 +0100 |
| commit | 61aee93425149e2288c4ab1466847093af678de6 (patch) | |
| tree | 5a3a82187b904bd230544ebd1d8cb7d94e6b3c93 /arch/arm64/boot | |
| parent | b2c76e275f7b583ab718dc04805d79c8f25d036d (diff) | |
| download | linux-stable-61aee93425149e2288c4ab1466847093af678de6.tar.gz linux-stable-61aee93425149e2288c4ab1466847093af678de6.tar.bz2 linux-stable-61aee93425149e2288c4ab1466847093af678de6.zip | |
arm64: dts: mt8173: add MT8173 display PWM driver support node
Add display PWM node in mt8173-evb.dts and mt8173.dtsi.
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 13 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 |
2 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 811cb760ba49..1b3fabd10307 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -92,6 +92,13 @@ }; &pio { + disp_pwm0_pins: disp_pwm0_pins { + pins1 { + pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; + output-low; + }; + }; + mmc0_pins_default: mmc0default { pins_cmd_dat { pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, @@ -190,6 +197,12 @@ }; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + &pwrap { pmic: mt6397 { compatible = "mediatek,mt6397"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d301ce5c9da9..ed0047a3b687 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -525,6 +525,28 @@ #clock-cells = <1>; }; + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM026M>, + <&mmsys CLK_MM_DISP_PWM0MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + pwm1: pwm@1401f000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401f000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM126M>, + <&mmsys CLK_MM_DISP_PWM1MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8173-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; |