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| author | Will Deacon <will.deacon@arm.com> | 2018-03-27 12:04:51 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-03-27 12:04:51 +0100 |
| commit | 3f251cf0abec2afb6eca67f71380670dd55bdebe (patch) | |
| tree | e2ebead8eb4ed13267839d8710749154d77545d7 /arch/arm64/kernel | |
| parent | 12eb369125abe92bfc55e9ce198200f5807b63ff (diff) | |
| download | linux-stable-3f251cf0abec2afb6eca67f71380670dd55bdebe.tar.gz linux-stable-3f251cf0abec2afb6eca67f71380670dd55bdebe.tar.bz2 linux-stable-3f251cf0abec2afb6eca67f71380670dd55bdebe.zip | |
Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)"
This reverts commit 1f85b42a691cd8329ba82dbcaeec80ac1231b32a.
The internal dma-direct.h API has changed in -next, which collides with
us trying to use it to manage non-coherent DMA devices on systems with
unreasonably large cache writeback granules.
This isn't at all trivial to resolve, so revert our changes for now and
we can revisit this after the merge window. Effectively, this just
restores our behaviour back to that of 4.16.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 071a4548a231..96b15d7b10a8 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1624,6 +1624,7 @@ static void __init setup_system_capabilities(void) void __init setup_cpu_features(void) { u32 cwg; + int cls; setup_system_capabilities(); mark_const_caps_ready(); @@ -1644,9 +1645,13 @@ void __init setup_cpu_features(void) * Check for sane CTR_EL0.CWG value. */ cwg = cache_type_cwg(); + cls = cache_line_size(); if (!cwg) - pr_warn("No Cache Writeback Granule information, assuming %d\n", - ARCH_DMA_MINALIGN); + pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", + cls); + if (L1_CACHE_BYTES < cls) + pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", + L1_CACHE_BYTES, cls); } static bool __maybe_unused |