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| author | Will Deacon <will.deacon@arm.com> | 2011-04-05 13:57:53 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-04-10 21:13:35 +0100 |
| commit | e89c0d7090c54d7b11b9b091e495a1ae345dd3ff (patch) | |
| tree | 279617e19acadcafd6c7c22e9e4f5e7395236a9e /arch/arm | |
| parent | 6a7861825f79f09213ef81b3c468f6f2e86f408e (diff) | |
| download | linux-stable-e89c0d7090c54d7b11b9b091e495a1ae345dd3ff.tar.gz linux-stable-e89c0d7090c54d7b11b9b091e495a1ae345dd3ff.tar.bz2 linux-stable-e89c0d7090c54d7b11b9b091e495a1ae345dd3ff.zip | |
ARM: 6864/1: hw_breakpoint: clear DBGVCR out of reset
The DBGVCR, used for configuring vector catch debug events, is UNKNOWN
out of reset on ARMv7. When enabling monitor mode, this must be zeroed
to avoid UNPREDICTABLE behaviour.
This patch adds the zeroing code to the debug reset path.
Cc: stable <stable@kernel.org>
Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/kernel/hw_breakpoint.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 8dbc126f7152..87acc25d7a3e 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -868,6 +868,13 @@ static void reset_ctrl_regs(void *info) */ asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); isb(); + + /* + * Clear any configured vector-catch events before + * enabling monitor mode. + */ + asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); + isb(); } if (enable_monitor_mode()) |