diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2010-08-05 07:49:26 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-18 04:01:04 -0400 |
| commit | c6345ab1a3d17f4b6c80ac79d7fb0f006b32fdaa (patch) | |
| tree | 8f3980f69cba2e3269aa9688426fca95be56d7a6 /arch/blackfin/Kconfig | |
| parent | 6f546bc3ac9eedbf770bf3bcbc45ce2ea32c94ad (diff) | |
| download | linux-stable-c6345ab1a3d17f4b6c80ac79d7fb0f006b32fdaa.tar.gz linux-stable-c6345ab1a3d17f4b6c80ac79d7fb0f006b32fdaa.tar.bz2 linux-stable-c6345ab1a3d17f4b6c80ac79d7fb0f006b32fdaa.zip | |
Blackfin: SMP: work around anomaly 05000491
In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram. The trouble with multi-core systems is that all
L1 sram is visible only to the active core. So we can't just place the
functions into L1 and call it directly. We need to setup a jump table and
place the entry point in external memory. This will call the right func
based on the active core.
In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/Kconfig')
| -rw-r--r-- | arch/blackfin/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 0f34ec58bac3..c4cda6f52b61 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -850,7 +850,6 @@ config CPLB_SWITCH_TAB_L1 config ICACHE_FLUSH_L1 bool "Locate icache flush funcs in L1 Inst Memory" default y - depends on !SMP help If enabled, the Blackfin icache flushing functions are linked into L1 instruction memory. |