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| author | Dave Airlie <airlied@redhat.com> | 2012-08-27 16:22:20 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2012-08-27 16:22:20 +1000 |
| commit | 93bb70e0c00f1be4cc857e4d8375c44058cce71e (patch) | |
| tree | 7b6a11844e00b3f4bf8281c7a799e61494220819 /arch/c6x/include/asm/cache.h | |
| parent | 6f314ebbaa2667d67a7206ba78f28e46cf47eda5 (diff) | |
| parent | c182ae42cc3611f7b3fa803c0bcab6e5d29bea63 (diff) | |
| download | linux-stable-93bb70e0c00f1be4cc857e4d8375c44058cce71e.tar.gz linux-stable-93bb70e0c00f1be4cc857e4d8375c44058cce71e.tar.bz2 linux-stable-93bb70e0c00f1be4cc857e4d8375c44058cce71e.zip | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next
There was some merge conflicts in -next and they weren't so pretty, so
backmerge now to avoid them.
Conflicts:
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/intel_modes.c
Diffstat (limited to 'arch/c6x/include/asm/cache.h')
| -rw-r--r-- | arch/c6x/include/asm/cache.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h index 6d521d96d941..09c5a0f5f4d1 100644 --- a/arch/c6x/include/asm/cache.h +++ b/arch/c6x/include/asm/cache.h @@ -1,7 +1,7 @@ /* * Port on Texas Instruments TMS320C6x architecture * - * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated + * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) * * This program is free software; you can redistribute it and/or modify @@ -16,9 +16,14 @@ /* * Cache line size */ -#define L1D_CACHE_BYTES 64 -#define L1P_CACHE_BYTES 32 -#define L2_CACHE_BYTES 128 +#define L1D_CACHE_SHIFT 6 +#define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) + +#define L1P_CACHE_SHIFT 5 +#define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) + +#define L2_CACHE_SHIFT 7 +#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) /* * L2 used as cache @@ -29,7 +34,8 @@ * For practical reasons the L1_CACHE_BYTES defines should not be smaller than * the L2 line size */ -#define L1_CACHE_BYTES L2_CACHE_BYTES +#define L1_CACHE_SHIFT L2_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define L2_CACHE_ALIGN_LOW(x) \ (((x) & ~(L2_CACHE_BYTES - 1))) |