Merge tag 'please-pull-ia64_for_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux

Pull ia64 updates from Tony Luck:
 "The big change here is removal of support for SGI Altix"

* tag 'please-pull-ia64_for_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux: (33 commits)
  genirq: remove the is_affinity_mask_valid hook
  ia64: remove CONFIG_SWIOTLB ifdefs
  ia64: remove support for machvecs
  ia64: move the screen_info setup to common code
  ia64: move the ROOT_DEV setup to common code
  ia64: rework iommu probing
  ia64: remove the unused sn_coherency_id symbol
  ia64: remove the SGI UV simulator support
  ia64: remove the zx1 swiotlb machvec
  ia64: remove CONFIG_ACPI ifdefs
  ia64: remove CONFIG_PCI ifdefs
  ia64: remove the hpsim platform
  ia64: remove now unused machvec indirections
  ia64: remove support for the SGI SN2 platform
  drivers: remove the SGI SN2 IOC4 base support
  drivers: remove the SGI SN2 IOC3 base support
  qla2xxx: remove SGI SN2 support
  qla1280: remove SGI SN2 support
  misc/sgi-xp: remove SGI SN2 support
  char/mspec: remove SGI SN2 support
  ...

172 files changed, 306 insertions, 25603 deletions

diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 7468d8e50467..13d49c232556 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -10,12 +10,14 @@ config IA64
 	bool
 	select ARCH_MIGHT_HAVE_PC_PARPORT
 	select ARCH_MIGHT_HAVE_PC_SERIO
-	select ACPI if (!IA64_HP_SIM)
-	select ARCH_SUPPORTS_ACPI if (!IA64_HP_SIM)
+	select ACPI
+	select ACPI_NUMA if NUMA
+	select ARCH_SUPPORTS_ACPI
 	select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI
 	select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI
-	select FORCE_PCI if (!IA64_HP_SIM)
+	select FORCE_PCI
 	select PCI_DOMAINS if PCI
+	select PCI_MSI
 	select PCI_SYSCALL if PCI
 	select HAVE_UNSTABLE_SCHED_CLOCK
 	select HAVE_EXIT_THREAD
@@ -30,8 +32,8 @@ config IA64
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_MEMBLOCK_NODE_MAP
 	select HAVE_VIRT_CPU_ACCOUNTING
-	select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB
-	select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
+	select ARCH_HAS_DMA_COHERENT_TO_PFN
+	select ARCH_HAS_SYNC_DMA_FOR_CPU
 	select VIRT_TO_BUS
 	select GENERIC_IRQ_PROBE
 	select GENERIC_PENDING_IRQ if SMP
@@ -45,6 +47,7 @@ config IA64
 	select ARCH_THREAD_STACK_ALLOCATOR
 	select ARCH_CLOCKSOURCE_DATA
 	select GENERIC_TIME_VSYSCALL
+	select SWIOTLB
 	select SYSCTL_ARCH_UNALIGN_NO_WARN
 	select HAVE_MOD_ARCH_SPECIFIC
 	select MODULES_USE_ELF_RELA
@@ -52,6 +55,7 @@ config IA64
 	select HAVE_ARCH_AUDITSYSCALL
 	select NEED_DMA_MAP_STATE
 	select NEED_SG_DMA_LENGTH
+	select NUMA if !FLATMEM
 	default y
 	help
 	  The Itanium Processor Family is Intel's 64-bit successor to
@@ -66,7 +70,6 @@ config 64BIT
 
 config ZONE_DMA32
 	def_bool y
-	depends on !IA64_SGI_SN2
 
 config QUICKLIST
 	bool
@@ -121,87 +124,6 @@ config AUDIT_ARCH
 	default y
 
 choice
-	prompt "System type"
-	default IA64_GENERIC
-
-config IA64_GENERIC
-	bool "generic"
-	select NUMA
-	select ACPI_NUMA
-	select SWIOTLB
-	select PCI_MSI
-	help
-	  This selects the system type of your hardware.  A "generic" kernel
-	  will run on any supported IA-64 system.  However, if you configure
-	  a kernel for your specific system, it will be faster and smaller.
-
-	  generic		For any supported IA-64 system
-	  DIG-compliant		For DIG ("Developer's Interface Guide") compliant systems
-	  DIG+Intel+IOMMU	For DIG systems with Intel IOMMU
-	  HP-zx1/sx1000		For HP systems
-	  HP-zx1/sx1000+swiotlb	For HP systems with (broken) DMA-constrained devices.
-	  SGI-SN2		For SGI Altix systems
-	  SGI-UV		For SGI UV systems
-	  Ski-simulator		For the HP simulator <http://www.hpl.hp.com/research/linux/ski/>
-
-	  If you don't know what to do, choose "generic".
-
-config IA64_DIG
-	bool "DIG-compliant"
-	select SWIOTLB
-
-config IA64_DIG_VTD
-	bool "DIG+Intel+IOMMU"
-	select INTEL_IOMMU
-	select PCI_MSI
-
-config IA64_HP_ZX1
-	bool "HP-zx1/sx1000"
-	help
-	  Build a kernel that runs on HP zx1 and sx1000 systems.  This adds
-	  support for the HP I/O MMU.
-
-config IA64_HP_ZX1_SWIOTLB
-	bool "HP-zx1/sx1000 with software I/O TLB"
-	select SWIOTLB
-	help
-	  Build a kernel that runs on HP zx1 and sx1000 systems even when they
-	  have broken PCI devices which cannot DMA to full 32 bits.  Apart
-	  from support for the HP I/O MMU, this includes support for the software
-	  I/O TLB, which allows supporting the broken devices at the expense of
-	  wasting some kernel memory (about 2MB by default).
-
-config IA64_SGI_SN2
-	bool "SGI-SN2"
-	select NUMA
-	select ACPI_NUMA
-	help
-	  Selecting this option will optimize the kernel for use on sn2 based
-	  systems, but the resulting kernel binary will not run on other
-	  types of ia64 systems.  If you have an SGI Altix system, it's safe
-	  to select this option.  If in doubt, select ia64 generic support
-	  instead.
-
-config IA64_SGI_UV
-	bool "SGI-UV"
-	select NUMA
-	select ACPI_NUMA
-	select SWIOTLB
-	help
-	  Selecting this option will optimize the kernel for use on UV based
-	  systems, but the resulting kernel binary will not run on other
-	  types of ia64 systems.  If you have an SGI UV system, it's safe
-	  to select this option.  If in doubt, select ia64 generic support
-	  instead.
-
-config IA64_HP_SIM
-	bool "Ski-simulator"
-	select SWIOTLB
-	depends on !PM
-
-endchoice
-
-choice
 	prompt "Processor type"
 	default ITANIUM
 
@@ -252,14 +174,7 @@ config IA64_PAGE_SIZE_64KB
 
 endchoice
 
-if IA64_HP_SIM
-config HZ
-	default 32
-endif
-
-if !IA64_HP_SIM
 source "kernel/Kconfig.hz"
-endif
 
 config IA64_BRL_EMU
 	bool
@@ -272,17 +187,26 @@ config IA64_L1_CACHE_SHIFT
 	default "7" if MCKINLEY
 	default "6" if ITANIUM
 
+config IA64_SGI_UV
+	bool "SGI-UV support"
+	help
+	  Selecting this option will add specific support for running on SGI
+	  UV based systems.  If you have an SGI UV system or are building a
+	  distro kernel, select this option.
+
+config IA64_HP_SBA_IOMMU
+	bool "HP SBA IOMMU support"
+	default y
+	help
+	  Say Y here to add support for the SBA IOMMU found on HP zx1 and
+	  sx1000 systems.  If you're unsure, answer Y.
+
 config IA64_CYCLONE
 	bool "Cyclone (EXA) Time Source support"
 	help
 	  Say Y here to enable support for IBM EXA Cyclone time source.
 	  If you're unsure, answer N.
 
-config IOSAPIC
-	bool
-	depends on !IA64_HP_SIM
-	default y
-
 config FORCE_MAX_ZONEORDER
 	int "MAX_ORDER (11 - 17)"  if !HUGETLB_PAGE
 	range 11 17  if !HUGETLB_PAGE
@@ -381,14 +305,12 @@ config ARCH_SPARSEMEM_ENABLE
 	select SPARSEMEM_VMEMMAP_ENABLE
 
 config ARCH_DISCONTIGMEM_DEFAULT
-	def_bool y if (IA64_SGI_SN2 || IA64_GENERIC || IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB)
+	def_bool y
 	depends on ARCH_DISCONTIGMEM_ENABLE
 
 config NUMA
 	bool "NUMA support"
-	depends on !IA64_HP_SIM && !FLATMEM
-	default y if IA64_SGI_SN2
-	select ACPI_NUMA if ACPI
+	depends on !FLATMEM
 	help
 	  Say Y to compile the kernel to support NUMA (Non-Uniform Memory
 	  Access).  This option is for configuring high-end multiprocessor
@@ -409,7 +331,7 @@ config NODES_SHIFT
 config VIRTUAL_MEM_MAP
 	bool "Virtual mem map"
 	depends on !SPARSEMEM
-	default y if !IA64_HP_SIM
+	default y
 	help
 	  Say Y to compile the kernel with support for a virtual mem map.
 	  This code also only takes effect if a memory hole of greater than
@@ -472,9 +394,6 @@ config IA64_MC_ERR_INJECT
 
 	  If you're unsure, do not select this option.
 
-config SGI_SN
-	def_bool y if (IA64_SGI_SN2 || IA64_GENERIC)
-
 config IA64_ESI
 	bool "ESI (Extensible SAL Interface) support"
 	help
@@ -493,11 +412,9 @@ config IA64_HP_AML_NFW
 	  the "force" module parameter, e.g., with the "aml_nfw.force"
 	  kernel command line option.
 
-source "drivers/sn/Kconfig"
-
 config KEXEC
 	bool "kexec system call"
-	depends on !IA64_HP_SIM && (!SMP || HOTPLUG_CPU)
+	depends on !SMP || HOTPLUG_CPU
 	select KEXEC_CORE
 	help
 	  kexec is a system call that implements the ability to shutdown your
@@ -515,7 +432,7 @@ config KEXEC
 
 config CRASH_DUMP
 	  bool "kernel crash dumps"
-	  depends on IA64_MCA_RECOVERY && !IA64_HP_SIM && (!SMP || HOTPLUG_CPU)
+	  depends on IA64_MCA_RECOVERY && (!SMP || HOTPLUG_CPU)
 	  help
 	    Generate crash dump after being started by kexec.
 
@@ -537,8 +454,6 @@ endif
 
 endmenu
 
-source "arch/ia64/hp/sim/Kconfig"
-
 config MSPEC
 	tristate "Memory special operations driver"
 	depends on IA64
diff --git a/arch/ia64/Kconfig.debug b/arch/ia64/Kconfig.debug
index 1371efc9b005..40ca23bd228d 100644
--- a/arch/ia64/Kconfig.debug
+++ b/arch/ia64/Kconfig.debug
@@ -14,7 +14,7 @@ config IA64_GRANULE_16MB
 
 config IA64_GRANULE_64MB
 	bool "64MB"
-	depends on !(IA64_GENERIC || IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_SGI_SN2)
+	depends on BROKEN
 
 endchoice
 
diff --git a/arch/ia64/Makefile b/arch/ia64/Makefile
index 171290f9f1de..e0bb2b6aaa35 100644
--- a/arch/ia64/Makefile
+++ b/arch/ia64/Makefile
@@ -39,29 +39,23 @@ $(error Sorry, you need a newer version of the assember, one that is built from
 		ftp://ftp.hpl.hp.com/pub/linux-ia64/gas-030124.tar.gz)
 endif
 
+quiet_cmd_gzip = GZIP    $@
+cmd_gzip = cat $(real-prereqs) | gzip -n -f -9 > $@
+
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
+
 KBUILD_CFLAGS += $(cflags-y)
 head-y := arch/ia64/kernel/head.o
 
 libs-y				+= arch/ia64/lib/
 core-y				+= arch/ia64/kernel/ arch/ia64/mm/
-core-$(CONFIG_IA64_DIG) 	+= arch/ia64/dig/
-core-$(CONFIG_IA64_DIG_VTD) 	+= arch/ia64/dig/
-core-$(CONFIG_IA64_GENERIC) 	+= arch/ia64/dig/
-core-$(CONFIG_IA64_HP_ZX1)	+= arch/ia64/dig/
-core-$(CONFIG_IA64_HP_ZX1_SWIOTLB) += arch/ia64/dig/
-core-$(CONFIG_IA64_SGI_SN2)	+= arch/ia64/sn/
 core-$(CONFIG_IA64_SGI_UV)	+= arch/ia64/uv/
 
-drivers-$(CONFIG_PCI)		+= arch/ia64/pci/
-drivers-$(CONFIG_IA64_HP_SIM)	+= arch/ia64/hp/sim/
-drivers-$(CONFIG_IA64_HP_ZX1)	+= arch/ia64/hp/common/ arch/ia64/hp/zx1/
-drivers-$(CONFIG_IA64_HP_ZX1_SWIOTLB) += arch/ia64/hp/common/ arch/ia64/hp/zx1/
-drivers-$(CONFIG_IA64_GENERIC)	+= arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ arch/ia64/sn/ arch/ia64/uv/
+drivers-y			+= arch/ia64/pci/ arch/ia64/hp/common/
 drivers-$(CONFIG_OPROFILE)	+= arch/ia64/oprofile/
 
-boot := arch/ia64/hp/sim/boot
-
-PHONY += boot compressed check
+PHONY += compressed check
 
 all: compressed unwcheck
 
@@ -69,22 +63,21 @@ compressed: vmlinux.gz
 
 vmlinuz: vmlinux.gz
 
-vmlinux.gz: vmlinux
-	$(Q)$(MAKE) $(build)=$(boot) $@
+vmlinux.gz: vmlinux.bin FORCE
+	$(call if_changed,gzip)
+
+vmlinux.bin: vmlinux FORCE
+	$(call if_changed,objcopy)
 
 unwcheck: vmlinux
 	-$(Q)READELF=$(READELF) $(PYTHON) $(srctree)/arch/ia64/scripts/unwcheck.py $<
 
 archclean:
-	$(Q)$(MAKE) $(clean)=$(boot)
 
 archheaders:
 	$(Q)$(MAKE) $(build)=arch/ia64/kernel/syscalls all
 
-CLEAN_FILES += vmlinux.gz bootloader
-
-boot:	lib/lib.a vmlinux
-	$(Q)$(MAKE) $(build)=$(boot) $@
+CLEAN_FILES += vmlinux.gz
 
 install: vmlinux.gz
 	sh $(srctree)/arch/ia64/install.sh $(KERNELRELEASE) $< System.map "$(INSTALL_PATH)"
@@ -92,7 +85,6 @@ install: vmlinux.gz
 define archhelp
   echo '* compressed	- Build compressed kernel image'
   echo '  install	- Install compressed kernel image'
-  echo '  boot		- Build vmlinux and bootloader for Ski simulator'
   echo '* unwcheck	- Check vmlinux for invalid unwind info'
 endef
 
diff --git a/arch/ia64/configs/bigsur_defconfig b/arch/ia64/configs/bigsur_defconfig
index b6bda1838629..b630bd7351c4 100644
--- a/arch/ia64/configs/bigsur_defconfig
+++ b/arch/ia64/configs/bigsur_defconfig
@@ -7,7 +7,6 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_SGI_PARTITION=y
-CONFIG_IA64_DIG=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig
index 81f686dee53c..661d90b3e148 100644
--- a/arch/ia64/configs/generic_defconfig
+++ b/arch/ia64/configs/generic_defconfig
@@ -44,14 +44,12 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
-CONFIG_SGI_IOC4=y
 CONFIG_SGI_XP=m
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_GENERIC=y
 CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_PIIX=y
-CONFIG_BLK_DEV_SGIIOC4=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=m
 CONFIG_BLK_DEV_SR=m
@@ -90,16 +88,11 @@ CONFIG_IGB=y
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_GAMEPORT=m
 CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_SGI_SNSC=y
-CONFIG_SGI_TIOCX=y
-CONFIG_SGI_MBCS=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=6
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_SGI_L1_CONSOLE=y
-CONFIG_SERIAL_SGI_IOC4=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_EFI_RTC=y
 CONFIG_RAW_DRIVER=m
@@ -107,7 +100,6 @@ CONFIG_HPET=y
 CONFIG_AGP=m
 CONFIG_AGP_I460=m
 CONFIG_AGP_HP_ZX1=m
-CONFIG_AGP_SGI_TIOCA=m
 CONFIG_DRM=m
 CONFIG_DRM_TDFX=m
 CONFIG_DRM_R128=m
diff --git a/arch/ia64/configs/gensparse_defconfig b/arch/ia64/configs/gensparse_defconfig
index 5b4fcdd51457..7844e6a956a4 100644
--- a/arch/ia64/configs/gensparse_defconfig
+++ b/arch/ia64/configs/gensparse_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPARSEMEM_MANUAL=y
 CONFIG_IA64_MCA_RECOVERY=y
 CONFIG_PERFMON=y
 CONFIG_IA64_PALINFO=y
-CONFIG_SGI_IOC3=y
 CONFIG_EFI_VARS=y
 CONFIG_BINFMT_MISC=m
 CONFIG_ACPI_BUTTON=m
@@ -37,14 +36,12 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
-CONFIG_SGI_IOC4=y
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_IDE_GENERIC=y
 CONFIG_BLK_DEV_GENERIC=y
 CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_PIIX=y
-CONFIG_BLK_DEV_SGIIOC4=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=m
@@ -79,17 +76,11 @@ CONFIG_E1000=y
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_GAMEPORT=m
 CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_SGI_SNSC=y
-CONFIG_SGI_TIOCX=y
-CONFIG_SGI_MBCS=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=6
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_SGI_L1_CONSOLE=y
-CONFIG_SERIAL_SGI_IOC4=y
-CONFIG_SERIAL_SGI_IOC3=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_EFI_RTC=y
 CONFIG_RAW_DRIVER=m
@@ -97,7 +88,6 @@ CONFIG_HPET=y
 CONFIG_AGP=m
 CONFIG_AGP_I460=m
 CONFIG_AGP_HP_ZX1=m
-CONFIG_AGP_SGI_TIOCA=m
 CONFIG_DRM=m
 CONFIG_DRM_TDFX=m
 CONFIG_DRM_R128=m
diff --git a/arch/ia64/configs/sim_defconfig b/arch/ia64/configs/sim_defconfig
deleted file mode 100644
index f0f69fdbddae..000000000000
--- a/arch/ia64/configs/sim_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_IA64_HP_SIM=y
-CONFIG_MCKINLEY=y
-CONFIG_IA64_PAGE_SIZE_64KB=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=64
-CONFIG_PREEMPT=y
-CONFIG_IA64_PALINFO=m
-CONFIG_EFI_VARS=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IPV6 is not set
-# CONFIG_STANDALONE is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_EFI_RTC=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_HP_SIMETH=y
-CONFIG_HP_SIMSERIAL=y
-CONFIG_HP_SIMSERIAL_CONSOLE=y
-CONFIG_HP_SIMSCSI=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_PROC_KCORE=y
-CONFIG_HUGETLBFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
diff --git a/arch/ia64/configs/tiger_defconfig b/arch/ia64/configs/tiger_defconfig
index 192ed157c9ce..1d6e2a01452b 100644
--- a/arch/ia64/configs/tiger_defconfig
+++ b/arch/ia64/configs/tiger_defconfig
@@ -12,7 +12,6 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_SGI_PARTITION=y
-CONFIG_IA64_DIG=y
 CONFIG_MCKINLEY=y
 CONFIG_IA64_PAGE_SIZE_64KB=y
 CONFIG_IA64_CYCLONE=y
diff --git a/arch/ia64/configs/zx1_defconfig b/arch/ia64/configs/zx1_defconfig
index b504c8e2fd52..8c92e095f8bb 100644
--- a/arch/ia64/configs/zx1_defconfig
+++ b/arch/ia64/configs/zx1_defconfig
@@ -4,7 +4,6 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_KPROBES=y
 CONFIG_MODULES=y
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_IA64_HP_ZX1=y
 CONFIG_MCKINLEY=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=16
diff --git a/arch/ia64/dig/Makefile b/arch/ia64/dig/Makefile
deleted file mode 100644
index e7f830825470..000000000000
--- a/arch/ia64/dig/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# ia64/platform/dig/Makefile
-#
-# Copyright (C) 1999 Silicon Graphics, Inc.
-# Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
-#
-
-obj-y := setup.o
-ifeq ($(CONFIG_INTEL_IOMMU), y)
-obj-$(CONFIG_IA64_GENERIC) += machvec.o machvec_vtd.o
-else
-obj-$(CONFIG_IA64_GENERIC) += machvec.o
-endif
-
diff --git a/arch/ia64/dig/machvec.c b/arch/ia64/dig/machvec.c
deleted file mode 100644
index 0c55bdafb473..000000000000
--- a/arch/ia64/dig/machvec.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define MACHVEC_PLATFORM_NAME		dig
-#define MACHVEC_PLATFORM_HEADER		<asm/machvec_dig.h>
-#include <asm/machvec_init.h>
diff --git a/arch/ia64/dig/machvec_vtd.c b/arch/ia64/dig/machvec_vtd.c
deleted file mode 100644
index 7cd3eb471cad..000000000000
--- a/arch/ia64/dig/machvec_vtd.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define MACHVEC_PLATFORM_NAME		dig_vtd
-#define MACHVEC_PLATFORM_HEADER		<asm/machvec_dig_vtd.h>
-#include <asm/machvec_init.h>
diff --git a/arch/ia64/dig/setup.c b/arch/ia64/dig/setup.c
deleted file mode 100644
index cc14fdce6db6..000000000000
--- a/arch/ia64/dig/setup.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Platform dependent support for DIG64 platforms.
- *
- * Copyright (C) 1999 Intel Corp.
- * Copyright (C) 1999, 2001 Hewlett-Packard Co
- * Copyright (C) 1999, 2001, 2003 David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1999 VA Linux Systems
- * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
- * Copyright (C) 1999 Vijay Chander <vijay@engr.sgi.com>
- */
-
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/kdev_t.h>
-#include <linux/string.h>
-#include <linux/screen_info.h>
-#include <linux/console.h>
-#include <linux/timex.h>
-#include <linux/sched.h>
-#include <linux/root_dev.h>
-
-#include <asm/io.h>
-#include <asm/machvec.h>
-#include <asm/setup.h>
-
-void __init
-dig_setup (char **cmdline_p)
-{
-	unsigned int orig_x, orig_y, num_cols, num_rows, font_height;
-
-	/*
-	 * Default to /dev/sda2.  This assumes that the EFI partition
-	 * is physical disk 1 partition 1 and the Linux root disk is
-	 * physical disk 1 partition 2.
-	 */
-	ROOT_DEV = Root_SDA2;		/* default to second partition on first drive */
-
-#ifdef CONFIG_SMP
-	init_smp_config();
-#endif
-
-	memset(&screen_info, 0, sizeof(screen_info));
-
-	if (!ia64_boot_param->console_info.num_rows
-	    || !ia64_boot_param->console_info.num_cols)
-	{
-		printk(KERN_WARNING "dig_setup: warning: invalid screen-info, guessing 80x25\n");
-		orig_x = 0;
-		orig_y = 0;
-		num_cols = 80;
-		num_rows = 25;
-		font_height = 16;
-	} else {
-		orig_x = ia64_boot_param->console_info.orig_x;
-		orig_y = ia64_boot_param->console_info.orig_y;
-		num_cols = ia64_boot_param->console_info.num_cols;
-		num_rows = ia64_boot_param->console_info.num_rows;
-		font_height = 400 / num_rows;
-	}
-
-	screen_info.orig_x = orig_x;
-	screen_info.orig_y = orig_y;
-	screen_info.orig_video_cols  = num_cols;
-	screen_info.orig_video_lines = num_rows;
-	screen_info.orig_video_points = font_height;
-	screen_info.orig_video_mode = 3;	/* XXX fake */
-	screen_info.orig_video_isVGA = 1;	/* XXX fake */
-	screen_info.orig_video_ega_bx = 3;	/* XXX fake */
-}
diff --git a/arch/ia64/hp/common/Makefile b/arch/ia64/hp/common/Makefile
index 6026308f9a62..11a56ed38229 100644
--- a/arch/ia64/hp/common/Makefile
+++ b/arch/ia64/hp/common/Makefile
@@ -6,7 +6,5 @@
 # Copyright (C) Alex Williamson (alex_williamson@hp.com)
 #
 
-obj-y := sba_iommu.o
-obj-$(CONFIG_IA64_HP_ZX1_SWIOTLB) += hwsw_iommu.o
-obj-$(CONFIG_IA64_GENERIC) += hwsw_iommu.o
+obj-$(CONFIG_IA64_HP_SBA_IOMMU) += sba_iommu.o
 obj-$(CONFIG_IA64_HP_AML_NFW) += aml_nfw.o
diff --git a/arch/ia64/hp/common/hwsw_iommu.c b/arch/ia64/hp/common/hwsw_iommu.c
deleted file mode 100644
index 8840ed97712f..000000000000
--- a/arch/ia64/hp/common/hwsw_iommu.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2004 Hewlett-Packard Development Company, L.P.
- *   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
- *
- * This is a pseudo I/O MMU which dispatches to the hardware I/O MMU
- * whenever possible.  We assume that the hardware I/O MMU requires
- * full 32-bit addressability, as is the case, e.g., for HP zx1-based
- * systems (there, the I/O MMU window is mapped at 3-4GB).  If a
- * device doesn't provide full 32-bit addressability, we fall back on
- * the sw I/O TLB.  This is good enough to let us support broken
- * hardware such as soundcards which have a DMA engine that can
- * address only 28 bits.
- */
-
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/swiotlb.h>
-#include <linux/export.h>
-#include <asm/machvec.h>
-
-extern const struct dma_map_ops sba_dma_ops;
-
-/* swiotlb declarations & definitions: */
-extern int swiotlb_late_init_with_default_size (size_t size);
-
-/*
- * Note: we need to make the determination of whether or not to use
- * the sw I/O TLB based purely on the device structure.  Anything else
- * would be unreliable or would be too intrusive.
- */
-static inline int use_swiotlb(struct device *dev)
-{
-	return dev && dev->dma_mask &&
-		!sba_dma_ops.dma_supported(dev, *dev->dma_mask);
-}
-
-const struct dma_map_ops *hwsw_dma_get_ops(struct device *dev)
-{
-	if (use_swiotlb(dev))
-		return NULL;
-	return &sba_dma_ops;
-}
-EXPORT_SYMBOL(hwsw_dma_get_ops);
-
-void __init
-hwsw_init (void)
-{
-	/* default to a smallish 2MB sw I/O TLB */
-	if (swiotlb_late_init_with_default_size (2 * (1<<20)) != 0) {
-#ifdef CONFIG_IA64_GENERIC
-		/* Better to have normal DMA than panic */
-		printk(KERN_WARNING "%s: Failed to initialize software I/O TLB,"
-		       " reverting to hpzx1 platform vector\n", __func__);
-		machvec_init("hpzx1");
-#else
-		panic("Unable to initialize software I/O TLB services");
-#endif
-	}
-}
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index 3d24cc43385b..a7eff5e6d260 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -35,6 +35,7 @@
 #include <linux/iommu-helper.h>
 #include <linux/dma-mapping.h>
 #include <linux/prefetch.h>
+#include <linux/swiotlb.h>
 
 #include <asm/delay.h>		/* ia64_get_itc() */
 #include <asm/io.h>
@@ -43,8 +44,6 @@
 
 #include <asm/acpi-ext.h>
 
-extern int swiotlb_late_init_with_default_size (size_t size);
-
 #define PFX "IOC: "
 
 /*
@@ -251,12 +250,8 @@ static SBA_INLINE void sba_free_range(struct ioc *, dma_addr_t, size_t);
 static u64 prefetch_spill_page;
 #endif
 
-#ifdef CONFIG_PCI
-# define GET_IOC(dev)	((dev_is_pci(dev))						\
+#define GET_IOC(dev)	((dev_is_pci(dev))						\
 			 ? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL)
-#else
-# define GET_IOC(dev)	NULL
-#endif
 
 /*
 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
@@ -1741,9 +1736,7 @@ ioc_sac_init(struct ioc *ioc)
 	controller->iommu = ioc;
 	sac->sysdata = controller;
 	sac->dma_mask = 0xFFFFFFFFUL;
-#ifdef CONFIG_PCI
 	sac->dev.bus = &pci_bus_type;
-#endif
 	ioc->sac_only_dev = sac;
 }
 
@@ -2062,27 +2055,33 @@ static int __init acpi_sba_ioc_init_acpi(void)
 /* This has to run before acpi_scan_init(). */
 arch_initcall(acpi_sba_ioc_init_acpi);
 
+static int sba_dma_supported (struct device *dev, u64 mask)
+{
+	/* make sure it's at least 32bit capable */
+	return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL);
+}
+
+static const struct dma_map_ops sba_dma_ops = {
+	.alloc			= sba_alloc_coherent,
+	.free			= sba_free_coherent,
+	.map_page		= sba_map_page,
+	.unmap_page		= sba_unmap_page,
+	.map_sg			= sba_map_sg_attrs,
+	.unmap_sg		= sba_unmap_sg_attrs,
+	.dma_supported		= sba_dma_supported,
+};
+
 static int __init
 sba_init(void)
 {
-	if (!ia64_platform_is("hpzx1") && !ia64_platform_is("hpzx1_swiotlb"))
-		return 0;
-
-#if defined(CONFIG_IA64_GENERIC)
-	/* If we are booting a kdump kernel, the sba_iommu will
-	 * cause devices that were not shutdown properly to MCA
-	 * as soon as they are turned back on.  Our only option for
-	 * a successful kdump kernel boot is to use the swiotlb.
+	/*
+	 * If we are booting a kdump kernel, the sba_iommu will cause devices
+	 * that were not shutdown properly to MCA as soon as they are turned
+	 * back on.  Our only option for a successful kdump kernel boot is to
+	 * use swiotlb.
 	 */
-	if (is_kdump_kernel()) {
-		dma_ops = NULL;
-		if (swiotlb_late_init_with_default_size(64 * (1<<20)) != 0)
-			panic("Unable to initialize software I/O TLB:"
-				  " Try machvec=dig boot option");
-		machvec_init("dig");
+	if (is_kdump_kernel())
 		return 0;
-	}
-#endif
 
 	/*
 	 * ioc_found should be populated by the acpi_sba_ioc_handler's .attach()
@@ -2091,43 +2090,18 @@ sba_init(void)
 	while (ioc_found)
 		acpi_sba_ioc_add(ioc_found);
 
-	if (!ioc_list) {
-#ifdef CONFIG_IA64_GENERIC
-		/*
-		 * If we didn't find something sba_iommu can claim, we
-		 * need to setup the swiotlb and switch to the dig machvec.
-		 */
-		dma_ops = NULL;
-		if (swiotlb_late_init_with_default_size(64 * (1<<20)) != 0)
-			panic("Unable to find SBA IOMMU or initialize "
-			      "software I/O TLB: Try machvec=dig boot option");
-		machvec_init("dig");
-#else
-		panic("Unable to find SBA IOMMU: Try a generic or DIG kernel");
-#endif
+	if (!ioc_list)
 		return 0;
-	}
 
-#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_HP_ZX1_SWIOTLB)
-	/*
-	 * hpzx1_swiotlb needs to have a fairly small swiotlb bounce
-	 * buffer setup to support devices with smaller DMA masks than
-	 * sba_iommu can handle.
-	 */
-	if (ia64_platform_is("hpzx1_swiotlb")) {
-		extern void hwsw_init(void);
-
-		hwsw_init();
-	}
-#endif
-
-#ifdef CONFIG_PCI
 	{
 		struct pci_bus *b = NULL;
 		while ((b = pci_find_next_bus(b)) != NULL)
 			sba_connect_bus(b);
 	}
-#endif
+
+	/* no need for swiotlb with the iommu */
+	swiotlb_exit();
+	dma_ops = &sba_dma_ops;
 
 #ifdef CONFIG_PROC_FS
 	ioc_proc_init();
@@ -2144,12 +2118,6 @@ nosbagart(char *str)
 	return 1;
 }
 
-static int sba_dma_supported (struct device *dev, u64 mask)
-{
-	/* make sure it's at least 32bit capable */
-	return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL);
-}
-
 __setup("nosbagart", nosbagart);
 
 static int __init
@@ -2174,18 +2142,3 @@ sba_page_override(char *str)
 }
 
 __setup("sbapagesize=",sba_page_override);
-
-const struct dma_map_ops sba_dma_ops = {
-	.alloc			= sba_alloc_coherent,
-	.free			= sba_free_coherent,
-	.map_page		= sba_map_page,
-	.unmap_page		= sba_unmap_page,
-	.map_sg			= sba_map_sg_attrs,
-	.unmap_sg		= sba_unmap_sg_attrs,
-	.dma_supported		= sba_dma_supported,
-};
-
-void sba_dma_init(void)
-{
-	dma_ops = &sba_dma_ops;
-}
diff --git a/arch/ia64/hp/sim/Kconfig b/arch/ia64/hp/sim/Kconfig
deleted file mode 100644
index 56fb4f1d4f7c..000000000000
--- a/arch/ia64/hp/sim/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-
-menu "HP Simulator drivers"
-	depends on IA64_HP_SIM || IA64_GENERIC
-
-config HP_SIMETH
-	bool "Simulated Ethernet "
-	depends on NET
-
-config HP_SIMSERIAL
-	bool "Simulated serial driver support"
-	depends on TTY
-
-config HP_SIMSERIAL_CONSOLE
-	bool "Console for HP simulator"
-	depends on HP_SIMSERIAL
-
-config HP_SIMSCSI
-	bool "Simulated SCSI disk"
-	depends on SCSI=y
-
-endmenu
-
diff --git a/arch/ia64/hp/sim/Makefile b/arch/ia64/hp/sim/Makefile
deleted file mode 100644
index 0224a13d2c5b..000000000000
--- a/arch/ia64/hp/sim/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# ia64/platform/hp/sim/Makefile
-#
-# Copyright (C) 2002 Hewlett-Packard Co.
-#	David Mosberger-Tang <davidm@hpl.hp.com>
-# Copyright (C) 1999 Silicon Graphics, Inc.
-# Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
-#
-
-obj-y := hpsim_irq.o hpsim_setup.o hpsim.o
-obj-$(CONFIG_IA64_GENERIC) += hpsim_machvec.o
-
-obj-$(CONFIG_HP_SIMETH)	+= simeth.o
-obj-$(CONFIG_HP_SIMSERIAL) += simserial.o
-obj-$(CONFIG_HP_SIMSERIAL_CONSOLE) += hpsim_console.o
-obj-$(CONFIG_HP_SIMSCSI) += simscsi.o
diff --git a/arch/ia64/hp/sim/boot/Makefile b/arch/ia64/hp/sim/boot/Makefile
deleted file mode 100644
index df6e9968c845..000000000000
--- a/arch/ia64/hp/sim/boot/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-#
-# ia64/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1998, 2003 by David Mosberger-Tang <davidm@hpl.hp.com>
-#
-
-targets-$(CONFIG_IA64_HP_SIM)  += bootloader
-targets := vmlinux.bin vmlinux.gz $(targets-y)
-
-quiet_cmd_cptotop = LN      $@
-      cmd_cptotop = ln -f $< $@
-
-vmlinux.gz: $(obj)/vmlinux.gz $(addprefix $(obj)/,$(targets-y))
-	$(call cmd,cptotop)
-	@echo '  Kernel: $@ is ready'
-
-boot: bootloader
-
-bootloader: $(obj)/bootloader
-	$(call cmd,cptotop)
-
-$(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE
-	$(call if_changed,gzip)
-
-$(obj)/vmlinux.bin: vmlinux FORCE
-	$(call if_changed,objcopy)
-
-
-LDFLAGS_bootloader = -static -T
-
-$(obj)/bootloader: $(src)/bootloader.lds $(obj)/bootloader.o $(obj)/boot_head.o $(obj)/fw-emu.o \
-                   lib/lib.a arch/ia64/lib/lib.a FORCE
-	$(call if_changed,ld)
diff --git a/arch/ia64/hp/sim/boot/boot_head.S b/arch/ia64/hp/sim/boot/boot_head.S
deleted file mode 100644
index a7d178fb41e8..000000000000
--- a/arch/ia64/hp/sim/boot/boot_head.S
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 1998-2003 Hewlett-Packard Co
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- */
-
-#include <asm/asmmacro.h>
-#include <asm/pal.h>
-
-	.bss
-	.align 16
-stack_mem:
-	.skip 16834
-
-	.text
-
-/* This needs to be defined because lib/string.c:strlcat() calls it in case of error... */
-GLOBAL_ENTRY(printk)
-	break 0
-END(printk)
-
-GLOBAL_ENTRY(_start)
-	.prologue
-	.save rp, r0
-	.body
-	movl gp = __gp
-	movl sp = stack_mem+16384-16
-	bsw.1
-	br.call.sptk.many rp=start_bootloader
-0:	nop 0		  /* dummy nop to make unwinding work */
-END(_start)
-
-/*
- * Set a break point on this function so that symbols are available to set breakpoints in
- * the kernel being debugged.
- */
-GLOBAL_ENTRY(debug_break)
-	br.ret.sptk.many b0
-END(debug_break)
-
-GLOBAL_ENTRY(ssc)
-	.regstk 5,0,0,0
-	mov r15=in4
-	break 0x80001
-	br.ret.sptk.many b0
-END(ssc)
-
-GLOBAL_ENTRY(jmp_to_kernel)
-	.regstk 2,0,0,0
-	mov r28=in0
-	mov b7=in1
-	br.sptk.few b7
-END(jmp_to_kernel)
-
-/*
- * r28 contains the index of the PAL function
- * r29--31 the args
- * Return values in ret0--3 (r8--11)
- */
-GLOBAL_ENTRY(pal_emulator_static)
-	mov r8=-1
-	mov r9=256
-	;;
-	cmp.gtu p6,p7=r9,r28		/* r28 <= 255? */
-(p6)	br.cond.sptk.few static
-	;;
-	mov r9=512
-	;;
-	cmp.gtu p6,p7=r9,r28
-(p6)	br.cond.sptk.few stacked
-	;;
-static:	cmp.eq p6,p7=PAL_PTCE_INFO,r28
-(p7)	br.cond.sptk.few 1f
-	;;
-	mov r8=0			/* status = 0 */
-	movl r9=0x100000000		/* tc.base */
-	movl r10=0x0000000200000003	/* count[0], count[1] */
-	movl r11=0x1000000000002000	/* stride[0], stride[1] */
-	br.cond.sptk.few rp
-1:	cmp.eq p6,p7=PAL_FREQ_RATIOS,r28
-(p7)	br.cond.sptk.few 1f
-	mov r8=0			/* status = 0 */
-	movl r9 =0x100000064		/* proc_ratio (1/100) */
-	movl r10=0x100000100		/* bus_ratio<<32 (1/256) */
-	movl r11=0x100000064		/* itc_ratio<<32 (1/100) */
-	;;
-1:	cmp.eq p6,p7=PAL_RSE_INFO,r28
-(p7)	br.cond.sptk.few 1f
-	mov r8=0			/* status = 0 */
-	mov r9=96			/* num phys stacked */
-	mov r10=0			/* hints */
-	mov r11=0
-	br.cond.sptk.few rp
-1:	cmp.eq p6,p7=PAL_CACHE_FLUSH,r28		/* PAL_CACHE_FLUSH */
-(p7)	br.cond.sptk.few 1f
-	mov r9=ar.lc
-	movl r8=524288			/* flush 512k million cache lines (16MB) */
-	;;
-	mov ar.lc=r8
-	movl r8=0xe000000000000000
-	;;
-.loop:	fc r8
-	add r8=32,r8
-	br.cloop.sptk.few .loop
-	sync.i
-	;;
-	srlz.i
-	;;
-	mov ar.lc=r9
-	mov r8=r0
-	;;
-1:	cmp.eq p6,p7=PAL_PERF_MON_INFO,r28
-(p7)	br.cond.sptk.few 1f
-	mov r8=0			/* status = 0 */
-	movl r9 =0x08122f04		/* generic=4 width=47 retired=8 cycles=18 */
-	mov r10=0			/* reserved */
-	mov r11=0			/* reserved */
-	mov r16=0xffff			/* implemented PMC */
-	mov r17=0x3ffff			/* implemented PMD */
-	add r18=8,r29			/* second index */
-	;;
-	st8 [r29]=r16,16		/* store implemented PMC */
-	st8 [r18]=r0,16			/* clear remaining bits  */
-	;;
-	st8 [r29]=r0,16			/* clear remaining bits  */
-	st8 [r18]=r0,16			/* clear remaining bits  */
-	;;
-	st8 [r29]=r17,16		/* store implemented PMD */
-	st8 [r18]=r0,16			/* clear remaining bits  */
-	mov r16=0xf0			/* cycles count capable PMC */
-	;;
-	st8 [r29]=r0,16			/* clear remaining bits  */
-	st8 [r18]=r0,16			/* clear remaining bits  */
-	mov r17=0xf0			/* retired bundles capable PMC */
-	;;
-	st8 [r29]=r16,16		/* store cycles capable */
-	st8 [r18]=r0,16			/* clear remaining bits  */
-	;;
-	st8 [r29]=r0,16			/* clear remaining bits  */
-	st8 [r18]=r0,16			/* clear remaining bits  */
-	;;
-	st8 [r29]=r17,16		/* store retired bundle capable */
-	st8 [r18]=r0,16			/* clear remaining bits  */
-	;;
-	st8 [r29]=r0,16			/* clear remaining bits  */
-	st8 [r18]=r0,16			/* clear remaining bits  */
-	;;
-1:	cmp.eq p6,p7=PAL_VM_SUMMARY,r28
-(p7)	br.cond.sptk.few 1f
-	mov	r8=0			/* status = 0  */
-	movl	r9=0x2044040020F1865	/* num_tc_levels=2, num_unique_tcs=4 */
-					/* max_itr_entry=64, max_dtr_entry=64 */
-					/* hash_tag_id=2, max_pkr=15 */
-					/* key_size=24, phys_add_size=50, vw=1 */
-	movl	r10=0x183C		/* rid_size=24, impl_va_msb=60 */
-	;;
-1:	cmp.eq p6,p7=PAL_MEM_ATTRIB,r28
-(p7)	br.cond.sptk.few 1f
-	mov	r8=0			/* status = 0 */
-	mov	r9=0x80|0x01		/* NatPage|WB */
-	;;
-1:	br.cond.sptk.few rp
-stacked:
-	br.ret.sptk.few rp
-END(pal_emulator_static)
diff --git a/arch/ia64/hp/sim/boot/bootloader.c b/arch/ia64/hp/sim/boot/bootloader.c
deleted file mode 100644
index 6d804608dc81..000000000000
--- a/arch/ia64/hp/sim/boot/bootloader.c
+++ /dev/null
@@ -1,175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/ia64/hp/sim/boot/bootloader.c
- *
- * Loads an ELF kernel.
- *
- * Copyright (C) 1998-2003 Hewlett-Packard Co
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- *	Stephane Eranian <eranian@hpl.hp.com>
- *
- * 01/07/99 S.Eranian modified to pass command line arguments to kernel
- */
-struct task_struct;	/* forward declaration for elf.h */
-
-#include <linux/elf.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-
-#include <asm/elf.h>
-#include <asm/intrinsics.h>
-#include <asm/pal.h>
-#include <asm/pgtable.h>
-#include <asm/sal.h>
-
-#include "ssc.h"
-
-struct disk_req {
-	unsigned long addr;
-	unsigned len;
-};
-
-struct disk_stat {
-	int fd;
-	unsigned count;
-};
-
-extern void jmp_to_kernel (unsigned long bp, unsigned long e_entry);
-extern struct ia64_boot_param *sys_fw_init (const char *args, int arglen);
-extern void debug_break (void);
-
-static void
-cons_write (const char *buf)
-{
-	unsigned long ch;
-
-	while ((ch = *buf++) != '\0') {
-		ssc(ch, 0, 0, 0, SSC_PUTCHAR);
-		if (ch == '\n')
-		  ssc('\r', 0, 0, 0, SSC_PUTCHAR);
-	}
-}
-
-#define MAX_ARGS 32
-
-void
-start_bootloader (void)
-{
-	static char mem[4096];
-	static char buffer[1024];
-	unsigned long off;
-	int fd, i;
-	struct disk_req req;
-	struct disk_stat stat;
-	struct elfhdr *elf;
-	struct elf_phdr *elf_phdr;	/* program header */
-	unsigned long e_entry, e_phoff, e_phnum;
-	register struct ia64_boot_param *bp;
-	char *kpath, *args;
-	long arglen = 0;
-
-	ssc(0, 0, 0, 0, SSC_CONSOLE_INIT);
-
-	/*
-	 * S.Eranian: extract the commandline argument from the simulator
-	 *
-	 * The expected format is as follows:
-         *
-	 *	kernelname args...
-	 *
-	 * Both are optional but you can't have the second one without the first.
-	 */
-	arglen = ssc((long) buffer, 0, 0, 0, SSC_GET_ARGS);
-
-	kpath = "vmlinux";
-	args = buffer;
-	if (arglen > 0) {
-		kpath = buffer;
-		while (*args != ' ' && *args != '\0')
-			++args, --arglen;
-		if (*args == ' ')
-			*args++ = '\0', --arglen;
-	}
-
-	if (arglen <= 0) {
-		args = "";
-		arglen = 1;
-	}
-
-	fd = ssc((long) kpath, 1, 0, 0, SSC_OPEN);
-
-	if (fd < 0) {
-		cons_write(kpath);
-		cons_write(": file not found, reboot now\n");
-		for(;;);
-	}
-	stat.fd = fd;
-	off = 0;
-
-	req.len = sizeof(mem);
-	req.addr = (long) mem;
-	ssc(fd, 1, (long) &req, off, SSC_READ);
-	ssc((long) &stat, 0, 0, 0, SSC_WAIT_COMPLETION);
-
-	elf = (struct elfhdr *) mem;
-	if (elf->e_ident[0] == 0x7f && strncmp(elf->e_ident + 1, "ELF", 3) != 0) {
-		cons_write("not an ELF file\n");
-		return;
-	}
-	if (elf->e_type != ET_EXEC) {
-		cons_write("not an ELF executable\n");
-		return;
-	}
-	if (!elf_check_arch(elf)) {
-		cons_write("kernel not for this processor\n");
-		return;
-	}
-
-	e_entry = elf->e_entry;
-	e_phnum = elf->e_phnum;
-	e_phoff = elf->e_phoff;
-
-	cons_write("loading ");
-	cons_write(kpath);
-	cons_write("...\n");
-
-	for (i = 0; i < e_phnum; ++i) {
-		req.len = sizeof(*elf_phdr);
-		req.addr = (long) mem;
-		ssc(fd, 1, (long) &req, e_phoff, SSC_READ);
-		ssc((long) &stat, 0, 0, 0, SSC_WAIT_COMPLETION);
-		if (stat.count != sizeof(*elf_phdr)) {
-			cons_write("failed to read phdr\n");
-			return;
-		}
-		e_phoff += sizeof(*elf_phdr);
-
-		elf_phdr = (struct elf_phdr *) mem;
-
-		if (elf_phdr->p_type != PT_LOAD)
-			continue;
-
-		req.len = elf_phdr->p_filesz;
-		req.addr = __pa(elf_phdr->p_paddr);
-		ssc(fd, 1, (long) &req, elf_phdr->p_offset, SSC_READ);
-		ssc((long) &stat, 0, 0, 0, SSC_WAIT_COMPLETION);
-		memset((char *)__pa(elf_phdr->p_paddr) + elf_phdr->p_filesz, 0,
-		       elf_phdr->p_memsz - elf_phdr->p_filesz);
-	}
-	ssc(fd, 0, 0, 0, SSC_CLOSE);
-
-	cons_write("starting kernel...\n");
-
-	/* fake an I/O base address: */
-	ia64_setreg(_IA64_REG_AR_KR0, 0xffffc000000UL);
-
-	bp = sys_fw_init(args, arglen);
-
-	ssc(0, (long) kpath, 0, 0, SSC_LOAD_SYMBOLS);
-
-	debug_break();
-	jmp_to_kernel((unsigned long) bp, e_entry);
-
-	cons_write("kernel returned!\n");
-	ssc(-1, 0, 0, 0, SSC_EXIT);
-}
diff --git a/arch/ia64/hp/sim/boot/bootloader.lds b/arch/ia64/hp/sim/boot/bootloader.lds
deleted file mode 100644
index f3f284d6514c..000000000000
--- a/arch/ia64/hp/sim/boot/bootloader.lds
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-OUTPUT_FORMAT("elf64-ia64-little")
-OUTPUT_ARCH(ia64)
-ENTRY(_start)
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = 0x100000;
-
-  _text = .;
-  .text : { *(__ivt_section) *(.text) }
-  _etext = .;
-
-  /* Global data */
-  _data = .;
-  .rodata : { *(.rodata) *(.rodata.*) }
-  .data    : { *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS }
-  __gp = ALIGN (8) + 0x200000;
-  .got           : { *(.got.plt) *(.got) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata     : { *(.sdata) }
-  _edata  =  .;
-
-  __bss_start = .;
-  .sbss      : { *(.sbss) *(.scommon) }
-  .bss       : { *(.bss) *(COMMON) }
-  . = ALIGN(64 / 8);
-  __bss_stop = .;
-  _end = . ;
-
-  /* Stabs debugging sections.  */
-  .stab 0 : { *(.stab) }
-  .stabstr 0 : { *(.stabstr) }
-  .stab.excl 0 : { *(.stab.excl) }
-  .stab.exclstr 0 : { *(.stab.exclstr) }
-  .stab.index 0 : { *(.stab.index) }
-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  .comment 0 : { *(.comment) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-  /* These must appear regardless of  .  */
-}
diff --git a/arch/ia64/hp/sim/boot/fw-emu.c b/arch/ia64/hp/sim/boot/fw-emu.c
deleted file mode 100644
index 517fb2822e04..000000000000
--- a/arch/ia64/hp/sim/boot/fw-emu.c
+++ /dev/null
@@ -1,374 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * PAL & SAL emulation.
- *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- */
-
-#ifdef CONFIG_PCI
-# include <linux/pci.h>
-#endif
-
-#include <linux/efi.h>
-#include <asm/io.h>
-#include <asm/pal.h>
-#include <asm/sal.h>
-#include <asm/setup.h>
-
-#include "ssc.h"
-
-#define MB	(1024*1024UL)
-
-#define SIMPLE_MEMMAP	1
-
-#if SIMPLE_MEMMAP
-# define NUM_MEM_DESCS	4
-#else
-# define NUM_MEM_DESCS	16
-#endif
-
-static char fw_mem[(  sizeof(struct ia64_boot_param)
-		    + sizeof(efi_system_table_t)
-		    + sizeof(efi_runtime_services_t)
-		    + 1*sizeof(efi_config_table_t)
-		    + sizeof(struct ia64_sal_systab)
-		    + sizeof(struct ia64_sal_desc_entry_point)
-		    + NUM_MEM_DESCS*(sizeof(efi_memory_desc_t))
-		    + 1024)] __attribute__ ((aligned (8)));
-
-#define SECS_PER_HOUR   (60 * 60)
-#define SECS_PER_DAY    (SECS_PER_HOUR * 24)
-
-/* Compute the `struct tm' representation of *T,
-   offset OFFSET seconds east of UTC,
-   and store year, yday, mon, mday, wday, hour, min, sec into *TP.
-   Return nonzero if successful.  */
-int
-offtime (unsigned long t, efi_time_t *tp)
-{
-	const unsigned short int __mon_yday[2][13] =
-	{
-		/* Normal years.  */
-		{ 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365 },
-		/* Leap years.  */
-		{ 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335, 366 }
-	};
-	long int days, rem, y;
-	const unsigned short int *ip;
-
-	days = t / SECS_PER_DAY;
-	rem = t % SECS_PER_DAY;
-	while (rem < 0) {
-		rem += SECS_PER_DAY;
-		--days;
-	}
-	while (rem >= SECS_PER_DAY) {
-		rem -= SECS_PER_DAY;
-		++days;
-	}
-	tp->hour = rem / SECS_PER_HOUR;
-	rem %= SECS_PER_HOUR;
-	tp->minute = rem / 60;
-	tp->second = rem % 60;
-	/* January 1, 1970 was a Thursday.  */
-	y = 1970;
-
-#	define DIV(a, b) ((a) / (b) - ((a) % (b) < 0))
-#	define LEAPS_THRU_END_OF(y) (DIV (y, 4) - DIV (y, 100) + DIV (y, 400))
-#	define __isleap(year) \
-	  ((year) % 4 == 0 && ((year) % 100 != 0 || (year) % 400 == 0))
-
-	while (days < 0 || days >= (__isleap (y) ? 366 : 365)) {
-		/* Guess a corrected year, assuming 365 days per year.  */
-		long int yg = y + days / 365 - (days % 365 < 0);
-
-		/* Adjust DAYS and Y to match the guessed year.  */
-		days -= ((yg - y) * 365 + LEAPS_THRU_END_OF (yg - 1)
-			 - LEAPS_THRU_END_OF (y - 1));
-		y = yg;
-	}
-	tp->year = y;
-	ip = __mon_yday[__isleap(y)];
-	for (y = 11; days < (long int) ip[y]; --y)
-		continue;
-	days -= ip[y];
-	tp->month = y + 1;
-	tp->day = days + 1;
-	return 1;
-}
-
-extern void pal_emulator_static (void);
-
-/* Macro to emulate SAL call using legacy IN and OUT calls to CF8, CFC etc.. */
-
-#define BUILD_CMD(addr)		((0x80000000 | (addr)) & ~3)
-
-#define REG_OFFSET(addr)	(0x00000000000000FF & (addr))
-#define DEVICE_FUNCTION(addr)	(0x000000000000FF00 & (addr))
-#define BUS_NUMBER(addr)	(0x0000000000FF0000 & (addr))
-
-static efi_status_t
-fw_efi_get_time (efi_time_t *tm, efi_time_cap_t *tc)
-{
-#if defined(CONFIG_IA64_HP_SIM) || defined(CONFIG_IA64_GENERIC)
-	struct {
-		int tv_sec;	/* must be 32bits to work */
-		int tv_usec;
-	} tv32bits;
-
-	ssc((unsigned long) &tv32bits, 0, 0, 0, SSC_GET_TOD);
-
-	memset(tm, 0, sizeof(*tm));
-	offtime(tv32bits.tv_sec, tm);
-
-	if (tc)
-		memset(tc, 0, sizeof(*tc));
-#else
-#	error Not implemented yet...
-#endif
-	return EFI_SUCCESS;
-}
-
-static void
-efi_reset_system (int reset_type, efi_status_t status, unsigned long data_size, efi_char16_t *data)
-{
-#if defined(CONFIG_IA64_HP_SIM) || defined(CONFIG_IA64_GENERIC)
-	ssc(status, 0, 0, 0, SSC_EXIT);
-#else
-#	error Not implemented yet...
-#endif
-}
-
-static efi_status_t
-efi_unimplemented (void)
-{
-	return EFI_UNSUPPORTED;
-}
-
-static struct sal_ret_values
-sal_emulator (long index, unsigned long in1, unsigned long in2,
-	      unsigned long in3, unsigned long in4, unsigned long in5,
-	      unsigned long in6, unsigned long in7)
-{
-	long r9  = 0;
-	long r10 = 0;
-	long r11 = 0;
-	long status;
-
-	/*
-	 * Don't do a "switch" here since that gives us code that
-	 * isn't self-relocatable.
-	 */
-	status = 0;
-	if (index == SAL_FREQ_BASE) {
-		if (in1 == SAL_FREQ_BASE_PLATFORM)
-			r9 = 200000000;
-		else if (in1 == SAL_FREQ_BASE_INTERVAL_TIMER) {
-			/*
-			 * Is this supposed to be the cr.itc frequency
-			 * or something platform specific?  The SAL
-			 * doc ain't exactly clear on this...
-			 */
-			r9 = 700000000;
-		} else if (in1 == SAL_FREQ_BASE_REALTIME_CLOCK)
-			r9 = 1;
-		else
-			status = -1;
-	} else if (index == SAL_SET_VECTORS) {
-		;
-	} else if (index == SAL_GET_STATE_INFO) {
-		;
-	} else if (index == SAL_GET_STATE_INFO_SIZE) {
-		;
-	} else if (index == SAL_CLEAR_STATE_INFO) {
-		;
-	} else if (index == SAL_MC_RENDEZ) {
-		;
-	} else if (index == SAL_MC_SET_PARAMS) {
-		;
-	} else if (index == SAL_CACHE_FLUSH) {
-		;
-	} else if (index == SAL_CACHE_INIT) {
-		;
-#ifdef CONFIG_PCI
-	} else if (index == SAL_PCI_CONFIG_READ) {
-		/*
-		 * in1 contains the PCI configuration address and in2
-		 * the size of the read.  The value that is read is
-		 * returned via the general register r9.
-		 */
-                outl(BUILD_CMD(in1), 0xCF8);
-                if (in2 == 1)                           /* Reading byte  */
-                        r9 = inb(0xCFC + ((REG_OFFSET(in1) & 3)));
-                else if (in2 == 2)                      /* Reading word  */
-                        r9 = inw(0xCFC + ((REG_OFFSET(in1) & 2)));
-                else                                    /* Reading dword */
-                        r9 = inl(0xCFC);
-                status = PCIBIOS_SUCCESSFUL;
-	} else if (index == SAL_PCI_CONFIG_WRITE) {
-	      	/*
-		 * in1 contains the PCI configuration address, in2 the
-		 * size of the write, and in3 the actual value to be
-		 * written out.
-		 */
-                outl(BUILD_CMD(in1), 0xCF8);
-                if (in2 == 1)                           /* Writing byte  */
-                        outb(in3, 0xCFC + ((REG_OFFSET(in1) & 3)));
-                else if (in2 == 2)                      /* Writing word  */
-                        outw(in3, 0xCFC + ((REG_OFFSET(in1) & 2)));
-                else                                    /* Writing dword */
-                        outl(in3, 0xCFC);
-                status = PCIBIOS_SUCCESSFUL;
-#endif /* CONFIG_PCI */
-	} else if (index == SAL_UPDATE_PAL) {
-		;
-	} else {
-		status = -1;
-	}
-	return ((struct sal_ret_values) {status, r9, r10, r11});
-}
-
-struct ia64_boot_param *
-sys_fw_init (const char *args, int arglen)
-{
-	efi_system_table_t *efi_systab;
-	efi_runtime_services_t *efi_runtime;
-	efi_config_table_t *efi_tables;
-	struct ia64_sal_systab *sal_systab;
-	efi_memory_desc_t *efi_memmap, *md;
-	unsigned long *pal_desc, *sal_desc;
-	struct ia64_sal_desc_entry_point *sal_ed;
-	struct ia64_boot_param *bp;
-	unsigned char checksum = 0;
-	char *cp, *cmd_line;
-	int i = 0;
-#	define MAKE_MD(typ, attr, start, end)		\
-	do {						\
-		md = efi_memmap + i++;			\
-		md->type = typ;				\
-		md->pad = 0;				\
-		md->phys_addr = start;			\
-		md->virt_addr = 0;			\
-		md->num_pages = (end - start) >> 12;	\
-		md->attribute = attr;			\
-	} while (0)
-
-	memset(fw_mem, 0, sizeof(fw_mem));
-
-	pal_desc = (unsigned long *) &pal_emulator_static;
-	sal_desc = (unsigned long *) &sal_emulator;
-
-	cp = fw_mem;
-	efi_systab  = (void *) cp; cp += sizeof(*efi_systab);
-	efi_runtime = (void *) cp; cp += sizeof(*efi_runtime);
-	efi_tables  = (void *) cp; cp += sizeof(*efi_tables);
-	sal_systab  = (void *) cp; cp += sizeof(*sal_systab);
-	sal_ed      = (void *) cp; cp += sizeof(*sal_ed);
-	efi_memmap  = (void *) cp; cp += NUM_MEM_DESCS*sizeof(*efi_memmap);
-	bp	    = (void *) cp; cp += sizeof(*bp);
-	cmd_line    = (void *) cp;
-
-	if (args) {
-		if (arglen >= 1024)
-			arglen = 1023;
-		memcpy(cmd_line, args, arglen);
-	} else {
-		arglen = 0;
-	}
-	cmd_line[arglen] = '\0';
-
-	memset(efi_systab, 0, sizeof(*efi_systab));
-	efi_systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
-	efi_systab->hdr.revision  = ((1 << 16) | 00);
-	efi_systab->hdr.headersize = sizeof(efi_systab->hdr);
-	efi_systab->fw_vendor = __pa("H\0e\0w\0l\0e\0t\0t\0-\0P\0a\0c\0k\0a\0r\0d\0\0");
-	efi_systab->fw_revision = 1;
-	efi_systab->runtime = (void *) __pa(efi_runtime);
-	efi_systab->nr_tables = 1;
-	efi_systab->tables = __pa(efi_tables);
-
-	efi_runtime->hdr.signature = EFI_RUNTIME_SERVICES_SIGNATURE;
-	efi_runtime->hdr.revision = EFI_RUNTIME_SERVICES_REVISION;
-	efi_runtime->hdr.headersize = sizeof(efi_runtime->hdr);
-	efi_runtime->get_time = (void *)__pa(&fw_efi_get_time);
-	efi_runtime->set_time = (void *)__pa(&efi_unimplemented);
-	efi_runtime->get_wakeup_time = (void *)__pa(&efi_unimplemented);
-	efi_runtime->set_wakeup_time = (void *)__pa(&efi_unimplemented);
-	efi_runtime->set_virtual_address_map = (void *)__pa(&efi_unimplemented);
-	efi_runtime->get_variable = (void *)__pa(&efi_unimplemented);
-	efi_runtime->get_next_variable = (void *)__pa(&efi_unimplemented);
-	efi_runtime->set_variable = (void *)__pa(&efi_unimplemented);
-	efi_runtime->get_next_high_mono_count = (void *)__pa(&efi_unimplemented);
-	efi_runtime->reset_system = (void *)__pa(&efi_reset_system);
-
-	efi_tables->guid = SAL_SYSTEM_TABLE_GUID;
-	efi_tables->table = __pa(sal_systab);
-
-	/* fill in the SAL system table: */
-	memcpy(sal_systab->signature, "SST_", 4);
-	sal_systab->size = sizeof(*sal_systab);
-	sal_systab->sal_rev_minor = 1;
-	sal_systab->sal_rev_major = 0;
-	sal_systab->entry_count = 1;
-
-#ifdef CONFIG_IA64_GENERIC
-        strcpy(sal_systab->oem_id, "Generic");
-        strcpy(sal_systab->product_id, "IA-64 system");
-#endif
-
-#ifdef CONFIG_IA64_HP_SIM
-	strcpy(sal_systab->oem_id, "Hewlett-Packard");
-	strcpy(sal_systab->product_id, "HP-simulator");
-#endif
-
-	/* fill in an entry point: */
-	sal_ed->type = SAL_DESC_ENTRY_POINT;
-	sal_ed->pal_proc = __pa(pal_desc[0]);
-	sal_ed->sal_proc = __pa(sal_desc[0]);
-	sal_ed->gp = __pa(sal_desc[1]);
-
-	for (cp = (char *) sal_systab; cp < (char *) efi_memmap; ++cp)
-		checksum += *cp;
-
-	sal_systab->checksum = -checksum;
-
-#if SIMPLE_MEMMAP
-	/* simulate free memory at physical address zero */
-	MAKE_MD(EFI_BOOT_SERVICES_DATA,		EFI_MEMORY_WB,    0*MB,    1*MB);
-	MAKE_MD(EFI_PAL_CODE,			EFI_MEMORY_WB,    1*MB,    2*MB);
-	MAKE_MD(EFI_CONVENTIONAL_MEMORY,	EFI_MEMORY_WB,    2*MB,  130*MB);
-	MAKE_MD(EFI_CONVENTIONAL_MEMORY,	EFI_MEMORY_WB, 4096*MB, 4128*MB);
-#else
-	MAKE_MD( 4,		   0x9, 0x0000000000000000, 0x0000000000001000);
-	MAKE_MD( 7,		   0x9, 0x0000000000001000, 0x000000000008a000);
-	MAKE_MD( 4,		   0x9, 0x000000000008a000, 0x00000000000a0000);
-	MAKE_MD( 5, 0x8000000000000009, 0x00000000000c0000, 0x0000000000100000);
-	MAKE_MD( 7,		   0x9, 0x0000000000100000, 0x0000000004400000);
-	MAKE_MD( 2,		   0x9, 0x0000000004400000, 0x0000000004be5000);
-	MAKE_MD( 7,		   0x9, 0x0000000004be5000, 0x000000007f77e000);
-	MAKE_MD( 6, 0x8000000000000009, 0x000000007f77e000, 0x000000007fb94000);
-	MAKE_MD( 6, 0x8000000000000009, 0x000000007fb94000, 0x000000007fb95000);
-	MAKE_MD( 6, 0x8000000000000009, 0x000000007fb95000, 0x000000007fc00000);
-	MAKE_MD(13, 0x8000000000000009, 0x000000007fc00000, 0x000000007fc3a000);
-	MAKE_MD( 7,		   0x9, 0x000000007fc3a000, 0x000000007fea0000);
-	MAKE_MD( 5, 0x8000000000000009, 0x000000007fea0000, 0x000000007fea8000);
-	MAKE_MD( 7,		   0x9, 0x000000007fea8000, 0x000000007feab000);
-	MAKE_MD( 5, 0x8000000000000009, 0x000000007feab000, 0x000000007ffff000);
-	MAKE_MD( 7,		   0x9, 0x00000000ff400000, 0x0000000104000000);
-#endif
-
-	bp->efi_systab = __pa(&fw_mem);
-	bp->efi_memmap = __pa(efi_memmap);
-	bp->efi_memmap_size = NUM_MEM_DESCS*sizeof(efi_memory_desc_t);
-	bp->efi_memdesc_size = sizeof(efi_memory_desc_t);
-	bp->efi_memdesc_version = 1;
-	bp->command_line = __pa(cmd_line);
-	bp->console_info.num_cols = 80;
-	bp->console_info.num_rows = 25;
-	bp->console_info.orig_x = 0;
-	bp->console_info.orig_y = 24;
-	bp->fpswa = 0;
-
-	return bp;
-}
diff --git a/arch/ia64/hp/sim/boot/ssc.h b/arch/ia64/hp/sim/boot/ssc.h
deleted file mode 100644
index 88752c7509e0..000000000000
--- a/arch/ia64/hp/sim/boot/ssc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 1998-2003 Hewlett-Packard Co
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- *	Stephane Eranian <eranian@hpl.hp.com>
- */
-#ifndef ssc_h
-#define ssc_h
-
-/* Simulator system calls: */
-
-#define SSC_CONSOLE_INIT		20
-#define SSC_GETCHAR			21
-#define SSC_PUTCHAR			31
-#define SSC_OPEN			50
-#define SSC_CLOSE			51
-#define SSC_READ			52
-#define SSC_WRITE			53
-#define SSC_GET_COMPLETION		54
-#define SSC_WAIT_COMPLETION		55
-#define SSC_CONNECT_INTERRUPT		58
-#define SSC_GENERATE_INTERRUPT		59
-#define SSC_SET_PERIODIC_INTERRUPT	60
-#define SSC_GET_RTC			65
-#define SSC_EXIT			66
-#define SSC_LOAD_SYMBOLS		69
-#define SSC_GET_TOD			74
-
-#define SSC_GET_ARGS			75
-
-/*
- * Simulator system call.
- */
-extern long ssc (long arg0, long arg1, long arg2, long arg3, int nr);
-
-#endif /* ssc_h */
diff --git a/arch/ia64/hp/sim/hpsim.S b/arch/ia64/hp/sim/hpsim.S
deleted file mode 100644
index 44b4d53e1689..000000000000
--- a/arch/ia64/hp/sim/hpsim.S
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <asm/asmmacro.h>
-
-/*
- * Simulator system call.
- */
-GLOBAL_ENTRY(ia64_ssc)
-	mov r15=r36
-	break 0x80001
-	br.ret.sptk.many rp
-END(ia64_ssc)
diff --git a/arch/ia64/hp/sim/hpsim_console.c b/arch/ia64/hp/sim/hpsim_console.c
deleted file mode 100644
index bffd9f67a8a1..000000000000
--- a/arch/ia64/hp/sim/hpsim_console.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Platform dependent support for HP simulator.
- *
- * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1999 Vijay Chander <vijay@engr.sgi.com>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/tty.h>
-#include <linux/kdev_t.h>
-#include <linux/console.h>
-
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/pal.h>
-#include <asm/machvec.h>
-#include <asm/pgtable.h>
-#include <asm/sal.h>
-#include <asm/hpsim.h>
-
-#include "hpsim_ssc.h"
-
-static int simcons_init (struct console *, char *);
-static void simcons_write (struct console *, const char *, unsigned);
-static struct tty_driver *simcons_console_device (struct console *, int *);
-
-static struct console hpsim_cons = {
-	.name =		"simcons",
-	.write =	simcons_write,
-	.device =	simcons_console_device,
-	.setup =	simcons_init,
-	.flags =	CON_PRINTBUFFER,
-	.index =	-1,
-};
-
-static int
-simcons_init (struct console *cons, char *options)
-{
-	return 0;
-}
-
-static void
-simcons_write (struct console *cons, const char *buf, unsigned count)
-{
-	unsigned long ch;
-
-	while (count-- > 0) {
-		ch = *buf++;
-		ia64_ssc(ch, 0, 0, 0, SSC_PUTCHAR);
-		if (ch == '\n')
-		  ia64_ssc('\r', 0, 0, 0, SSC_PUTCHAR);
-	}
-}
-
-static struct tty_driver *simcons_console_device (struct console *c, int *index)
-{
-	*index = c->index;
-	return hp_simserial_driver;
-}
-
-int simcons_register(void)
-{
-	if (!ia64_platform_is("hpsim"))
-		return 1;
-
-	if (hpsim_cons.flags & CON_ENABLED)
-		return 1;
-
-	register_console(&hpsim_cons);
-	return 0;
-}
diff --git a/arch/ia64/hp/sim/hpsim_irq.c b/arch/ia64/hp/sim/hpsim_irq.c
deleted file mode 100644
index 2f1cc59650ab..000000000000
--- a/arch/ia64/hp/sim/hpsim_irq.c
+++ /dev/null
@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Platform dependent support for HP simulator.
- *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/irq.h>
-
-#include "hpsim_ssc.h"
-
-static unsigned int
-hpsim_irq_startup(struct irq_data *data)
-{
-	return 0;
-}
-
-static void
-hpsim_irq_noop(struct irq_data *data)
-{
-}
-
-static int
-hpsim_set_affinity_noop(struct irq_data *d, const struct cpumask *b, bool f)
-{
-	return 0;
-}
-
-static struct irq_chip irq_type_hp_sim = {
-	.name =			"hpsim",
-	.irq_startup =		hpsim_irq_startup,
-	.irq_shutdown =		hpsim_irq_noop,
-	.irq_enable =		hpsim_irq_noop,
-	.irq_disable =		hpsim_irq_noop,
-	.irq_ack =		hpsim_irq_noop,
-	.irq_set_affinity =	hpsim_set_affinity_noop,
-};
-
-static void hpsim_irq_set_chip(int irq)
-{
-	struct irq_chip *chip = irq_get_chip(irq);
-
-	if (chip == &no_irq_chip)
-		irq_set_chip(irq, &irq_type_hp_sim);
-}
-
-static void hpsim_connect_irq(int intr, int irq)
-{
-	ia64_ssc(intr, irq, 0, 0, SSC_CONNECT_INTERRUPT);
-}
-
-int hpsim_get_irq(int intr)
-{
-	int irq = assign_irq_vector(AUTO_ASSIGN);
-
-	if (irq >= 0) {
-		hpsim_irq_set_chip(irq);
-		irq_set_handler(irq, handle_simple_irq);
-		hpsim_connect_irq(intr, irq);
-	}
-
-	return irq;
-}
-
-void __init
-hpsim_irq_init (void)
-{
-	int i;
-
-	for_each_active_irq(i)
-		hpsim_irq_set_chip(i);
-}
diff --git a/arch/ia64/hp/sim/hpsim_machvec.c b/arch/ia64/hp/sim/hpsim_machvec.c
deleted file mode 100644
index c21419359185..000000000000
--- a/arch/ia64/hp/sim/hpsim_machvec.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define MACHVEC_PLATFORM_NAME		hpsim
-#define MACHVEC_PLATFORM_HEADER		<asm/machvec_hpsim.h>
-#include <asm/machvec_init.h>
diff --git a/arch/ia64/hp/sim/hpsim_setup.c b/arch/ia64/hp/sim/hpsim_setup.c
deleted file mode 100644
index 41d21d51dc4d..000000000000
--- a/arch/ia64/hp/sim/hpsim_setup.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Platform dependent support for HP simulator.
- *
- * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1999 Vijay Chander <vijay@engr.sgi.com>
- */
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/kdev_t.h>
-#include <linux/kernel.h>
-#include <linux/major.h>
-#include <linux/param.h>
-#include <linux/root_dev.h>
-#include <linux/string.h>
-#include <linux/types.h>
-
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/pal.h>
-#include <asm/machvec.h>
-#include <asm/pgtable.h>
-#include <asm/sal.h>
-#include <asm/hpsim.h>
-
-#include "hpsim_ssc.h"
-
-void
-ia64_ctl_trace (long on)
-{
-	ia64_ssc(on, 0, 0, 0, SSC_CTL_TRACE);
-}
-
-void __init
-hpsim_setup (char **cmdline_p)
-{
-	ROOT_DEV = Root_SDA1;		/* default to first SCSI drive */
-
-	simcons_register();
-}
diff --git a/arch/ia64/hp/sim/hpsim_ssc.h b/arch/ia64/hp/sim/hpsim_ssc.h
deleted file mode 100644
index 6fd97a487811..000000000000
--- a/arch/ia64/hp/sim/hpsim_ssc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Platform dependent support for HP simulator.
- *
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1999 Vijay Chander <vijay@engr.sgi.com>
- */
-#ifndef _IA64_PLATFORM_HPSIM_SSC_H
-#define _IA64_PLATFORM_HPSIM_SSC_H
-
-/* Simulator system calls: */
-
-#define SSC_CONSOLE_INIT		20
-#define SSC_GETCHAR			21
-#define SSC_PUTCHAR			31
-#define SSC_CONNECT_INTERRUPT		58
-#define SSC_GENERATE_INTERRUPT		59
-#define SSC_SET_PERIODIC_INTERRUPT	60
-#define SSC_GET_RTC			65
-#define SSC_EXIT			66
-#define SSC_LOAD_SYMBOLS		69
-#define SSC_GET_TOD			74
-#define SSC_CTL_TRACE			76
-
-#define SSC_NETDEV_PROBE		100
-#define SSC_NETDEV_SEND			101
-#define SSC_NETDEV_RECV			102
-#define SSC_NETDEV_ATTACH		103
-#define SSC_NETDEV_DETACH		104
-
-/*
- * Simulator system call.
- */
-extern long ia64_ssc (long arg0, long arg1, long arg2, long arg3, int nr);
-
-#endif /* _IA64_PLATFORM_HPSIM_SSC_H */
diff --git a/arch/ia64/hp/sim/simeth.c b/arch/ia64/hp/sim/simeth.c
deleted file mode 100644
index f39ef2b4ed72..000000000000
--- a/arch/ia64/hp/sim/simeth.c
+++ /dev/null
@@ -1,510 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Simulated Ethernet Driver
- *
- * Copyright (C) 1999-2001, 2003 Hewlett-Packard Co
- *	Stephane Eranian <eranian@hpl.hp.com>
- */
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/in.h>
-#include <linux/string.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/inetdevice.h>
-#include <linux/if_ether.h>
-#include <linux/if_arp.h>
-#include <linux/skbuff.h>
-#include <linux/notifier.h>
-#include <linux/bitops.h>
-#include <asm/irq.h>
-#include <asm/hpsim.h>
-
-#include "hpsim_ssc.h"
-
-#define SIMETH_RECV_MAX	10
-
-/*
- * Maximum possible received frame for Ethernet.
- * We preallocate an sk_buff of that size to avoid costly
- * memcpy for temporary buffer into sk_buff. We do basically
- * what's done in other drivers, like eepro with a ring.
- * The difference is, of course, that we don't have real DMA !!!
- */
-#define SIMETH_FRAME_SIZE	ETH_FRAME_LEN
-
-
-#define NETWORK_INTR			8
-
-struct simeth_local {
-	struct net_device_stats stats;
-	int 			simfd;	 /* descriptor in the simulator */
-};
-
-static int simeth_probe1(void);
-static int simeth_open(struct net_device *dev);
-static int simeth_close(struct net_device *dev);
-static int simeth_tx(struct sk_buff *skb, struct net_device *dev);
-static int simeth_rx(struct net_device *dev);
-static struct net_device_stats *simeth_get_stats(struct net_device *dev);
-static irqreturn_t simeth_interrupt(int irq, void *dev_id);
-static void set_multicast_list(struct net_device *dev);
-static int simeth_device_event(struct notifier_block *this,unsigned long event, void *ptr);
-
-static char *simeth_version="0.3";
-
-/*
- * This variable is used to establish a mapping between the Linux/ia64 kernel
- * and the host linux kernel.
- *
- * As of today, we support only one card, even though most of the code
- * is ready for many more. The mapping is then:
- *	linux/ia64 -> linux/x86
- * 	   eth0    -> eth1
- *
- * In the future, we some string operations, we could easily support up
- * to 10 cards (0-9).
- *
- * The default mapping can be changed on the kernel command line by
- * specifying simeth=ethX (or whatever string you want).
- */
-static char *simeth_device="eth0";	 /* default host interface to use */
-
-
-
-static volatile unsigned int card_count; /* how many cards "found" so far */
-static int simeth_debug;		/* set to 1 to get debug information */
-
-/*
- * Used to catch IFF_UP & IFF_DOWN events
- */
-static struct notifier_block simeth_dev_notifier = {
-	simeth_device_event,
-	NULL
-};
-
-
-/*
- * Function used when using a kernel command line option.
- *
- * Format: simeth=interface_name (like eth0)
- */
-static int __init
-simeth_setup(char *str)
-{
-	simeth_device = str;
-	return 1;
-}
-
-__setup("simeth=", simeth_setup);
-
-/*
- * Function used to probe for simeth devices when not installed
- * as a loadable module
- */
-
-int __init
-simeth_probe (void)
-{
-	int r;
-
-	printk(KERN_INFO "simeth: v%s\n", simeth_version);
-
-	r = simeth_probe1();
-
-	if (r == 0) register_netdevice_notifier(&simeth_dev_notifier);
-
-	return r;
-}
-
-static inline int
-netdev_probe(char *name, unsigned char *ether)
-{
-	return ia64_ssc(__pa(name), __pa(ether), 0,0, SSC_NETDEV_PROBE);
-}
-
-
-static inline int
-netdev_attach(int fd, int irq, unsigned int ipaddr)
-{
-	/* this puts the host interface in the right mode (start interrupting) */
-	return ia64_ssc(fd, ipaddr, 0,0, SSC_NETDEV_ATTACH);
-}
-
-
-static inline int
-netdev_detach(int fd)
-{
-	/*
-	 * inactivate the host interface (don't interrupt anymore) */
-	return ia64_ssc(fd, 0,0,0, SSC_NETDEV_DETACH);
-}
-
-static inline int
-netdev_send(int fd, unsigned char *buf, unsigned int len)
-{
-	return ia64_ssc(fd, __pa(buf), len, 0, SSC_NETDEV_SEND);
-}
-
-static inline int
-netdev_read(int fd, unsigned char *buf, unsigned int len)
-{
-	return ia64_ssc(fd, __pa(buf), len, 0, SSC_NETDEV_RECV);
-}
-
-static const struct net_device_ops simeth_netdev_ops = {
-	.ndo_open		= simeth_open,
-	.ndo_stop		= simeth_close,
-	.ndo_start_xmit		= simeth_tx,
-	.ndo_get_stats		= simeth_get_stats,
-	.ndo_set_rx_mode	= set_multicast_list, /* not yet used */
-
-};
-
-/*
- * Function shared with module code, so cannot be in init section
- *
- * So far this function "detects" only one card (test_&_set) but could
- * be extended easily.
- *
- * Return:
- * 	- -ENODEV is no device found
- *	- -ENOMEM is no more memory
- *	- 0 otherwise
- */
-static int
-simeth_probe1(void)
-{
-	unsigned char mac_addr[ETH_ALEN];
-	struct simeth_local *local;
-	struct net_device *dev;
-	int fd, err, rc;
-
-	/*
-	 * XXX Fix me
-	 * let's support just one card for now
-	 */
-	if (test_and_set_bit(0, &card_count))
-		return -ENODEV;
-
-	/*
-	 * check with the simulator for the device
-	 */
-	fd = netdev_probe(simeth_device, mac_addr);
-	if (fd == -1)
-		return -ENODEV;
-
-	dev = alloc_etherdev(sizeof(struct simeth_local));
-	if (!dev)
-		return -ENOMEM;
-
-	memcpy(dev->dev_addr, mac_addr, sizeof(mac_addr));
-
-	local = netdev_priv(dev);
-	local->simfd = fd; /* keep track of underlying file descriptor */
-
-	dev->netdev_ops = &simeth_netdev_ops;
-
-	err = register_netdev(dev);
-	if (err) {
-		free_netdev(dev);
-		return err;
-	}
-
-	/*
-	 * attach the interrupt in the simulator, this does enable interrupts
-	 * until a netdev_attach() is called
-	 */
-	if ((rc = hpsim_get_irq(NETWORK_INTR)) < 0)
-		panic("%s: out of interrupt vectors!\n", __func__);
-	dev->irq = rc;
-
-	printk(KERN_INFO "%s: hosteth=%s simfd=%d, HwAddr=%pm, IRQ %d\n",
-	       dev->name, simeth_device, local->simfd, dev->dev_addr, dev->irq);
-
-	return 0;
-}
-
-/*
- * actually binds the device to an interrupt vector
- */
-static int
-simeth_open(struct net_device *dev)
-{
-	if (request_irq(dev->irq, simeth_interrupt, 0, "simeth", dev)) {
-		printk(KERN_WARNING "simeth: unable to get IRQ %d.\n", dev->irq);
-		return -EAGAIN;
-	}
-
-	netif_start_queue(dev);
-
-	return 0;
-}
-
-/* copied from lapbether.c */
-static __inline__ int dev_is_ethdev(struct net_device *dev)
-{
-       return ( dev->type == ARPHRD_ETHER && strncmp(dev->name, "dummy", 5));
-}
-
-
-/*
- * Handler for IFF_UP or IFF_DOWN
- *
- * The reason for that is that we don't want to be interrupted when the
- * interface is down. There is no way to unconnect in the simualtor. Instead
- * we use this function to shutdown packet processing in the frame filter
- * in the simulator. Thus no interrupts are generated
- *
- *
- * That's also the place where we pass the IP address of this device to the
- * simulator so that that we can start filtering packets for it
- *
- * There may be a better way of doing this, but I don't know which yet.
- */
-static int
-simeth_device_event(struct notifier_block *this,unsigned long event, void *ptr)
-{
-	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
-	struct simeth_local *local;
-	struct in_device *in_dev;
-	struct in_ifaddr **ifap = NULL;
-	struct in_ifaddr *ifa = NULL;
-	int r;
-
-
-	if ( ! dev ) {
-		printk(KERN_WARNING "simeth_device_event dev=0\n");
-		return NOTIFY_DONE;
-	}
-
-	if (dev_net(dev) != &init_net)
-		return NOTIFY_DONE;
-
-	if ( event != NETDEV_UP && event != NETDEV_DOWN ) return NOTIFY_DONE;
-
-	/*
-	 * Check whether or not it's for an ethernet device
-	 *
-	 * XXX Fixme: This works only as long as we support one
-	 * type of ethernet device.
-	 */
-	if ( !dev_is_ethdev(dev) ) return NOTIFY_DONE;
-
-	if ((in_dev=dev->ip_ptr) != NULL) {
-		for (ifap=&in_dev->ifa_list; (ifa=*ifap) != NULL; ifap=&ifa->ifa_next)
-			if (strcmp(dev->name, ifa->ifa_label) == 0) break;
-	}
-	if ( ifa == NULL ) {
-		printk(KERN_ERR "simeth_open: can't find device %s's ifa\n", dev->name);
-		return NOTIFY_DONE;
-	}
-
-	printk(KERN_INFO "simeth_device_event: %s ipaddr=0x%x\n",
-	       dev->name, ntohl(ifa->ifa_local));
-
-	/*
-	 * XXX Fix me
-	 * if the device was up, and we're simply reconfiguring it, not sure
-	 * we get DOWN then UP.
-	 */
-
-	local = netdev_priv(dev);
-	/* now do it for real */
-	r = event == NETDEV_UP ?
-		netdev_attach(local->simfd, dev->irq, ntohl(ifa->ifa_local)):
-		netdev_detach(local->simfd);
-
-	printk(KERN_INFO "simeth: netdev_attach/detach: event=%s ->%d\n",
-	       event == NETDEV_UP ? "attach":"detach", r);
-
-	return NOTIFY_DONE;
-}
-
-static int
-simeth_close(struct net_device *dev)
-{
-	netif_stop_queue(dev);
-
-	free_irq(dev->irq, dev);
-
-	return 0;
-}
-
-/*
- * Only used for debug
- */
-static void
-frame_print(unsigned char *from, unsigned char *frame, int len)
-{
-	int i;
-
-	printk("%s: (%d) %02x", from, len, frame[0] & 0xff);
-	for(i=1; i < 6; i++ ) {
-		printk(":%02x", frame[i] &0xff);
-	}
-	printk(" %2x", frame[6] &0xff);
-	for(i=7; i < 12; i++ ) {
-		printk(":%02x", frame[i] &0xff);
-	}
-	printk(" [%02x%02x]\n", frame[12], frame[13]);
-
-	for(i=14; i < len; i++ ) {
-		printk("%02x ", frame[i] &0xff);
-		if ( (i%10)==0) printk("\n");
-	}
-	printk("\n");
-}
-
-
-/*
- * Function used to transmit of frame, very last one on the path before
- * going to the simulator.
- */
-static int
-simeth_tx(struct sk_buff *skb, struct net_device *dev)
-{
-	struct simeth_local *local = netdev_priv(dev);
-
-#if 0
-	/* ensure we have at least ETH_ZLEN bytes (min frame size) */
-	unsigned int length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
-	/* Where do the extra padding bytes comes from inthe skbuff ? */
-#else
-	/* the real driver in the host system is going to take care of that
-	 * or maybe it's the NIC itself.
-	 */
-	unsigned int length = skb->len;
-#endif
-
-	local->stats.tx_bytes += skb->len;
-	local->stats.tx_packets++;
-
-
-	if (simeth_debug > 5) frame_print("simeth_tx", skb->data, length);
-
-	netdev_send(local->simfd, skb->data, length);
-
-	/*
-	 * we are synchronous on write, so we don't simulate a
-	 * trasnmit complete interrupt, thus we don't need to arm a tx
-	 */
-
-	dev_kfree_skb(skb);
-	return NETDEV_TX_OK;
-}
-
-static inline struct sk_buff *
-make_new_skb(struct net_device *dev)
-{
-	struct sk_buff *nskb;
-
-	/*
-	 * The +2 is used to make sure that the IP header is nicely
-	 * aligned (on 4byte boundary I assume 14+2=16)
-	 */
-	nskb = dev_alloc_skb(SIMETH_FRAME_SIZE + 2);
-	if ( nskb == NULL ) {
-		printk(KERN_NOTICE "%s: memory squeeze. dropping packet.\n", dev->name);
-		return NULL;
-	}
-
-	skb_reserve(nskb, 2);	/* Align IP on 16 byte boundaries */
-
-	skb_put(nskb,SIMETH_FRAME_SIZE);
-
-	return nskb;
-}
-
-/*
- * called from interrupt handler to process a received frame
- */
-static int
-simeth_rx(struct net_device *dev)
-{
-	struct simeth_local	*local;
-	struct sk_buff		*skb;
-	int			len;
-	int			rcv_count = SIMETH_RECV_MAX;
-
-	local = netdev_priv(dev);
-	/*
-	 * the loop concept has been borrowed from other drivers
-	 * looks to me like it's a throttling thing to avoid pushing to many
-	 * packets at one time into the stack. Making sure we can process them
-	 * upstream and make forward progress overall
-	 */
-	do {
-		if ( (skb=make_new_skb(dev)) == NULL ) {
-			printk(KERN_NOTICE "%s: memory squeeze. dropping packet.\n", dev->name);
-			local->stats.rx_dropped++;
-			return 0;
-		}
-		/*
-		 * Read only one frame at a time
-		 */
-		len = netdev_read(local->simfd, skb->data, SIMETH_FRAME_SIZE);
-		if ( len == 0 ) {
-			if ( simeth_debug > 0 ) printk(KERN_WARNING "%s: count=%d netdev_read=0\n",
-						       dev->name, SIMETH_RECV_MAX-rcv_count);
-			break;
-		}
-#if 0
-		/*
-		 * XXX Fix me
-		 * Should really do a csum+copy here
-		 */
-		skb_copy_to_linear_data(skb, frame, len);
-#endif
-		skb->protocol = eth_type_trans(skb, dev);
-
-		if ( simeth_debug > 6 ) frame_print("simeth_rx", skb->data, len);
-
-		/*
-		 * push the packet up & trigger software interrupt
-		 */
-		netif_rx(skb);
-
-		local->stats.rx_packets++;
-		local->stats.rx_bytes += len;
-
-	} while ( --rcv_count );
-
-	return len; /* 0 = nothing left to read, otherwise, we can try again */
-}
-
-/*
- * Interrupt handler (Yes, we can do it too !!!)
- */
-static irqreturn_t
-simeth_interrupt(int irq, void *dev_id)
-{
-	struct net_device *dev = dev_id;
-
-	/*
-	 * very simple loop because we get interrupts only when receiving
-	 */
-	while (simeth_rx(dev));
-	return IRQ_HANDLED;
-}
-
-static struct net_device_stats *
-simeth_get_stats(struct net_device *dev)
-{
-	struct simeth_local *local = netdev_priv(dev);
-
-	return &local->stats;
-}
-
-/* fake multicast ability */
-static void
-set_multicast_list(struct net_device *dev)
-{
-	printk(KERN_WARNING "%s: set_multicast_list called\n", dev->name);
-}
-
-__initcall(simeth_probe);
diff --git a/arch/ia64/hp/sim/simscsi.c b/arch/ia64/hp/sim/simscsi.c
deleted file mode 100644
index 0a8a74271173..000000000000
--- a/arch/ia64/hp/sim/simscsi.c
+++ /dev/null
@@ -1,373 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Simulated SCSI driver.
- *
- * Copyright (C) 1999, 2001-2003 Hewlett-Packard Co
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- *	Stephane Eranian <eranian@hpl.hp.com>
- *
- * 02/01/15 David Mosberger	Updated for v2.5.1
- * 99/12/18 David Mosberger	Added support for READ10/WRITE10 needed by linux v2.3.33
- */
-#include <linux/blkdev.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/timer.h>
-#include <asm/irq.h>
-#include "hpsim_ssc.h"
-
-#include <scsi/scsi.h>
-#include <scsi/scsi_cmnd.h>
-#include <scsi/scsi_device.h>
-#include <scsi/scsi_host.h>
-
-#define DEBUG_SIMSCSI	0
-
-#define SIMSCSI_REQ_QUEUE_LEN	64
-#define DEFAULT_SIMSCSI_ROOT	"/var/ski-disks/sd"
-
-/* Simulator system calls: */
-
-#define SSC_OPEN			50
-#define SSC_CLOSE			51
-#define SSC_READ			52
-#define SSC_WRITE			53
-#define SSC_GET_COMPLETION		54
-#define SSC_WAIT_COMPLETION		55
-
-#define SSC_WRITE_ACCESS		2
-#define SSC_READ_ACCESS			1
-
-#if DEBUG_SIMSCSI
-  int simscsi_debug;
-# define DBG	simscsi_debug
-#else
-# define DBG	0
-#endif
-
-static struct Scsi_Host *host;
-
-static void simscsi_interrupt (unsigned long val);
-static DECLARE_TASKLET(simscsi_tasklet, simscsi_interrupt, 0);
-
-struct disk_req {
-	unsigned long addr;
-	unsigned len;
-};
-
-struct disk_stat {
-	int fd;
-	unsigned count;
-};
-
-static int desc[16] = {
-	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-static struct queue_entry {
-	struct scsi_cmnd *sc;
-} queue[SIMSCSI_REQ_QUEUE_LEN];
-
-static int rd, wr;
-static atomic_t num_reqs = ATOMIC_INIT(0);
-
-/* base name for default disks */
-static char *simscsi_root = DEFAULT_SIMSCSI_ROOT;
-
-#define MAX_ROOT_LEN	128
-
-/*
- * used to setup a new base for disk images
- * to use /foo/bar/disk[a-z] as disk images
- * you have to specify simscsi=/foo/bar/disk on the command line
- */
-static int __init
-simscsi_setup (char *s)
-{
-	/* XXX Fix me we may need to strcpy() ? */
-	if (strlen(s) > MAX_ROOT_LEN) {
-		printk(KERN_ERR "simscsi_setup: prefix too long---using default %s\n",
-		       simscsi_root);
-	} else
-		simscsi_root = s;
-	return 1;
-}
-
-__setup("simscsi=", simscsi_setup);
-
-static void
-simscsi_interrupt (unsigned long val)
-{
-	struct scsi_cmnd *sc;
-
-	while ((sc = queue[rd].sc) != NULL) {
-		atomic_dec(&num_reqs);
-		queue[rd].sc = NULL;
-		if (DBG)
-			printk("simscsi_interrupt: done with %u\n",
-			       sc->request->tag);
-		(*sc->scsi_done)(sc);
-		rd = (rd + 1) % SIMSCSI_REQ_QUEUE_LEN;
-	}
-}
-
-static int
-simscsi_biosparam (struct scsi_device *sdev, struct block_device *n,
-		sector_t capacity, int ip[])
-{
-	ip[0] = 64;		/* heads */
-	ip[1] = 32;		/* sectors */
-	ip[2] = capacity >> 11;	/* cylinders */
-	return 0;
-}
-
-static void
-simscsi_sg_readwrite (struct scsi_cmnd *sc, int mode, unsigned long offset)
-{
-	int i;
-	struct scatterlist *sl;
-	struct disk_stat stat;
-	struct disk_req req;
-
-	stat.fd = desc[sc->device->id];
-
-	scsi_for_each_sg(sc, sl, scsi_sg_count(sc), i) {
-		req.addr = __pa(sg_virt(sl));
-		req.len  = sl->length;
-		if (DBG)
-			printk("simscsi_sg_%s @ %lx (off %lx) use_sg=%d len=%d\n",
-			       mode == SSC_READ ? "read":"write", req.addr, offset,
-			       scsi_sg_count(sc) - i, sl->length);
-		ia64_ssc(stat.fd, 1, __pa(&req), offset, mode);
-		ia64_ssc(__pa(&stat), 0, 0, 0, SSC_WAIT_COMPLETION);
-
-		/* should not happen in our case */
-		if (stat.count != req.len) {
-			sc->result = DID_ERROR << 16;
-			return;
-		}
-		offset +=  sl->length;
-	}
-	sc->result = GOOD;
-}
-
-/*
- * function handling both READ_6/WRITE_6 (non-scatter/gather mode)
- * commands.
- * Added 02/26/99 S.Eranian
- */
-static void
-simscsi_readwrite6 (struct scsi_cmnd *sc, int mode)
-{
-	unsigned long offset;
-
-	offset = (((sc->cmnd[1] & 0x1f) << 16) | (sc->cmnd[2] << 8) | sc->cmnd[3])*512;
-	simscsi_sg_readwrite(sc, mode, offset);
-}
-
-static size_t
-simscsi_get_disk_size (int fd)
-{
-	struct disk_stat stat;
-	size_t bit, sectors = 0;
-	struct disk_req req;
-	char buf[512];
-
-	/*
-	 * This is a bit kludgey: the simulator doesn't provide a
-	 * direct way of determining the disk size, so we do a binary
-	 * search, assuming a maximum disk size of 128GB.
-	 */
-	for (bit = (128UL << 30)/512; bit != 0; bit >>= 1) {
-		req.addr = __pa(&buf);
-		req.len = sizeof(buf);
-		ia64_ssc(fd, 1, __pa(&req), ((sectors | bit) - 1)*512, SSC_READ);
-		stat.fd = fd;
-		ia64_ssc(__pa(&stat), 0, 0, 0, SSC_WAIT_COMPLETION);
-		if (stat.count == sizeof(buf))
-			sectors |= bit;
-	}
-	return sectors - 1;	/* return last valid sector number */
-}
-
-static void
-simscsi_readwrite10 (struct scsi_cmnd *sc, int mode)
-{
-	unsigned long offset;
-
-	offset = (((unsigned long)sc->cmnd[2] << 24) 
-		| ((unsigned long)sc->cmnd[3] << 16)
-		| ((unsigned long)sc->cmnd[4] <<  8) 
-		| ((unsigned long)sc->cmnd[5] <<  0))*512UL;
-	simscsi_sg_readwrite(sc, mode, offset);
-}
-
-static int
-simscsi_queuecommand_lck (struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *))
-{
-	unsigned int target_id = sc->device->id;
-	char fname[MAX_ROOT_LEN+16];
-	size_t disk_size;
-	char *buf;
-	char localbuf[36];
-#if DEBUG_SIMSCSI
-	register long sp asm ("sp");
-
-	if (DBG)
-		printk("simscsi_queuecommand: target=%d,cmnd=%u,sc=%u,sp=%lx,done=%p\n",
-		       target_id, sc->cmnd[0], sc->request->tag, sp, done);
-#endif
-
-	sc->result = DID_BAD_TARGET << 16;
-	sc->scsi_done = done;
-	if (target_id <= 15 && sc->device->lun == 0) {
-		switch (sc->cmnd[0]) {
-		      case INQUIRY:
-			if (scsi_bufflen(sc) < 35) {
-				break;
-			}
-			sprintf (fname, "%s%c", simscsi_root, 'a' + target_id);
-			desc[target_id] = ia64_ssc(__pa(fname), SSC_READ_ACCESS|SSC_WRITE_ACCESS,
-						   0, 0, SSC_OPEN);
-			if (desc[target_id] < 0) {
-				/* disk doesn't exist... */
-				break;
-			}
-			buf = localbuf;
-			buf[0] = 0;	/* magnetic disk */
-			buf[1] = 0;	/* not a removable medium */
-			buf[2] = 2;	/* SCSI-2 compliant device */
-			buf[3] = 2;	/* SCSI-2 response data format */
-			buf[4] = 31;	/* additional length (bytes) */
-			buf[5] = 0;	/* reserved */
-			buf[6] = 0;	/* reserved */
-			buf[7] = 0;	/* various flags */
-			memcpy(buf + 8, "HP      SIMULATED DISK  0.00",  28);
-			scsi_sg_copy_from_buffer(sc, buf, 36);
-			sc->result = GOOD;
-			break;
-
-		      case TEST_UNIT_READY:
-			sc->result = GOOD;
-			break;
-
-		      case READ_6:
-			if (desc[target_id] < 0 )
-				break;
-			simscsi_readwrite6(sc, SSC_READ);
-			break;
-
-		      case READ_10:
-			if (desc[target_id] < 0 )
-				break;
-			simscsi_readwrite10(sc, SSC_READ);
-			break;
-
-		      case WRITE_6:
-			if (desc[target_id] < 0)
-				break;
-			simscsi_readwrite6(sc, SSC_WRITE);
-			break;
-
-		      case WRITE_10:
-			if (desc[target_id] < 0)
-				break;
-			simscsi_readwrite10(sc, SSC_WRITE);
-			break;
-
-		      case READ_CAPACITY:
-			if (desc[target_id] < 0 || scsi_bufflen(sc) < 8) {
-				break;
-			}
-			buf = localbuf;
-			disk_size = simscsi_get_disk_size(desc[target_id]);
-
-			buf[0] = (disk_size >> 24) & 0xff;
-			buf[1] = (disk_size >> 16) & 0xff;
-			buf[2] = (disk_size >>  8) & 0xff;
-			buf[3] = (disk_size >>  0) & 0xff;
-			/* set block size of 512 bytes: */
-			buf[4] = 0;
-			buf[5] = 0;
-			buf[6] = 2;
-			buf[7] = 0;
-			scsi_sg_copy_from_buffer(sc, buf, 8);
-			sc->result = GOOD;
-			break;
-
-		      case MODE_SENSE:
-		      case MODE_SENSE_10:
-			/* sd.c uses this to determine whether disk does write-caching. */
-			scsi_sg_copy_from_buffer(sc, (char *)empty_zero_page,
-						 PAGE_SIZE);
-			sc->result = GOOD;
-			break;
-
-		      case START_STOP:
-			printk(KERN_ERR "START_STOP\n");
-			break;
-
-		      default:
-			panic("simscsi: unknown SCSI command %u\n", sc->cmnd[0]);
-		}
-	}
-	if (sc->result == DID_BAD_TARGET) {
-		sc->result |= DRIVER_SENSE << 24;
-		sc->sense_buffer[0] = 0x70;
-		sc->sense_buffer[2] = 0x00;
-	}
-	if (atomic_read(&num_reqs) >= SIMSCSI_REQ_QUEUE_LEN) {
-		panic("Attempt to queue command while command is pending!!");
-	}
-	atomic_inc(&num_reqs);
-	queue[wr].sc = sc;
-	wr = (wr + 1) % SIMSCSI_REQ_QUEUE_LEN;
-
-	tasklet_schedule(&simscsi_tasklet);
-	return 0;
-}
-
-static DEF_SCSI_QCMD(simscsi_queuecommand)
-
-static int
-simscsi_host_reset (struct scsi_cmnd *sc)
-{
-	printk(KERN_ERR "simscsi_host_reset: not implemented\n");
-	return 0;
-}
-
-static struct scsi_host_template driver_template = {
-	.name			= "simulated SCSI host adapter",
-	.proc_name		= "simscsi",
-	.queuecommand		= simscsi_queuecommand,
-	.eh_host_reset_handler	= simscsi_host_reset,
-	.bios_param		= simscsi_biosparam,
-	.can_queue		= SIMSCSI_REQ_QUEUE_LEN,
-	.this_id		= -1,
-	.sg_tablesize		= SG_ALL,
-	.max_sectors		= 1024,
-	.cmd_per_lun		= SIMSCSI_REQ_QUEUE_LEN,
-	.dma_boundary		= PAGE_SIZE - 1,
-};
-
-static int __init
-simscsi_init(void)
-{
-	int error;
-
-	host = scsi_host_alloc(&driver_template, 0);
-	if (!host)
-		return -ENOMEM;
-
-	error = scsi_add_host(host, NULL);
-	if (error)
-		goto free_host;
-	scsi_scan_host(host);
-	return 0;
-
- free_host:
-	scsi_host_put(host);
-	return error;
-}
-device_initcall(simscsi_init);
diff --git a/arch/ia64/hp/sim/simserial.c b/arch/ia64/hp/sim/simserial.c
deleted file mode 100644
index 1a338e541334..000000000000
--- a/arch/ia64/hp/sim/simserial.c
+++ /dev/null
@@ -1,521 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Simulated Serial Driver (fake serial)
- *
- * This driver is mostly used for bringup purposes and will go away.
- * It has a strong dependency on the system console. All outputs
- * are rerouted to the same facility as the one used by printk which, in our
- * case means sys_sim.c console (goes via the simulator).
- *
- * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co
- *	Stephane Eranian <eranian@hpl.hp.com>
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- */
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
-#include <linux/major.h>
-#include <linux/fcntl.h>
-#include <linux/mm.h>
-#include <linux/seq_file.h>
-#include <linux/slab.h>
-#include <linux/capability.h>
-#include <linux/circ_buf.h>
-#include <linux/console.h>
-#include <linux/irq.h>
-#include <linux/module.h>
-#include <linux/serial.h>
-#include <linux/sysrq.h>
-#include <linux/uaccess.h>
-
-#include <asm/hpsim.h>
-
-#include "hpsim_ssc.h"
-
-#undef SIMSERIAL_DEBUG	/* define this to get some debug information */
-
-#define KEYBOARD_INTR	3	/* must match with simulator! */
-
-#define NR_PORTS	1	/* only one port for now */
-
-struct serial_state {
-	struct tty_port port;
-	struct circ_buf xmit;
-	int irq;
-	int x_char;
-};
-
-static struct serial_state rs_table[NR_PORTS];
-
-struct tty_driver *hp_simserial_driver;
-
-static struct console *console;
-
-static void receive_chars(struct tty_port *port)
-{
-	unsigned char ch;
-	static unsigned char seen_esc = 0;
-
-	while ( (ch = ia64_ssc(0, 0, 0, 0, SSC_GETCHAR)) ) {
-		if (ch == 27 && seen_esc == 0) {
-			seen_esc = 1;
-			continue;
-		} else if (seen_esc == 1 && ch == 'O') {
-			seen_esc = 2;
-			continue;
-		} else if (seen_esc == 2) {
-			if (ch == 'P') /* F1 */
-				show_state();
-#ifdef CONFIG_MAGIC_SYSRQ
-			if (ch == 'S') { /* F4 */
-				do {
-					ch = ia64_ssc(0, 0, 0, 0, SSC_GETCHAR);
-				} while (!ch);
-				handle_sysrq(ch);
-			}
-#endif
-			seen_esc = 0;
-			continue;
-		}
-		seen_esc = 0;
-
-		if (tty_insert_flip_char(port, ch, TTY_NORMAL) == 0)
-			break;
-	}
-	tty_flip_buffer_push(port);
-}
-
-/*
- * This is the serial driver's interrupt routine for a single port
- */
-static irqreturn_t rs_interrupt_single(int irq, void *dev_id)
-{
-	struct serial_state *info = dev_id;
-
-	receive_chars(&info->port);
-
-	return IRQ_HANDLED;
-}
-
-/*
- * -------------------------------------------------------------------
- * Here ends the serial interrupt routines.
- * -------------------------------------------------------------------
- */
-
-static int rs_put_char(struct tty_struct *tty, unsigned char ch)
-{
-	struct serial_state *info = tty->driver_data;
-	unsigned long flags;
-
-	if (!info->xmit.buf)
-		return 0;
-
-	local_irq_save(flags);
-	if (CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE) == 0) {
-		local_irq_restore(flags);
-		return 0;
-	}
-	info->xmit.buf[info->xmit.head] = ch;
-	info->xmit.head = (info->xmit.head + 1) & (SERIAL_XMIT_SIZE-1);
-	local_irq_restore(flags);
-	return 1;
-}
-
-static void transmit_chars(struct tty_struct *tty, struct serial_state *info,
-		int *intr_done)
-{
-	int count;
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	if (info->x_char) {
-		char c = info->x_char;
-
-		console->write(console, &c, 1);
-
-		info->x_char = 0;
-
-		goto out;
-	}
-
-	if (info->xmit.head == info->xmit.tail || tty->stopped) {
-#ifdef SIMSERIAL_DEBUG
-		printk("transmit_chars: head=%d, tail=%d, stopped=%d\n",
-		       info->xmit.head, info->xmit.tail, tty->stopped);
-#endif
-		goto out;
-	}
-	/*
-	 * We removed the loop and try to do it in to chunks. We need
-	 * 2 operations maximum because it's a ring buffer.
-	 *
-	 * First from current to tail if possible.
-	 * Then from the beginning of the buffer until necessary
-	 */
-
-	count = min(CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE),
-		    SERIAL_XMIT_SIZE - info->xmit.tail);
-	console->write(console, info->xmit.buf+info->xmit.tail, count);
-
-	info->xmit.tail = (info->xmit.tail+count) & (SERIAL_XMIT_SIZE-1);
-
-	/*
-	 * We have more at the beginning of the buffer
-	 */
-	count = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
-	if (count) {
-		console->write(console, info->xmit.buf, count);
-		info->xmit.tail += count;
-	}
-out:
-	local_irq_restore(flags);
-}
-
-static void rs_flush_chars(struct tty_struct *tty)
-{
-	struct serial_state *info = tty->driver_data;
-
-	if (info->xmit.head == info->xmit.tail || tty->stopped ||
-			!info->xmit.buf)
-		return;
-
-	transmit_chars(tty, info, NULL);
-}
-
-static int rs_write(struct tty_struct * tty,
-		    const unsigned char *buf, int count)
-{
-	struct serial_state *info = tty->driver_data;
-	int	c, ret = 0;
-	unsigned long flags;
-
-	if (!info->xmit.buf)
-		return 0;
-
-	local_irq_save(flags);
-	while (1) {
-		c = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
-		if (count < c)
-			c = count;
-		if (c <= 0) {
-			break;
-		}
-		memcpy(info->xmit.buf + info->xmit.head, buf, c);
-		info->xmit.head = ((info->xmit.head + c) &
-				   (SERIAL_XMIT_SIZE-1));
-		buf += c;
-		count -= c;
-		ret += c;
-	}
-	local_irq_restore(flags);
-	/*
-	 * Hey, we transmit directly from here in our case
-	 */
-	if (CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE) &&
-			!tty->stopped)
-		transmit_chars(tty, info, NULL);
-
-	return ret;
-}
-
-static int rs_write_room(struct tty_struct *tty)
-{
-	struct serial_state *info = tty->driver_data;
-
-	return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
-}
-
-static int rs_chars_in_buffer(struct tty_struct *tty)
-{
-	struct serial_state *info = tty->driver_data;
-
-	return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
-}
-
-static void rs_flush_buffer(struct tty_struct *tty)
-{
-	struct serial_state *info = tty->driver_data;
-	unsigned long flags;
-
-	local_irq_save(flags);
-	info->xmit.head = info->xmit.tail = 0;
-	local_irq_restore(flags);
-
-	tty_wakeup(tty);
-}
-
-/*
- * This function is used to send a high-priority XON/XOFF character to
- * the device
- */
-static void rs_send_xchar(struct tty_struct *tty, char ch)
-{
-	struct serial_state *info = tty->driver_data;
-
-	info->x_char = ch;
-	if (ch) {
-		/*
-		 * I guess we could call console->write() directly but
-		 * let's do that for now.
-		 */
-		transmit_chars(tty, info, NULL);
-	}
-}
-
-/*
- * ------------------------------------------------------------
- * rs_throttle()
- *
- * This routine is called by the upper-layer tty layer to signal that
- * incoming characters should be throttled.
- * ------------------------------------------------------------
- */
-static void rs_throttle(struct tty_struct * tty)
-{
-	if (I_IXOFF(tty))
-		rs_send_xchar(tty, STOP_CHAR(tty));
-
-	printk(KERN_INFO "simrs_throttle called\n");
-}
-
-static void rs_unthrottle(struct tty_struct * tty)
-{
-	struct serial_state *info = tty->driver_data;
-
-	if (I_IXOFF(tty)) {
-		if (info->x_char)
-			info->x_char = 0;
-		else
-			rs_send_xchar(tty, START_CHAR(tty));
-	}
-	printk(KERN_INFO "simrs_unthrottle called\n");
-}
-
-static int rs_setserial(struct tty_struct *tty, struct serial_struct *ss)
-{
-	return 0;
-}
-
-static int rs_getserial(struct tty_struct *tty, struct serial_struct *ss)
-{
-	return 0;
-}
-
-static int rs_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg)
-{
-	if ((cmd != TIOCSERCONFIG) && (cmd != TIOCMIWAIT)) {
-		if (tty_io_error(tty))
-		    return -EIO;
-	}
-
-	switch (cmd) {
-	case TIOCMIWAIT:
-		return 0;
-	case TIOCSERCONFIG:
-	case TIOCSERGETLSR: /* Get line status register */
-		return -EINVAL;
-	}
-	return -ENOIOCTLCMD;
-}
-
-/*
- * This routine will shutdown a serial port; interrupts are disabled, and
- * DTR is dropped if the hangup on close termio flag is on.
- */
-static void shutdown(struct tty_port *port)
-{
-	struct serial_state *info = container_of(port, struct serial_state,
-			port);
-	unsigned long flags;
-
-	local_irq_save(flags);
-	if (info->irq)
-		free_irq(info->irq, info);
-
-	if (info->xmit.buf) {
-		free_page((unsigned long) info->xmit.buf);
-		info->xmit.buf = NULL;
-	}
-	local_irq_restore(flags);
-}
-
-static void rs_close(struct tty_struct *tty, struct file * filp)
-{
-	struct serial_state *info = tty->driver_data;
-
-	tty_port_close(&info->port, tty, filp);
-}
-
-static void rs_hangup(struct tty_struct *tty)
-{
-	struct serial_state *info = tty->driver_data;
-
-	rs_flush_buffer(tty);
-	tty_port_hangup(&info->port);
-}
-
-static int activate(struct tty_port *port, struct tty_struct *tty)
-{
-	struct serial_state *state = container_of(port, struct serial_state,
-			port);
-	unsigned long flags, page;
-	int retval = 0;
-
-	page = get_zeroed_page(GFP_KERNEL);
-	if (!page)
-		return -ENOMEM;
-
-	local_irq_save(flags);
-
-	if (state->xmit.buf)
-		free_page(page);
-	else
-		state->xmit.buf = (unsigned char *) page;
-
-	if (state->irq) {
-		retval = request_irq(state->irq, rs_interrupt_single, 0,
-				"simserial", state);
-		if (retval)
-			goto errout;
-	}
-
-	state->xmit.head = state->xmit.tail = 0;
-errout:
-	local_irq_restore(flags);
-	return retval;
-}
-
-
-/*
- * This routine is called whenever a serial port is opened.  It
- * enables interrupts for a serial port, linking in its async structure into
- * the IRQ chain.   It also performs the serial-specific
- * initialization for the tty structure.
- */
-static int rs_open(struct tty_struct *tty, struct file * filp)
-{
-	struct serial_state *info = rs_table + tty->index;
-	struct tty_port *port = &info->port;
-
-	tty->driver_data = info;
-	port->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
-
-	/*
-	 * figure out which console to use (should be one already)
-	 */
-	console = console_drivers;
-	while (console) {
-		if ((console->flags & CON_ENABLED) && console->write) break;
-		console = console->next;
-	}
-
-	return tty_port_open(port, tty, filp);
-}
-
-/*
- * /proc fs routines....
- */
-
-static int rs_proc_show(struct seq_file *m, void *v)
-{
-	int i;
-
-	seq_printf(m, "simserinfo:1.0\n");
-	for (i = 0; i < NR_PORTS; i++)
-		seq_printf(m, "%d: uart:16550 port:3F8 irq:%d\n",
-		       i, rs_table[i].irq);
-	return 0;
-}
-
-static const struct tty_operations hp_ops = {
-	.open = rs_open,
-	.close = rs_close,
-	.write = rs_write,
-	.put_char = rs_put_char,
-	.flush_chars = rs_flush_chars,
-	.write_room = rs_write_room,
-	.chars_in_buffer = rs_chars_in_buffer,
-	.flush_buffer = rs_flush_buffer,
-	.ioctl = rs_ioctl,
-	.throttle = rs_throttle,
-	.unthrottle = rs_unthrottle,
-	.send_xchar = rs_send_xchar,
-	.set_serial = rs_setserial,
-	.get_serial = rs_getserial,
-	.hangup = rs_hangup,
-	.proc_show = rs_proc_show,
-};
-
-static const struct tty_port_operations hp_port_ops = {
-	.activate = activate,
-	.shutdown = shutdown,
-};
-
-static int __init simrs_init(void)
-{
-	struct serial_state *state;
-	int retval;
-
-	if (!ia64_platform_is("hpsim"))
-		return -ENODEV;
-
-	hp_simserial_driver = alloc_tty_driver(NR_PORTS);
-	if (!hp_simserial_driver)
-		return -ENOMEM;
-
-	printk(KERN_INFO "SimSerial driver with no serial options enabled\n");
-
-	/* Initialize the tty_driver structure */
-
-	hp_simserial_driver->driver_name = "simserial";
-	hp_simserial_driver->name = "ttyS";
-	hp_simserial_driver->major = TTY_MAJOR;
-	hp_simserial_driver->minor_start = 64;
-	hp_simserial_driver->type = TTY_DRIVER_TYPE_SERIAL;
-	hp_simserial_driver->subtype = SERIAL_TYPE_NORMAL;
-	hp_simserial_driver->init_termios = tty_std_termios;
-	hp_simserial_driver->init_termios.c_cflag =
-		B9600 | CS8 | CREAD | HUPCL | CLOCAL;
-	hp_simserial_driver->flags = TTY_DRIVER_REAL_RAW;
-	tty_set_operations(hp_simserial_driver, &hp_ops);
-
-	state = rs_table;
-	tty_port_init(&state->port);
-	state->port.ops = &hp_port_ops;
-	state->port.close_delay = 0; /* XXX really 0? */
-
-	retval = hpsim_get_irq(KEYBOARD_INTR);
-	if (retval < 0) {
-		printk(KERN_ERR "%s: out of interrupt vectors!\n",
-				__func__);
-		goto err_free_tty;
-	}
-
-	state->irq = retval;
-
-	/* the port is imaginary */
-	printk(KERN_INFO "ttyS0 at 0x03f8 (irq = %d) is a 16550\n", state->irq);
-
-	tty_port_link_device(&state->port, hp_simserial_driver, 0);
-	retval = tty_register_driver(hp_simserial_driver);
-	if (retval) {
-		printk(KERN_ERR "Couldn't register simserial driver\n");
-		goto err_free_tty;
-	}
-
-	return 0;
-err_free_tty:
-	put_tty_driver(hp_simserial_driver);
-	tty_port_destroy(&state->port);
-	return retval;
-}
-
-#ifndef MODULE
-__initcall(simrs_init);
-#endif
diff --git a/arch/ia64/hp/zx1/Makefile b/arch/ia64/hp/zx1/Makefile
deleted file mode 100644
index 46b37d820b59..000000000000
--- a/arch/ia64/hp/zx1/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# ia64/hp/zx1/Makefile
-#
-# Copyright (C) 2002 Hewlett Packard
-# Copyright (C) Alex Williamson (alex_williamson@hp.com)
-#
-
-obj-$(CONFIG_IA64_GENERIC) += hpzx1_machvec.o hpzx1_swiotlb_machvec.o
diff --git a/arch/ia64/hp/zx1/hpzx1_machvec.c b/arch/ia64/hp/zx1/hpzx1_machvec.c
deleted file mode 100644
index 32518b0f923e..000000000000
--- a/arch/ia64/hp/zx1/hpzx1_machvec.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define MACHVEC_PLATFORM_NAME		hpzx1
-#define MACHVEC_PLATFORM_HEADER		<asm/machvec_hpzx1.h>
-#include <asm/machvec_init.h>
diff --git a/arch/ia64/hp/zx1/hpzx1_swiotlb_machvec.c b/arch/ia64/hp/zx1/hpzx1_swiotlb_machvec.c
deleted file mode 100644
index 4392a96b3c58..000000000000
--- a/arch/ia64/hp/zx1/hpzx1_swiotlb_machvec.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define MACHVEC_PLATFORM_NAME		hpzx1_swiotlb
-#define MACHVEC_PLATFORM_HEADER		<asm/machvec_hpzx1_swiotlb.h>
-#include <asm/machvec_init.h>
diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h
index 0ea569040c5b..f886d4dc9d55 100644
--- a/arch/ia64/include/asm/acpi.h
+++ b/arch/ia64/include/asm/acpi.h
@@ -17,7 +17,7 @@
 #include <linux/numa.h>
 #include <asm/numa.h>
 
-#ifdef	CONFIG_ACPI
+
 extern int acpi_lapic;
 #define acpi_disabled 0	/* ACPI always enabled on IA64 */
 #define acpi_noirq 0	/* ACPI always enabled on IA64 */
@@ -28,34 +28,10 @@ static inline bool acpi_has_cpu_in_madt(void)
 {
 	return !!acpi_lapic;
 }
-#endif
+
 #define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */
 static inline void disable_acpi(void) { }
 
-#ifdef CONFIG_IA64_GENERIC
-const char *acpi_get_sysname (void);
-#else
-static inline const char *acpi_get_sysname (void)
-{
-# if defined (CONFIG_IA64_HP_SIM)
-	return "hpsim";
-# elif defined (CONFIG_IA64_HP_ZX1)
-	return "hpzx1";
-# elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
-	return "hpzx1_swiotlb";
-# elif defined (CONFIG_IA64_SGI_SN2)
-	return "sn2";
-# elif defined (CONFIG_IA64_SGI_UV)
-	return "uv";
-# elif defined (CONFIG_IA64_DIG)
-	return "dig";
-# elif defined(CONFIG_IA64_DIG_VTD)
-	return "dig_vtd";
-# else
-#	error Unknown platform.  Fix acpi.c.
-# endif
-}
-#endif
 int acpi_request_vector (u32 int_type);
 int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
 
diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h
index f7ec71e4001e..a5d9d788eede 100644
--- a/arch/ia64/include/asm/dma-mapping.h
+++ b/arch/ia64/include/asm/dma-mapping.h
@@ -6,17 +6,11 @@
  * Copyright (C) 2003-2004 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
-#include <asm/machvec.h>
-#include <linux/scatterlist.h>
-#include <linux/dma-debug.h>
-
 extern const struct dma_map_ops *dma_ops;
-extern struct ia64_machine_vector ia64_mv;
-extern void set_iommu_machvec(void);
 
 static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 {
-	return platform_dma_get_ops(NULL);
+	return dma_ops;
 }
 
 #endif /* _ASM_IA64_DMA_MAPPING_H */
diff --git a/arch/ia64/include/asm/dma.h b/arch/ia64/include/asm/dma.h
index 23604d6a2cb2..59625e9c1f9c 100644
--- a/arch/ia64/include/asm/dma.h
+++ b/arch/ia64/include/asm/dma.h
@@ -12,11 +12,7 @@
 
 extern unsigned long MAX_DMA_ADDRESS;
 
-#ifdef CONFIG_PCI
-  extern int isa_dma_bridge_buggy;
-#else
-# define isa_dma_bridge_buggy 	(0)
-#endif
+extern int isa_dma_bridge_buggy;
 
 #define free_dma(x)
 
diff --git a/arch/ia64/include/asm/hpsim.h b/arch/ia64/include/asm/hpsim.h
deleted file mode 100644
index 00fbd5cc8ab8..000000000000
--- a/arch/ia64/include/asm/hpsim.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASMIA64_HPSIM_H
-#define _ASMIA64_HPSIM_H
-
-#ifndef CONFIG_HP_SIMSERIAL_CONSOLE
-static inline int simcons_register(void) { return 1; }
-#else
-int simcons_register(void);
-#endif
-
-struct tty_driver;
-extern struct tty_driver *hp_simserial_driver;
-
-extern int hpsim_get_irq(int intr);
-void ia64_ctl_trace(long on);
-
-#endif
diff --git a/arch/ia64/include/asm/hw_irq.h b/arch/ia64/include/asm/hw_irq.h
index 5dd3c6485c3a..e6385c7bdeb0 100644
--- a/arch/ia64/include/asm/hw_irq.h
+++ b/arch/ia64/include/asm/hw_irq.h
@@ -12,7 +12,6 @@
 #include <linux/types.h>
 #include <linux/profile.h>
 
-#include <asm/machvec.h>
 #include <asm/ptrace.h>
 #include <asm/smp.h>
 
@@ -56,7 +55,7 @@ typedef u8 ia64_vector;
 extern int ia64_first_device_vector;
 extern int ia64_last_device_vector;
 
-#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_DIG))
+#ifdef CONFIG_SMP
 /* Reserve the lower priority vector than device vectors for "move IRQ" IPI */
 #define IA64_IRQ_MOVE_VECTOR		0x30	/* "move IRQ" IPI */
 #define IA64_DEF_FIRST_DEVICE_VECTOR	0x31
@@ -127,7 +126,7 @@ extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
 extern void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action);
 extern void destroy_and_reserve_irq (unsigned int irq);
 
-#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
+#ifdef CONFIG_SMP
 extern int irq_prepare_move(int irq, int cpu);
 extern void irq_complete_move(unsigned int irq);
 #else
@@ -137,26 +136,10 @@ static inline void irq_complete_move(unsigned int irq) {}
 
 static inline void ia64_native_resend_irq(unsigned int vector)
 {
-	platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
+	ia64_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
 }
 
 /*
- * Default implementations for the irq-descriptor API:
- */
-#ifndef CONFIG_IA64_GENERIC
-static inline ia64_vector __ia64_irq_to_vector(int irq)
-{
-	return irq_cfg[irq].vector;
-}
-
-static inline unsigned int
-__ia64_local_vector_to_irq (ia64_vector vec)
-{
-	return __this_cpu_read(vector_irq[vec]);
-}
-#endif
-
-/*
  * Next follows the irq descriptor interface.  On IA-64, each CPU supports 256 interrupt
  * vectors.  On smaller systems, there is a one-to-one correspondence between interrupt
  * vectors and the Linux irq numbers.  However, larger systems may have multiple interrupt
@@ -170,7 +153,7 @@ __ia64_local_vector_to_irq (ia64_vector vec)
 static inline ia64_vector
 irq_to_vector (int irq)
 {
-	return platform_irq_to_vector(irq);
+	return irq_cfg[irq].vector;
 }
 
 /*
@@ -181,7 +164,7 @@ irq_to_vector (int irq)
 static inline unsigned int
 local_vector_to_irq (ia64_vector vec)
 {
-	return platform_local_vector_to_irq(vec);
+	return __this_cpu_read(vector_irq[vec]);
 }
 
 #endif /* _ASM_IA64_HW_IRQ_H */
diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h
index a511d62d447a..54e70c21352a 100644
--- a/arch/ia64/include/asm/io.h
+++ b/arch/ia64/include/asm/io.h
@@ -71,7 +71,6 @@ extern unsigned int num_io_spaces;
 #define HAVE_ARCH_PIO_SIZE
 
 #include <asm/intrinsics.h>
-#include <asm/machvec.h>
 #include <asm/page.h>
 #include <asm-generic/iomap.h>
 
@@ -129,25 +128,6 @@ __ia64_mk_io_addr (unsigned long port)
 	return (void *) (space->mmio_base | offset);
 }
 
-#define __ia64_inb	___ia64_inb
-#define __ia64_inw	___ia64_inw
-#define __ia64_inl	___ia64_inl
-#define __ia64_outb	___ia64_outb
-#define __ia64_outw	___ia64_outw
-#define __ia64_outl	___ia64_outl
-#define __ia64_readb	___ia64_readb
-#define __ia64_readw	___ia64_readw
-#define __ia64_readl	___ia64_readl
-#define __ia64_readq	___ia64_readq
-#define __ia64_readb_relaxed	___ia64_readb
-#define __ia64_readw_relaxed	___ia64_readw
-#define __ia64_readl_relaxed	___ia64_readl
-#define __ia64_readq_relaxed	___ia64_readq
-#define __ia64_writeb	___ia64_writeb
-#define __ia64_writew	___ia64_writew
-#define __ia64_writel	___ia64_writel
-#define __ia64_writeq	___ia64_writeq
-
 /*
  * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
  * that the access has completed before executing other I/O accesses.  Since we're doing
@@ -156,8 +136,8 @@ __ia64_mk_io_addr (unsigned long port)
  * during optimization, which is why we use "volatile" pointers.
  */
 
-static inline unsigned int
-___ia64_inb (unsigned long port)
+#define inb inb
+static inline unsigned int inb(unsigned long port)
 {
 	volatile unsigned char *addr = __ia64_mk_io_addr(port);
 	unsigned char ret;
@@ -167,8 +147,8 @@ ___ia64_inb (unsigned long port)
 	return ret;
 }
 
-static inline unsigned int
-___ia64_inw (unsigned long port)
+#define inw inw
+static inline unsigned int inw(unsigned long port)
 {
 	volatile unsigned short *addr = __ia64_mk_io_addr(port);
 	unsigned short ret;
@@ -178,8 +158,8 @@ ___ia64_inw (unsigned long port)
 	return ret;
 }
 
-static inline unsigned int
-___ia64_inl (unsigned long port)
+#define inl inl
+static inline unsigned int inl(unsigned long port)
 {
 	volatile unsigned int *addr = __ia64_mk_io_addr(port);
 	unsigned int ret;
@@ -189,8 +169,8 @@ ___ia64_inl (unsigned long port)
 	return ret;
 }
 
-static inline void
-___ia64_outb (unsigned char val, unsigned long port)
+#define outb outb
+static inline void outb(unsigned char val, unsigned long port)
 {
 	volatile unsigned char *addr = __ia64_mk_io_addr(port);
 
@@ -198,8 +178,8 @@ ___ia64_outb (unsigned char val, unsigned long port)
 	__ia64_mf_a();
 }
 
-static inline void
-___ia64_outw (unsigned short val, unsigned long port)
+#define outw outw
+static inline void outw(unsigned short val, unsigned long port)
 {
 	volatile unsigned short *addr = __ia64_mk_io_addr(port);
 
@@ -207,8 +187,8 @@ ___ia64_outw (unsigned short val, unsigned long port)
 	__ia64_mf_a();
 }
 
-static inline void
-___ia64_outl (unsigned int val, unsigned long port)
+#define outl outl
+static inline void outl(unsigned int val, unsigned long port)
 {
 	volatile unsigned int *addr = __ia64_mk_io_addr(port);
 
@@ -216,199 +196,63 @@ ___ia64_outl (unsigned int val, unsigned long port)
 	__ia64_mf_a();
 }
 
-static inline void
-__insb (unsigned long port, void *dst, unsigned long count)
+#define insb insb
+static inline void insb(unsigned long port, void *dst, unsigned long count)
 {
 	unsigned char *dp = dst;
 
 	while (count--)
-		*dp++ = platform_inb(port);
+		*dp++ = inb(port);
 }
 
-static inline void
-__insw (unsigned long port, void *dst, unsigned long count)
+#define insw insw
+static inline void insw(unsigned long port, void *dst, unsigned long count)
 {
 	unsigned short *dp = dst;
 
 	while (count--)
-		put_unaligned(platform_inw(port), dp++);
+		put_unaligned(inw(port), dp++);
 }
 
-static inline void
-__insl (unsigned long port, void *dst, unsigned long count)
+#define insl insl
+static inline void insl(unsigned long port, void *dst, unsigned long count)
 {
 	unsigned int *dp = dst;
 
 	while (count--)
-		put_unaligned(platform_inl(port), dp++);
+		put_unaligned(inl(port), dp++);
 }
 
-static inline void
-__outsb (unsigned long port, const void *src, unsigned long count)
+#define outsb outsb
+static inline void outsb(unsigned long port, const void *src,
+		unsigned long count)
 {
 	const unsigned char *sp = src;
 
 	while (count--)
-		platform_outb(*sp++, port);
+		outb(*sp++, port);
 }
 
-static inline void
-__outsw (unsigned long port, const void *src, unsigned long count)
+#define outsw outsw
+static inline void outsw(unsigned long port, const void *src,
+		unsigned long count)
 {
 	const unsigned short *sp = src;
 
 	while (count--)
-		platform_outw(get_unaligned(sp++), port);
+		outw(get_unaligned(sp++), port);
 }
 
-static inline void
-__outsl (unsigned long port, const void *src, unsigned long count)
+#define outsl outsl
+static inline void outsl(unsigned long port, const void *src,
+		unsigned long count)
 {
 	const unsigned int *sp = src;
 
 	while (count--)
-		platform_outl(get_unaligned(sp++), port);
+		outl(get_unaligned(sp++), port);
 }
 
-/*
- * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
- * specification regarding legacy I/O support.  Thus, we have to make these operations
- * platform dependent...
- */
-#define __inb		platform_inb
-#define __inw		platform_inw
-#define __inl		platform_inl
-#define __outb		platform_outb
-#define __outw		platform_outw
-#define __outl		platform_outl
-
-#define inb(p)		__inb(p)
-#define inw(p)		__inw(p)
-#define inl(p)		__inl(p)
-#define insb(p,d,c)	__insb(p,d,c)
-#define insw(p,d,c)	__insw(p,d,c)
-#define insl(p,d,c)	__insl(p,d,c)
-#define outb(v,p)	__outb(v,p)
-#define outw(v,p)	__outw(v,p)
-#define outl(v,p)	__outl(v,p)
-#define outsb(p,s,c)	__outsb(p,s,c)
-#define outsw(p,s,c)	__outsw(p,s,c)
-#define outsl(p,s,c)	__outsl(p,s,c)
-
-/*
- * The address passed to these functions are ioremap()ped already.
- *
- * We need these to be machine vectors since some platforms don't provide
- * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
- * a good idea).  Writes are ok though for all existing ia64 platforms (and
- * hopefully it'll stay that way).
- */
-static inline unsigned char
-___ia64_readb (const volatile void __iomem *addr)
-{
-	return *(volatile unsigned char __force *)addr;
-}
-
-static inline unsigned short
-___ia64_readw (const volatile void __iomem *addr)
-{
-	return *(volatile unsigned short __force *)addr;
-}
-
-static inline unsigned int
-___ia64_readl (const volatile void __iomem *addr)
-{
-	return *(volatile unsigned int __force *) addr;
-}
-
-static inline unsigned long
-___ia64_readq (const volatile void __iomem *addr)
-{
-	return *(volatile unsigned long __force *) addr;
-}
-
-static inline void
-__writeb (unsigned char val, volatile void __iomem *addr)
-{
-	*(volatile unsigned char __force *) addr = val;
-}
-
-static inline void
-__writew (unsigned short val, volatile void __iomem *addr)
-{
-	*(volatile unsigned short __force *) addr = val;
-}
-
-static inline void
-__writel (unsigned int val, volatile void __iomem *addr)
-{
-	*(volatile unsigned int __force *) addr = val;
-}
-
-static inline void
-__writeq (unsigned long val, volatile void __iomem *addr)
-{
-	*(volatile unsigned long __force *) addr = val;
-}
-
-#define __readb		platform_readb
-#define __readw		platform_readw
-#define __readl		platform_readl
-#define __readq		platform_readq
-#define __readb_relaxed	platform_readb_relaxed
-#define __readw_relaxed	platform_readw_relaxed
-#define __readl_relaxed	platform_readl_relaxed
-#define __readq_relaxed	platform_readq_relaxed
-
-#define readb(a)	__readb((a))
-#define readw(a)	__readw((a))
-#define readl(a)	__readl((a))
-#define readq(a)	__readq((a))
-#define readb_relaxed(a)	__readb_relaxed((a))
-#define readw_relaxed(a)	__readw_relaxed((a))
-#define readl_relaxed(a)	__readl_relaxed((a))
-#define readq_relaxed(a)	__readq_relaxed((a))
-#define __raw_readb	readb
-#define __raw_readw	readw
-#define __raw_readl	readl
-#define __raw_readq	readq
-#define __raw_readb_relaxed	readb_relaxed
-#define __raw_readw_relaxed	readw_relaxed
-#define __raw_readl_relaxed	readl_relaxed
-#define __raw_readq_relaxed	readq_relaxed
-#define writeb(v,a)	__writeb((v), (a))
-#define writew(v,a)	__writew((v), (a))
-#define writel(v,a)	__writel((v), (a))
-#define writeq(v,a)	__writeq((v), (a))
-#define writeb_relaxed(v,a)	__writeb((v), (a))
-#define writew_relaxed(v,a)	__writew((v), (a))
-#define writel_relaxed(v,a)	__writel((v), (a))
-#define writeq_relaxed(v,a)	__writeq((v), (a))
-#define __raw_writeb	writeb
-#define __raw_writew	writew
-#define __raw_writel	writel
-#define __raw_writeq	writeq
-
-#ifndef inb_p
-# define inb_p		inb
-#endif
-#ifndef inw_p
-# define inw_p		inw
-#endif
-#ifndef inl_p
-# define inl_p		inl
-#endif
-
-#ifndef outb_p
-# define outb_p		outb
-#endif
-#ifndef outw_p
-# define outw_p		outw
-#endif
-#ifndef outl_p
-# define outl_p		outl
-#endif
-
 # ifdef __KERNEL__
 
 extern void __iomem * ioremap(unsigned long offset, unsigned long size);
diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h
index 92aceef63710..7904f591a79b 100644
--- a/arch/ia64/include/asm/iommu.h
+++ b/arch/ia64/include/asm/iommu.h
@@ -13,6 +13,5 @@ extern int iommu_detected;
 #define no_iommu		(1)
 #define iommu_detected		(0)
 #endif
-extern void machvec_init(const char *name);
 
 #endif
diff --git a/arch/ia64/include/asm/iosapic.h b/arch/ia64/include/asm/iosapic.h
index f48556cb8afc..a91aeb413e17 100644
--- a/arch/ia64/include/asm/iosapic.h
+++ b/arch/ia64/include/asm/iosapic.h
@@ -52,8 +52,6 @@
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_IOSAPIC
-
 #define NR_IOSAPICS			256
 
 #define iosapic_pcat_compat_init	ia64_native_iosapic_pcat_compat_init
@@ -103,16 +101,6 @@ extern int __init iosapic_register_platform_intr (u32 int_type,
 #ifdef CONFIG_NUMA
 extern void map_iosapic_to_node (unsigned int, int);
 #endif
-#else
-#define iosapic_system_init(pcat_compat)			do { } while (0)
-#define iosapic_init(address,gsi_base)				(-EINVAL)
-#define iosapic_remove(gsi_base)				(-ENODEV)
-#define iosapic_register_intr(gsi,polarity,trigger)		(gsi)
-#define iosapic_unregister_intr(irq)				do { } while (0)
-#define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger)	do { } while (0)
-#define iosapic_register_platform_intr(type,gsi,pmi,eid,id, \
-	polarity,trigger)					(gsi)
-#endif
 
 # endif /* !__ASSEMBLY__ */
 #endif /* __ASM_IA64_IOSAPIC_H */
diff --git a/arch/ia64/include/asm/irq.h b/arch/ia64/include/asm/irq.h
index 8b84a55ed38a..5acf52e90872 100644
--- a/arch/ia64/include/asm/irq.h
+++ b/arch/ia64/include/asm/irq.h
@@ -28,9 +28,6 @@ irq_canonicalize (int irq)
 }
 
 extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
-bool is_affinity_mask_valid(const struct cpumask *cpumask);
-
-#define is_affinity_mask_valid is_affinity_mask_valid
 
 int create_irq(void);
 void destroy_irq(unsigned int irq);
diff --git a/arch/ia64/include/asm/machvec.h b/arch/ia64/include/asm/machvec.h
deleted file mode 100644
index beae261fbcb4..000000000000
--- a/arch/ia64/include/asm/machvec.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Machine vector for IA-64.
- *
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
- * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
- * Copyright (C) 1999-2001, 2003-2004 Hewlett-Packard Co.
- *	David Mosberger-Tang <davidm@hpl.hp.com>
- */
-#ifndef _ASM_IA64_MACHVEC_H
-#define _ASM_IA64_MACHVEC_H
-
-#include <linux/types.h>
-
-/* forward declarations: */
-struct device;
-struct pt_regs;
-struct scatterlist;
-struct page;
-struct mm_struct;
-struct pci_bus;
-struct task_struct;
-struct pci_dev;
-struct msi_desc;
-
-typedef void ia64_mv_setup_t (char **);
-typedef void ia64_mv_cpu_init_t (void);
-typedef void ia64_mv_irq_init_t (void);
-typedef void ia64_mv_send_ipi_t (int, int, int, int);
-typedef void ia64_mv_timer_interrupt_t (int, void *);
-typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long);
-typedef u8 ia64_mv_irq_to_vector (int);
-typedef unsigned int ia64_mv_local_vector_to_irq (u8);
-typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *);
-typedef int ia64_mv_pci_legacy_read_t (struct pci_bus *, u16 port, u32 *val,
-				       u8 size);
-typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
-					u8 size);
-typedef void ia64_mv_migrate_t(struct task_struct * task);
-typedef void ia64_mv_pci_fixup_bus_t (struct pci_bus *);
-typedef void ia64_mv_kernel_launch_event_t(void);
-
-/* DMA-mapping interface: */
-typedef void ia64_mv_dma_init (void);
-typedef const struct dma_map_ops *ia64_mv_dma_get_ops(struct device *);
-
-/*
- * WARNING: The legacy I/O space is _architected_.  Platforms are
- * expected to follow this architected model (see Section 10.7 in the
- * IA-64 Architecture Software Developer's Manual).  Unfortunately,
- * some broken machines do not follow that model, which is why we have
- * to make the inX/outX operations part of the machine vector.
- * Platform designers should follow the architected model whenever
- * possible.
- */
-typedef unsigned int ia64_mv_inb_t (unsigned long);
-typedef unsigned int ia64_mv_inw_t (unsigned long);
-typedef unsigned int ia64_mv_inl_t (unsigned long);
-typedef void ia64_mv_outb_t (unsigned char, unsigned long);
-typedef void ia64_mv_outw_t (unsigned short, unsigned long);
-typedef void ia64_mv_outl_t (unsigned int, unsigned long);
-typedef void ia64_mv_mmiowb_t (void);
-typedef unsigned char ia64_mv_readb_t (const volatile void __iomem *);
-typedef unsigned short ia64_mv_readw_t (const volatile void __iomem *);
-typedef unsigned int ia64_mv_readl_t (const volatile void __iomem *);
-typedef unsigned long ia64_mv_readq_t (const volatile void __iomem *);
-typedef unsigned char ia64_mv_readb_relaxed_t (const volatile void __iomem *);
-typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *);
-typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *);
-typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *);
-
-typedef int ia64_mv_setup_msi_irq_t (struct pci_dev *pdev, struct msi_desc *);
-typedef void ia64_mv_teardown_msi_irq_t (unsigned int irq);
-
-static inline void
-machvec_noop (void)
-{
-}
-
-static inline void
-machvec_noop_task (struct task_struct *task)
-{
-}
-
-static inline void
-machvec_noop_bus (struct pci_bus *bus)
-{
-}
-
-extern void machvec_setup (char **);
-extern void machvec_timer_interrupt (int, void *);
-
-# if defined (CONFIG_IA64_HP_SIM)
-#  include <asm/machvec_hpsim.h>
-# elif defined (CONFIG_IA64_DIG)
-#  include <asm/machvec_dig.h>
-# elif defined(CONFIG_IA64_DIG_VTD)
-#  include <asm/machvec_dig_vtd.h>
-# elif defined (CONFIG_IA64_HP_ZX1)
-#  include <asm/machvec_hpzx1.h>
-# elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
-#  include <asm/machvec_hpzx1_swiotlb.h>
-# elif defined (CONFIG_IA64_SGI_SN2)
-#  include <asm/machvec_sn2.h>
-# elif defined (CONFIG_IA64_SGI_UV)
-#  include <asm/machvec_uv.h>
-# elif defined (CONFIG_IA64_GENERIC)
-
-# ifdef MACHVEC_PLATFORM_HEADER
-#  include MACHVEC_PLATFORM_HEADER
-# else
-#  define ia64_platform_name	ia64_mv.name
-#  define platform_setup	ia64_mv.setup
-#  define platform_cpu_init	ia64_mv.cpu_init
-#  define platform_irq_init	ia64_mv.irq_init
-#  define platform_send_ipi	ia64_mv.send_ipi
-#  define platform_timer_interrupt	ia64_mv.timer_interrupt
-#  define platform_global_tlb_purge	ia64_mv.global_tlb_purge
-#  define platform_dma_init		ia64_mv.dma_init
-#  define platform_dma_get_ops		ia64_mv.dma_get_ops
-#  define platform_irq_to_vector	ia64_mv.irq_to_vector
-#  define platform_local_vector_to_irq	ia64_mv.local_vector_to_irq
-#  define platform_pci_get_legacy_mem	ia64_mv.pci_get_legacy_mem
-#  define platform_pci_legacy_read	ia64_mv.pci_legacy_read
-#  define platform_pci_legacy_write	ia64_mv.pci_legacy_write
-#  define platform_inb		ia64_mv.inb
-#  define platform_inw		ia64_mv.inw
-#  define platform_inl		ia64_mv.inl
-#  define platform_outb		ia64_mv.outb
-#  define platform_outw		ia64_mv.outw
-#  define platform_outl		ia64_mv.outl
-#  define platform_mmiowb	ia64_mv.mmiowb
-#  define platform_readb        ia64_mv.readb
-#  define platform_readw        ia64_mv.readw
-#  define platform_readl        ia64_mv.readl
-#  define platform_readq        ia64_mv.readq
-#  define platform_readb_relaxed        ia64_mv.readb_relaxed
-#  define platform_readw_relaxed        ia64_mv.readw_relaxed
-#  define platform_readl_relaxed        ia64_mv.readl_relaxed
-#  define platform_readq_relaxed        ia64_mv.readq_relaxed
-#  define platform_migrate		ia64_mv.migrate
-#  define platform_setup_msi_irq	ia64_mv.setup_msi_irq
-#  define platform_teardown_msi_irq	ia64_mv.teardown_msi_irq
-#  define platform_pci_fixup_bus	ia64_mv.pci_fixup_bus
-#  define platform_kernel_launch_event	ia64_mv.kernel_launch_event
-# endif
-
-/* __attribute__((__aligned__(16))) is required to make size of the
- * structure multiple of 16 bytes.
- * This will fillup the holes created because of section 3.3.1 in
- * Software Conventions guide.
- */
-struct ia64_machine_vector {
-	const char *name;
-	ia64_mv_setup_t *setup;
-	ia64_mv_cpu_init_t *cpu_init;
-	ia64_mv_irq_init_t *irq_init;
-	ia64_mv_send_ipi_t *send_ipi;
-	ia64_mv_timer_interrupt_t *timer_interrupt;
-	ia64_mv_global_tlb_purge_t *global_tlb_purge;
-	ia64_mv_dma_init *dma_init;
-	ia64_mv_dma_get_ops *dma_get_ops;
-	ia64_mv_irq_to_vector *irq_to_vector;
-	ia64_mv_local_vector_to_irq *local_vector_to_irq;
-	ia64_mv_pci_get_legacy_mem_t *pci_get_legacy_mem;
-	ia64_mv_pci_legacy_read_t *pci_legacy_read;
-	ia64_mv_pci_legacy_write_t *pci_legacy_write;
-	ia64_mv_inb_t *inb;
-	ia64_mv_inw_t *inw;
-	ia64_mv_inl_t *inl;
-	ia64_mv_outb_t *outb;
-	ia64_mv_outw_t *outw;
-	ia64_mv_outl_t *outl;
-	ia64_mv_mmiowb_t *mmiowb;
-	ia64_mv_readb_t *readb;
-	ia64_mv_readw_t *readw;
-	ia64_mv_readl_t *readl;
-	ia64_mv_readq_t *readq;
-	ia64_mv_readb_relaxed_t *readb_relaxed;
-	ia64_mv_readw_relaxed_t *readw_relaxed;
-	ia64_mv_readl_relaxed_t *readl_relaxed;
-	ia64_mv_readq_relaxed_t *readq_relaxed;
-	ia64_mv_migrate_t *migrate;
-	ia64_mv_setup_msi_irq_t *setup_msi_irq;
-	ia64_mv_teardown_msi_irq_t *teardown_msi_irq;
-	ia64_mv_pci_fixup_bus_t *pci_fixup_bus;
-	ia64_mv_kernel_launch_event_t *kernel_launch_event;
-} __attribute__((__aligned__(16))); /* align attrib? see above comment */
-
-#define MACHVEC_INIT(name)			\
-{						\
-	#name,					\
-	platform_setup,				\
-	platform_cpu_init,			\
-	platform_irq_init,			\
-	platform_send_ipi,			\
-	platform_timer_interrupt,		\
-	platform_global_tlb_purge,		\
-	platform_dma_init,			\
-	platform_dma_get_ops,			\
-	platform_irq_to_vector,			\
-	platform_local_vector_to_irq,		\
-	platform_pci_get_legacy_mem,		\
-	platform_pci_legacy_read,		\
-	platform_pci_legacy_write,		\
-	platform_inb,				\
-	platform_inw,				\
-	platform_inl,				\
-	platform_outb,				\
-	platform_outw,				\
-	platform_outl,				\
-	platform_mmiowb,			\
-	platform_readb,				\
-	platform_readw,				\
-	platform_readl,				\
-	platform_readq,				\
-	platform_readb_relaxed,			\
-	platform_readw_relaxed,			\
-	platform_readl_relaxed,			\
-	platform_readq_relaxed,			\
-	platform_migrate,			\
-	platform_setup_msi_irq,			\
-	platform_teardown_msi_irq,		\
-	platform_pci_fixup_bus,			\
-	platform_kernel_launch_event            \
-}
-
-extern struct ia64_machine_vector ia64_mv;
-extern void machvec_init (const char *name);
-extern void machvec_init_from_cmdline(const char *cmdline);
-
-# else
-#  error Unknown configuration.  Update arch/ia64/include/asm/machvec.h.
-# endif /* CONFIG_IA64_GENERIC */
-
-extern void swiotlb_dma_init(void);
-extern const struct dma_map_ops *dma_get_ops(struct device *);
-
-/*
- * Define default versions so we can extend machvec for new platforms without having
- * to update the machvec files for all existing platforms.
- */
-#ifndef platform_setup
-# define platform_setup			machvec_setup
-#endif
-#ifndef platform_cpu_init
-# define platform_cpu_init		machvec_noop
-#endif
-#ifndef platform_irq_init
-# define platform_irq_init		machvec_noop
-#endif
-
-#ifndef platform_send_ipi
-# define platform_send_ipi		ia64_send_ipi	/* default to architected version */
-#endif
-#ifndef platform_timer_interrupt
-# define platform_timer_interrupt 	machvec_timer_interrupt
-#endif
-#ifndef platform_global_tlb_purge
-# define platform_global_tlb_purge	ia64_global_tlb_purge /* default to architected version */
-#endif
-#ifndef platform_kernel_launch_event
-# define platform_kernel_launch_event	machvec_noop
-#endif
-#ifndef platform_dma_init
-# define platform_dma_init		swiotlb_dma_init
-#endif
-#ifndef platform_dma_get_ops
-# define platform_dma_get_ops		dma_get_ops
-#endif
-#ifndef platform_irq_to_vector
-# define platform_irq_to_vector		__ia64_irq_to_vector
-#endif
-#ifndef platform_local_vector_to_irq
-# define platform_local_vector_to_irq	__ia64_local_vector_to_irq
-#endif
-#ifndef platform_pci_get_legacy_mem
-# define platform_pci_get_legacy_mem	ia64_pci_get_legacy_mem
-#endif
-#ifndef platform_pci_legacy_read
-# define platform_pci_legacy_read	ia64_pci_legacy_read
-extern int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size);
-#endif
-#ifndef platform_pci_legacy_write
-# define platform_pci_legacy_write	ia64_pci_legacy_write
-extern int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size);
-#endif
-#ifndef platform_inb
-# define platform_inb		__ia64_inb
-#endif
-#ifndef platform_inw
-# define platform_inw		__ia64_inw
-#endif
-#ifndef platform_inl
-# define platform_inl		__ia64_inl
-#endif
-#ifndef platform_outb
-# define platform_outb		__ia64_outb
-#endif
-#ifndef platform_outw
-# define platform_outw		__ia64_outw
-#endif
-#ifndef platform_outl
-# define platform_outl		__ia64_outl
-#endif
-#ifndef platform_mmiowb
-# define platform_mmiowb	__ia64_mmiowb
-#endif
-#ifndef platform_readb
-# define platform_readb		__ia64_readb
-#endif
-#ifndef platform_readw
-# define platform_readw		__ia64_readw
-#endif
-#ifndef platform_readl
-# define platform_readl		__ia64_readl
-#endif
-#ifndef platform_readq
-# define platform_readq		__ia64_readq
-#endif
-#ifndef platform_readb_relaxed
-# define platform_readb_relaxed	__ia64_readb_relaxed
-#endif
-#ifndef platform_readw_relaxed
-# define platform_readw_relaxed	__ia64_readw_relaxed
-#endif
-#ifndef platform_readl_relaxed
-# define platform_readl_relaxed	__ia64_readl_relaxed
-#endif
-#ifndef platform_readq_relaxed
-# define platform_readq_relaxed	__ia64_readq_relaxed
-#endif
-#ifndef platform_migrate
-# define platform_migrate machvec_noop_task
-#endif
-#ifndef platform_setup_msi_irq
-# define platform_setup_msi_irq		((ia64_mv_setup_msi_irq_t*)NULL)
-#endif
-#ifndef platform_teardown_msi_irq
-# define platform_teardown_msi_irq	((ia64_mv_teardown_msi_irq_t*)NULL)
-#endif
-#ifndef platform_pci_fixup_bus
-# define platform_pci_fixup_bus	machvec_noop_bus
-#endif
-
-#endif /* _ASM_IA64_MACHVEC_H */
diff --git a/arch/ia64/include/asm/machvec_dig.h b/arch/ia64/include/asm/machvec_dig.h
deleted file mode 100644
index bc230f69faeb..000000000000
--- a/arch/ia64/include/asm/machvec_dig.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_IA64_MACHVEC_DIG_h
-#define _ASM_IA64_MACHVEC_DIG_h
-
-extern ia64_mv_setup_t dig_setup;
-
-/*
- * This stuff has dual use!
- *
- * For a generic kernel, the macros are used to initialize the
- * platform's machvec structure.  When compiling a non-generic kernel,
- * the macros are used directly.
- */
-#define ia64_platform_name	"dig"
-#define platform_setup		dig_setup
-
-#endif /* _ASM_IA64_MACHVEC_DIG_h */
diff --git a/arch/ia64/include/asm/machvec_dig_vtd.h b/arch/ia64/include/asm/machvec_dig_vtd.h
deleted file mode 100644
index bb44eb9039dd..000000000000
--- a/arch/ia64/include/asm/machvec_dig_vtd.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_IA64_MACHVEC_DIG_VTD_h
-#define _ASM_IA64_MACHVEC_DIG_VTD_h
-
-extern ia64_mv_setup_t			dig_setup;
-extern ia64_mv_dma_init			pci_iommu_alloc;
-
-/*
- * This stuff has dual use!
- *
- * For a generic kernel, the macros are used to initialize the
- * platform's machvec structure.  When compiling a non-generic kernel,
- * the macros are used directly.
- */
-#define ia64_platform_name			"dig_vtd"
-#define platform_setup				dig_setup
-#define platform_dma_init			pci_iommu_alloc
-
-#endif /* _ASM_IA64_MACHVEC_DIG_VTD_h */
diff --git a/arch/ia64/include/asm/machvec_hpsim.h b/arch/ia64/include/asm/machvec_hpsim.h
deleted file mode 100644
index 056f8405822e..000000000000
--- a/arch/ia64/include/asm/machvec_hpsim.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_IA64_MACHVEC_HPSIM_h
-#define _ASM_IA64_MACHVEC_HPSIM_h
-
-extern ia64_mv_setup_t hpsim_setup;
-extern ia64_mv_irq_init_t hpsim_irq_init;
-
-/*
- * This stuff has dual use!
- *
- * For a generic kernel, the macros are used to initialize the
- * platform's machvec structure.  When compiling a non-generic kernel,
- * the macros are used directly.
- */
-#define ia64_platform_name	"hpsim"
-#define platform_setup		hpsim_setup
-#define platform_irq_init	hpsim_irq_init
-
-#endif /* _ASM_IA64_MACHVEC_HPSIM_h */
diff --git a/arch/ia64/include/asm/machvec_hpzx1.h b/arch/ia64/include/asm/machvec_hpzx1.h
deleted file mode 100644
index 5299ac38bfb6..000000000000
--- a/arch/ia64/include/asm/machvec_hpzx1.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_IA64_MACHVEC_HPZX1_h
-#define _ASM_IA64_MACHVEC_HPZX1_h
-
-extern ia64_mv_setup_t			dig_setup;
-extern ia64_mv_dma_init			sba_dma_init;
-
-/*
- * This stuff has dual use!
- *
- * For a generic kernel, the macros are used to initialize the
- * platform's machvec structure.  When compiling a non-generic kernel,
- * the macros are used directly.
- */
-#define ia64_platform_name			"hpzx1"
-#define platform_setup				dig_setup
-#define platform_dma_init			sba_dma_init
-
-#endif /* _ASM_IA64_MACHVEC_HPZX1_h */
diff --git a/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h b/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
deleted file mode 100644
index 5aec6a008c61..000000000000
--- a/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
-#define _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
-
-extern ia64_mv_setup_t				dig_setup;
-extern ia64_mv_dma_get_ops			hwsw_dma_get_ops;
-
-/*
- * This stuff has dual use!
- *
- * For a generic kernel, the macros are used to initialize the
- * platform's machvec structure.  When compiling a non-generic kernel,
- * the macros are used directly.
- */
-#define ia64_platform_name			"hpzx1_swiotlb"
-#define platform_setup				dig_setup
-#define platform_dma_init			machvec_noop
-#define platform_dma_get_ops			hwsw_dma_get_ops
-
-#endif /* _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h */
diff --git a/arch/ia64/include/asm/machvec_init.h b/arch/ia64/include/asm/machvec_init.h
deleted file mode 100644
index 2aafb69a3787..000000000000
--- a/arch/ia64/include/asm/machvec_init.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <asm/iommu.h>
-#include <asm/machvec.h>
-
-extern ia64_mv_send_ipi_t ia64_send_ipi;
-extern ia64_mv_global_tlb_purge_t ia64_global_tlb_purge;
-extern ia64_mv_irq_to_vector __ia64_irq_to_vector;
-extern ia64_mv_local_vector_to_irq __ia64_local_vector_to_irq;
-extern ia64_mv_pci_get_legacy_mem_t ia64_pci_get_legacy_mem;
-extern ia64_mv_pci_legacy_read_t ia64_pci_legacy_read;
-extern ia64_mv_pci_legacy_write_t ia64_pci_legacy_write;
-
-extern ia64_mv_inb_t __ia64_inb;
-extern ia64_mv_inw_t __ia64_inw;
-extern ia64_mv_inl_t __ia64_inl;
-extern ia64_mv_outb_t __ia64_outb;
-extern ia64_mv_outw_t __ia64_outw;
-extern ia64_mv_outl_t __ia64_outl;
-extern ia64_mv_mmiowb_t __ia64_mmiowb;
-extern ia64_mv_readb_t __ia64_readb;
-extern ia64_mv_readw_t __ia64_readw;
-extern ia64_mv_readl_t __ia64_readl;
-extern ia64_mv_readq_t __ia64_readq;
-extern ia64_mv_readb_t __ia64_readb_relaxed;
-extern ia64_mv_readw_t __ia64_readw_relaxed;
-extern ia64_mv_readl_t __ia64_readl_relaxed;
-extern ia64_mv_readq_t __ia64_readq_relaxed;
-
-#define MACHVEC_HELPER(name)									\
- struct ia64_machine_vector machvec_##name __attribute__ ((unused, __section__ (".machvec")))	\
-	= MACHVEC_INIT(name);
-
-#define MACHVEC_DEFINE(name)	MACHVEC_HELPER(name)
-
-MACHVEC_DEFINE(MACHVEC_PLATFORM_NAME)
diff --git a/arch/ia64/include/asm/machvec_sn2.h b/arch/ia64/include/asm/machvec_sn2.h
deleted file mode 100644
index a243e4fb4877..000000000000
--- a/arch/ia64/include/asm/machvec_sn2.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) 2002-2003,2006 Silicon Graphics, Inc.  All Rights Reserved.
- * 
- * This program is free software; you can redistribute it and/or modify it 
- * under the terms of version 2 of the GNU General Public License 
- * as published by the Free Software Foundation.
- * 
- * This program is distributed in the hope that it would be useful, but 
- * WITHOUT ANY WARRANTY; without even the implied warranty of 
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
- * 
- * Further, this software is distributed without any warranty that it is 
- * free of the rightful claim of any third person regarding infringement 
- * or the like.  Any license provided herein, whether implied or 
- * otherwise, applies only to this software file.  Patent licenses, if 
- * any, provided herein do not apply to combinations of this program with 
- * other software, or any other product whatsoever.
- * 
- * You should have received a copy of the GNU General Public 
- * License along with this program; if not, write the Free Software 
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- * 
- * For further information regarding this notice, see: 
- * 
- * http://oss.sgi.com/projects/GenInfo/NoticeExplan
- */
-
-#ifndef _ASM_IA64_MACHVEC_SN2_H
-#define _ASM_IA64_MACHVEC_SN2_H
-
-extern ia64_mv_setup_t sn_setup;
-extern ia64_mv_cpu_init_t sn_cpu_init;
-extern ia64_mv_irq_init_t sn_irq_init;
-extern ia64_mv_send_ipi_t sn2_send_IPI;
-extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
-extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
-extern ia64_mv_irq_to_vector sn_irq_to_vector;
-extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
-extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
-extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
-extern ia64_mv_pci_legacy_write_t sn_pci_legacy_write;
-extern ia64_mv_inb_t __sn_inb;
-extern ia64_mv_inw_t __sn_inw;
-extern ia64_mv_inl_t __sn_inl;
-extern ia64_mv_outb_t __sn_outb;
-extern ia64_mv_outw_t __sn_outw;
-extern ia64_mv_outl_t __sn_outl;
-extern ia64_mv_mmiowb_t __sn_mmiowb;
-extern ia64_mv_readb_t __sn_readb;
-extern ia64_mv_readw_t __sn_readw;
-extern ia64_mv_readl_t __sn_readl;
-extern ia64_mv_readq_t __sn_readq;
-extern ia64_mv_readb_t __sn_readb_relaxed;
-extern ia64_mv_readw_t __sn_readw_relaxed;
-extern ia64_mv_readl_t __sn_readl_relaxed;
-extern ia64_mv_readq_t __sn_readq_relaxed;
-extern ia64_mv_dma_init			sn_dma_init;
-extern ia64_mv_migrate_t		sn_migrate;
-extern ia64_mv_kernel_launch_event_t	sn_kernel_launch_event;
-extern ia64_mv_setup_msi_irq_t		sn_setup_msi_irq;
-extern ia64_mv_teardown_msi_irq_t	sn_teardown_msi_irq;
-extern ia64_mv_pci_fixup_bus_t		sn_pci_fixup_bus;
-
-
-/*
- * This stuff has dual use!
- *
- * For a generic kernel, the macros are used to initialize the
- * platform's machvec structure.  When compiling a non-generic kernel,
- * the macros are used directly.
- */
-#define ia64_platform_name		"sn2"
-#define platform_setup			sn_setup
-#define platform_cpu_init		sn_cpu_init
-#define platform_irq_init		sn_irq_init
-#define platform_send_ipi		sn2_send_IPI
-#define platform_timer_interrupt	sn_timer_interrupt
-#define platform_global_tlb_purge       sn2_global_tlb_purge
-#define platform_pci_fixup		sn_pci_fixup
-#define platform_inb			__sn_inb
-#define platform_inw			__sn_inw
-#define platform_inl			__sn_inl
-#define platform_outb			__sn_outb
-#define platform_outw			__sn_outw
-#define platform_outl			__sn_outl
-#define platform_mmiowb			__sn_mmiowb
-#define platform_readb			__sn_readb
-#define platform_readw			__sn_readw
-#define platform_readl			__sn_readl
-#define platform_readq			__sn_readq
-#define platform_readb_relaxed		__sn_readb_relaxed
-#define platform_readw_relaxed		__sn_readw_relaxed
-#define platform_readl_relaxed		__sn_readl_relaxed
-#define platform_readq_relaxed		__sn_readq_relaxed
-#define platform_irq_to_vector		sn_irq_to_vector
-#define platform_local_vector_to_irq	sn_local_vector_to_irq
-#define platform_pci_get_legacy_mem	sn_pci_get_legacy_mem
-#define platform_pci_legacy_read	sn_pci_legacy_read
-#define platform_pci_legacy_write	sn_pci_legacy_write
-#define platform_dma_init		sn_dma_init
-#define platform_migrate		sn_migrate
-#define platform_kernel_launch_event    sn_kernel_launch_event
-#ifdef CONFIG_PCI_MSI
-#define platform_setup_msi_irq		sn_setup_msi_irq
-#define platform_teardown_msi_irq	sn_teardown_msi_irq
-#else
-#define platform_setup_msi_irq		((ia64_mv_setup_msi_irq_t*)NULL)
-#define platform_teardown_msi_irq	((ia64_mv_teardown_msi_irq_t*)NULL)
-#endif
-#define platform_pci_fixup_bus		sn_pci_fixup_bus
-
-#include <asm/sn/io.h>
-
-#endif /* _ASM_IA64_MACHVEC_SN2_H */
diff --git a/arch/ia64/include/asm/machvec_uv.h b/arch/ia64/include/asm/machvec_uv.h
deleted file mode 100644
index 2c50853f35ac..000000000000
--- a/arch/ia64/include/asm/machvec_uv.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI UV Core Functions
- *
- * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_MACHVEC_UV_H
-#define _ASM_IA64_MACHVEC_UV_H
-
-extern ia64_mv_setup_t uv_setup;
-
-/*
- * This stuff has dual use!
- *
- * For a generic kernel, the macros are used to initialize the
- * platform's machvec structure.  When compiling a non-generic kernel,
- * the macros are used directly.
- */
-#define ia64_platform_name		"uv"
-#define platform_setup			uv_setup
-
-#endif /* _ASM_IA64_MACHVEC_UV_H */
diff --git a/arch/ia64/include/asm/mmiowb.h b/arch/ia64/include/asm/mmiowb.h
index 297b85ac84a0..d67aab4ea3b4 100644
--- a/arch/ia64/include/asm/mmiowb.h
+++ b/arch/ia64/include/asm/mmiowb.h
@@ -3,22 +3,14 @@
 #ifndef _ASM_IA64_MMIOWB_H
 #define _ASM_IA64_MMIOWB_H
 
-#include <asm/machvec.h>
-
 /**
- * ___ia64_mmiowb - I/O write barrier
+ * mmiowb - I/O write barrier
  *
  * Ensure ordering of I/O space writes.  This will make sure that writes
  * following the barrier will arrive after all previous writes.  For most
  * ia64 platforms, this is a simple 'mf.a' instruction.
  */
-static inline void ___ia64_mmiowb(void)
-{
-	ia64_mfa();
-}
-
-#define __ia64_mmiowb	___ia64_mmiowb
-#define mmiowb()	platform_mmiowb()
+#define mmiowb()	ia64_mfa()
 
 #include <asm-generic/mmiowb.h>
 
diff --git a/arch/ia64/include/asm/mmzone.h b/arch/ia64/include/asm/mmzone.h
index e0de61709cf1..767201f66c93 100644
--- a/arch/ia64/include/asm/mmzone.h
+++ b/arch/ia64/include/asm/mmzone.h
@@ -27,16 +27,9 @@ static inline int pfn_to_nid(unsigned long pfn)
 		return nid;
 }
 
-#ifdef CONFIG_IA64_DIG /* DIG systems are small */
-# define MAX_PHYSNODE_ID	8
-# define NR_NODE_MEMBLKS	(MAX_NUMNODES * 8)
-#else /* sn2 is the biggest case, so we use that if !DIG */
-# define MAX_PHYSNODE_ID	2048
-# define NR_NODE_MEMBLKS	(MAX_NUMNODES * 4)
-#endif
-
-#else /* CONFIG_NUMA */
-# define NR_NODE_MEMBLKS	(MAX_NUMNODES * 4)
+#define MAX_PHYSNODE_ID		2048
 #endif /* CONFIG_NUMA */
 
+#define NR_NODE_MEMBLKS		(MAX_NUMNODES * 4)
+
 #endif /* _ASM_IA64_MMZONE_H */
diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
index 780e8744ba85..8c163d1d0189 100644
--- a/arch/ia64/include/asm/pci.h
+++ b/arch/ia64/include/asm/pci.h
@@ -39,9 +39,9 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
 				      struct vm_area_struct *vma,
 				      enum pci_mmap_state mmap_state);
 
-#define pci_get_legacy_mem platform_pci_get_legacy_mem
-#define pci_legacy_read platform_pci_legacy_read
-#define pci_legacy_write platform_pci_legacy_write
+char *pci_get_legacy_mem(struct pci_bus *bus);
+int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size);
+int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size);
 
 struct pci_controller {
 	struct acpi_device *companion;
@@ -69,7 +69,4 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 	return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
 }
 
-#ifdef CONFIG_INTEL_IOMMU
-extern void pci_iommu_alloc(void);
-#endif
 #endif /* _ASM_IA64_PCI_H */
diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
index c91ef98ed6bf..95a2ec37400f 100644
--- a/arch/ia64/include/asm/processor.h
+++ b/arch/ia64/include/asm/processor.h
@@ -679,8 +679,6 @@ enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
 
 void default_idle(void);
 
-#define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0)
-
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_IA64_PROCESSOR_H */
diff --git a/arch/ia64/include/asm/sn/acpi.h b/arch/ia64/include/asm/sn/acpi.h
deleted file mode 100644
index fd480db25565..000000000000
--- a/arch/ia64/include/asm/sn/acpi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_ACPI_H
-#define _ASM_IA64_SN_ACPI_H
-
-extern int sn_acpi_rev;
-#define SN_ACPI_BASE_SUPPORT()   (sn_acpi_rev >= 0x20101)
-
-#endif /* _ASM_IA64_SN_ACPI_H */
diff --git a/arch/ia64/include/asm/sn/addrs.h b/arch/ia64/include/asm/sn/addrs.h
deleted file mode 100644
index e715c794b186..000000000000
--- a/arch/ia64/include/asm/sn/addrs.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_ADDRS_H
-#define _ASM_IA64_SN_ADDRS_H
-
-#include <asm/percpu.h>
-#include <asm/sn/types.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/pda.h>
-
-/*
- *  Memory/SHUB Address Format:
- *  +-+---------+--+--------------+
- *  |0|  NASID  |AS| NodeOffset   |
- *  +-+---------+--+--------------+
- *
- *  NASID: (low NASID bit is 0) Memory and SHUB MMRs
- *   AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
- *     00: Local Resources and MMR space
- *           Top bit of NodeOffset
- *               0: Local resources space
- *                  node id:
- *                        0: IA64/NT compatibility space
- *                        2: Local MMR Space
- *                        4: Local memory, regardless of local node id
- *               1: Global MMR space
- *     01: GET space.
- *     10: AMO space.
- *     11: Cacheable memory space.
- *
- *   NodeOffset: byte offset
- *
- *
- *  TIO address format:
- *  +-+----------+--+--------------+
- *  |0|  NASID   |AS| Nodeoffset   |
- *  +-+----------+--+--------------+
- *
- *  NASID: (low NASID bit is 1) TIO
- *   AS: 2-bit Chiplet Identifier
- *     00: TIO LB (Indicates TIO MMR access.)
- *     01: TIO ICE (indicates coretalk space access.)
- * 
- *   NodeOffset: top bit must be set.
- *
- *
- * Note that in both of the above address formats, the low
- * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
- */
-
-
-/*
- * Define basic shift & mask constants for manipulating NASIDs and AS values.
- */
-#define NASID_BITMASK		(sn_hub_info->nasid_bitmask)
-#define NASID_SHIFT		(sn_hub_info->nasid_shift)
-#define AS_SHIFT		(sn_hub_info->as_shift)
-#define AS_BITMASK		0x3UL
-
-#define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
-#define AS_MASK			((u64)AS_BITMASK << AS_SHIFT)
-
-
-/*
- * AS values. These are the same on both SHUB1 & SHUB2.
- */
-#define AS_GET_VAL		1UL
-#define AS_AMO_VAL		2UL
-#define AS_CAC_VAL		3UL
-#define AS_GET_SPACE		(AS_GET_VAL << AS_SHIFT)
-#define AS_AMO_SPACE		(AS_AMO_VAL << AS_SHIFT)
-#define AS_CAC_SPACE		(AS_CAC_VAL << AS_SHIFT)
-
-
-/* 
- * Virtual Mode Local & Global MMR space.  
- */
-#define SH1_LOCAL_MMR_OFFSET	0x8000000000UL
-#define SH2_LOCAL_MMR_OFFSET	0x0200000000UL
-#define LOCAL_MMR_OFFSET	(is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
-#define LOCAL_MMR_SPACE		(__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
-#define LOCAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
-
-#define SH1_GLOBAL_MMR_OFFSET	0x0800000000UL
-#define SH2_GLOBAL_MMR_OFFSET	0x0300000000UL
-#define GLOBAL_MMR_OFFSET	(is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
-#define GLOBAL_MMR_SPACE	(__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
-
-/*
- * Physical mode addresses
- */
-#define GLOBAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
-
-
-/*
- * Clear region & AS bits.
- */
-#define TO_PHYS_MASK		(~(RGN_BITS | AS_MASK))
-
-
-/*
- * Misc NASID manipulation.
- */
-#define NASID_SPACE(n)		((u64)(n) << NASID_SHIFT)
-#define REMOTE_ADDR(n,a)	(NASID_SPACE(n) | (a))
-#define NODE_OFFSET(x)		((x) & (NODE_ADDRSPACE_SIZE - 1))
-#define NODE_ADDRSPACE_SIZE     (1UL << AS_SHIFT)
-#define NASID_GET(x)		(int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
-#define LOCAL_MMR_ADDR(a)	(LOCAL_MMR_SPACE | (a))
-#define GLOBAL_MMR_ADDR(n,a)	(GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
-#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
-#define GLOBAL_CAC_ADDR(n,a)	(CAC_BASE | REMOTE_ADDR(n,a))
-#define CHANGE_NASID(n,x)	((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
-#define IS_TIO_NASID(n)		((n) & 1)
-
-
-/* non-II mmr's start at top of big window space (4G) */
-#define BWIN_TOP		0x0000000100000000UL
-
-/*
- * general address defines
- */
-#define CAC_BASE		(PAGE_OFFSET | AS_CAC_SPACE)
-#define AMO_BASE		(__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
-#define AMO_PHYS_BASE		(RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
-#define GET_BASE		(PAGE_OFFSET | AS_GET_SPACE)
-
-/*
- * Convert Memory addresses between various addressing modes.
- */
-#define TO_PHYS(x)		(TO_PHYS_MASK & (x))
-#define TO_CAC(x)		(CAC_BASE     | TO_PHYS(x))
-#ifdef CONFIG_SGI_SN
-#define TO_AMO(x)		(AMO_BASE     | TO_PHYS(x))
-#define TO_GET(x)		(GET_BASE     | TO_PHYS(x))
-#else
-#define TO_AMO(x)		({ BUG(); x; })
-#define TO_GET(x)		({ BUG(); x; })
-#endif
-
-/*
- * Covert from processor physical address to II/TIO physical address:
- *	II - squeeze out the AS bits
- *	TIO- requires a chiplet id in bits 38-39.  For DMA to memory,
- *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
- *           to insert a chiplet id into this macro.  However, it is our belief
- *           right now that this chiplet id will be ICE, which is also zero.
- */
-#define SH1_TIO_PHYS_TO_DMA(x) 						\
-	((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
-
-#define SH2_NETWORK_BANK_OFFSET(x) 					\
-        ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
-
-#define SH2_NETWORK_BANK_SELECT(x) 					\
-        ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4)))	\
-        	>> (sn_hub_info->nasid_shift - 4)) << 36)
-
-#define SH2_NETWORK_ADDRESS(x) 						\
-	(SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
-
-#define SH2_TIO_PHYS_TO_DMA(x) 						\
-        (((u64)(NASID_GET(x)) << 40) | 	SH2_NETWORK_ADDRESS(x))
-
-#define PHYS_TO_TIODMA(x)						\
-	(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
-
-#define PHYS_TO_DMA(x)							\
-	((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
-
-
-/*
- * Macros to test for address type.
- */
-#define IS_AMO_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
-#define IS_AMO_PHYS_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
-
-
-/*
- * The following definitions pertain to the IO special address
- * space.  They define the location of the big and little windows
- * of any given node.
- */
-#define BWIN_SIZE_BITS			29	/* big window size: 512M */
-#define TIO_BWIN_SIZE_BITS		30	/* big window size: 1G */
-#define NODE_SWIN_BASE(n, w)		((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
-		: RAW_NODE_SWIN_BASE(n, w))
-#define TIO_SWIN_BASE(n, w) 		(TIO_IO_BASE(n) + \
-					    ((u64) (w) << TIO_SWIN_SIZE_BITS))
-#define NODE_IO_BASE(n)			(GLOBAL_MMR_SPACE | NASID_SPACE(n))
-#define TIO_IO_BASE(n)                  (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
-#define BWIN_SIZE			(1UL << BWIN_SIZE_BITS)
-#define NODE_BWIN_BASE0(n)		(NODE_IO_BASE(n) + BWIN_SIZE)
-#define NODE_BWIN_BASE(n, w)		(NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
-#define RAW_NODE_SWIN_BASE(n, w)	(NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
-#define BWIN_WIDGET_MASK		0x7
-#define BWIN_WINDOWNUM(x)		(((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
-#define SH1_IS_BIG_WINDOW_ADDR(x)	((x) & BWIN_TOP)
-
-#define TIO_BWIN_WINDOW_SELECT_MASK	0x7
-#define TIO_BWIN_WINDOWNUM(x)		(((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
-
-#define TIO_HWIN_SHIFT_BITS		33
-#define TIO_HWIN(x)			(NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
-
-/*
- * The following definitions pertain to the IO special address
- * space.  They define the location of the big and little windows
- * of any given node.
- */
-
-#define SWIN_SIZE_BITS			24
-#define	SWIN_WIDGET_MASK		0xF
-
-#define TIO_SWIN_SIZE_BITS		28
-#define TIO_SWIN_SIZE			(1UL << TIO_SWIN_SIZE_BITS)
-#define TIO_SWIN_WIDGET_MASK		0x3
-
-/*
- * Convert smallwindow address to xtalk address.
- *
- * 'addr' can be physical or virtual address, but will be converted
- * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
- */
-#define	SWIN_WIDGETNUM(x)		(((x)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
-#define TIO_SWIN_WIDGETNUM(x)		(((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
-
-
-/*
- * The following macros produce the correct base virtual address for
- * the hub registers. The REMOTE_HUB_* macro produce
- * the address for the specified hub's registers.  The intent is
- * that the appropriate PI, MD, NI, or II register would be substituted
- * for x.
- *
- *   WARNING:
- *	When certain Hub chip workaround are defined, it's not sufficient
- *	to dereference the *_HUB_ADDR() macros.  You should instead use
- *	HUB_L() and HUB_S() if you must deal with pointers to hub registers.
- *	Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
- *	They're always safe.
- */
-/* Shub1 TIO & MMR addressing macros */
-#define SH1_TIO_IOSPACE_ADDR(n,x)					\
-	GLOBAL_MMR_ADDR(n,x)
-
-#define SH1_REMOTE_BWIN_MMR(n,x)					\
-	GLOBAL_MMR_ADDR(n,x)
-
-#define SH1_REMOTE_SWIN_MMR(n,x)					\
-	(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
-
-#define SH1_REMOTE_MMR(n,x)						\
-	(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) :		\
-	 	SH1_REMOTE_SWIN_MMR(n,x))
-
-/* Shub1 TIO & MMR addressing macros */
-#define SH2_TIO_IOSPACE_ADDR(n,x)					\
-	((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
-
-#define SH2_REMOTE_MMR(n,x)						\
-	GLOBAL_MMR_ADDR(n,x)
-
-
-/* TIO & MMR addressing macros that work on both shub1 & shub2 */
-#define TIO_IOSPACE_ADDR(n,x)						\
-	((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) :		\
-		 SH2_TIO_IOSPACE_ADDR(n,x)))
-
-#define SH_REMOTE_MMR(n,x)						\
-	(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
-
-#define REMOTE_HUB_ADDR(n,x)						\
-	(IS_TIO_NASID(n) ?  ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) :	\
-	 ((volatile u64*)SH_REMOTE_MMR(n,x)))
-
-
-#define HUB_L(x)			(*((volatile typeof(*x) *)x))
-#define	HUB_S(x,d)			(*((volatile typeof(*x) *)x) = (d))
-
-#define REMOTE_HUB_L(n, a)		HUB_L(REMOTE_HUB_ADDR((n), (a)))
-#define REMOTE_HUB_S(n, a, d)		HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
-
-/*
- * Coretalk address breakdown
- */
-#define CTALK_NASID_SHFT		40
-#define CTALK_NASID_MASK		(0x3FFFULL << CTALK_NASID_SHFT)
-#define CTALK_CID_SHFT			38
-#define CTALK_CID_MASK			(0x3ULL << CTALK_CID_SHFT)
-#define CTALK_NODE_OFFSET		0x3FFFFFFFFF
-
-#endif /* _ASM_IA64_SN_ADDRS_H */
diff --git a/arch/ia64/include/asm/sn/arch.h b/arch/ia64/include/asm/sn/arch.h
deleted file mode 100644
index 31eb784866f8..000000000000
--- a/arch/ia64/include/asm/sn/arch.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI specific setup.
- *
- * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc.  All rights reserved.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_IA64_SN_ARCH_H
-#define _ASM_IA64_SN_ARCH_H
-
-#include <linux/numa.h>
-#include <asm/types.h>
-#include <asm/percpu.h>
-#include <asm/sn/types.h>
-#include <asm/sn/sn_cpuid.h>
-
-/*
- * This is the maximum number of NUMALINK nodes that can be part of a single
- * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
- * remote partitions are NOT included in this number.
- * The number of compact nodes cannot exceed size of a coherency domain.
- * The purpose of this define is to specify a node count that includes
- * all C/M/TIO nodes in an SSI system.
- *
- * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
- *
- * 	Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
- * 	to ACPI3.0, this limit will be removed. The notion of "compact nodes"
- * 	should be deleted and TIOs should be included in MAX_NUMNODES.
- */
-#define MAX_TIO_NODES		MAX_NUMNODES
-#define MAX_COMPACT_NODES	(MAX_NUMNODES + MAX_TIO_NODES)
-
-/*
- * Maximum number of nodes in all partitions and in all coherency domains.
- * This is the total number of nodes accessible in the numalink fabric. It
- * includes all C & M bricks, plus all TIOs.
- *
- * This value is also the value of the maximum number of NASIDs in the numalink
- * fabric.
- */
-#define MAX_NUMALINK_NODES	16384
-
-/*
- * The following defines attributes of the HUB chip. These attributes are
- * frequently referenced. They are kept in the per-cpu data areas of each cpu.
- * They are kept together in a struct to minimize cache misses.
- */
-struct sn_hub_info_s {
-	u8 shub2;
-	u8 nasid_shift;
-	u8 as_shift;
-	u8 shub_1_1_found;
-	u16 nasid_bitmask;
-};
-DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
-#define sn_hub_info 	this_cpu_ptr(&__sn_hub_info)
-#define is_shub2()	(sn_hub_info->shub2)
-#define is_shub1()	(sn_hub_info->shub2 == 0)
-
-/*
- * Use this macro to test if shub 1.1 wars should be enabled
- */
-#define enable_shub_wars_1_1()	(sn_hub_info->shub_1_1_found)
-
-
-/*
- * Compact node ID to nasid mappings kept in the per-cpu data areas of each
- * cpu.
- */
-DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
-#define sn_cnodeid_to_nasid	this_cpu_ptr(&__sn_cnodeid_to_nasid[0])
-
-
-extern u8 sn_partition_id;
-extern u8 sn_system_size;
-extern u8 sn_sharing_domain_size;
-extern u8 sn_region_size;
-
-extern void sn_flush_all_caches(long addr, long bytes);
-extern bool sn_cpu_disable_allowed(int cpu);
-
-#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/arch/ia64/include/asm/sn/bte.h b/arch/ia64/include/asm/sn/bte.h
deleted file mode 100644
index cd71ab5faf62..000000000000
--- a/arch/ia64/include/asm/sn/bte.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2000-2007 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-
-#ifndef _ASM_IA64_SN_BTE_H
-#define _ASM_IA64_SN_BTE_H
-
-#include <linux/timer.h>
-#include <linux/spinlock.h>
-#include <linux/cache.h>
-#include <asm/sn/pda.h>
-#include <asm/sn/types.h>
-#include <asm/sn/shub_mmr.h>
-
-struct nodepda_s;
-
-#define IBCT_NOTIFY             (0x1UL << 4)
-#define IBCT_ZFIL_MODE          (0x1UL << 0)
-
-/* #define BTE_DEBUG */
-/* #define BTE_DEBUG_VERBOSE */
-
-#ifdef BTE_DEBUG
-#  define BTE_PRINTK(x) printk x	/* Terse */
-#  ifdef BTE_DEBUG_VERBOSE
-#    define BTE_PRINTKV(x) printk x	/* Verbose */
-#  else
-#    define BTE_PRINTKV(x)
-#  endif /* BTE_DEBUG_VERBOSE */
-#else
-#  define BTE_PRINTK(x)
-#  define BTE_PRINTKV(x)
-#endif	/* BTE_DEBUG */
-
-
-/* BTE status register only supports 16 bits for length field */
-#define BTE_LEN_BITS (16)
-#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
-#define BTE_MAX_XFER (BTE_LEN_MASK << L1_CACHE_SHIFT)
-
-
-/* Define hardware */
-#define BTES_PER_NODE (is_shub2() ? 4 : 2)
-#define MAX_BTES_PER_NODE 4
-
-#define BTE2OFF_CTRL	0
-#define BTE2OFF_SRC	(SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
-#define BTE2OFF_DEST	(SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
-#define BTE2OFF_NOTIFY	(SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
-
-#define BTE_BASE_ADDR(interface) 				\
-    (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 :		\
-		  (interface == 1) ? SH2_BT_ENG_CSR_1 :		\
-		  (interface == 2) ? SH2_BT_ENG_CSR_2 :		\
-		  		     SH2_BT_ENG_CSR_3 		\
-		: (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
-
-#define BTE_SOURCE_ADDR(base)					\
-    (is_shub2() ? base + (BTE2OFF_SRC/8) 			\
-		: base + (BTEOFF_SRC/8))
-
-#define BTE_DEST_ADDR(base)					\
-    (is_shub2() ? base + (BTE2OFF_DEST/8) 			\
-		: base + (BTEOFF_DEST/8))
-
-#define BTE_CTRL_ADDR(base)					\
-    (is_shub2() ? base + (BTE2OFF_CTRL/8) 			\
-		: base + (BTEOFF_CTRL/8))
-
-#define BTE_NOTIF_ADDR(base)					\
-    (is_shub2() ? base + (BTE2OFF_NOTIFY/8) 			\
-		: base + (BTEOFF_NOTIFY/8))
-
-/* Define hardware modes */
-#define BTE_NOTIFY IBCT_NOTIFY
-#define BTE_NORMAL BTE_NOTIFY
-#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
-/* Use a reserved bit to let the caller specify a wait for any BTE */
-#define BTE_WACQUIRE 0x4000
-/* Use the BTE on the node with the destination memory */
-#define BTE_USE_DEST (BTE_WACQUIRE << 1)
-/* Use any available BTE interface on any node for the transfer */
-#define BTE_USE_ANY (BTE_USE_DEST << 1)
-/* macro to force the IBCT0 value valid */
-#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
-
-#define BTE_ACTIVE		(IBLS_BUSY | IBLS_ERROR)
-#define BTE_WORD_AVAILABLE	(IBLS_BUSY << 1)
-#define BTE_WORD_BUSY		(~BTE_WORD_AVAILABLE)
-
-/*
- * Some macros to simplify reading.
- * Start with macros to locate the BTE control registers.
- */
-#define BTE_LNSTAT_LOAD(_bte)						\
-			HUB_L(_bte->bte_base_addr)
-#define BTE_LNSTAT_STORE(_bte, _x)					\
-			HUB_S(_bte->bte_base_addr, (_x))
-#define BTE_SRC_STORE(_bte, _x)						\
-({									\
-		u64 __addr = ((_x) & ~AS_MASK);				\
-		if (is_shub2()) 					\
-			__addr = SH2_TIO_PHYS_TO_DMA(__addr);		\
-		HUB_S(_bte->bte_source_addr, __addr);			\
-})
-#define BTE_DEST_STORE(_bte, _x)					\
-({									\
-		u64 __addr = ((_x) & ~AS_MASK);				\
-		if (is_shub2()) 					\
-			__addr = SH2_TIO_PHYS_TO_DMA(__addr);		\
-		HUB_S(_bte->bte_destination_addr, __addr);		\
-})
-#define BTE_CTRL_STORE(_bte, _x)					\
-			HUB_S(_bte->bte_control_addr, (_x))
-#define BTE_NOTIF_STORE(_bte, _x)					\
-({									\
-		u64 __addr = ia64_tpa((_x) & ~AS_MASK);			\
-		if (is_shub2()) 					\
-			__addr = SH2_TIO_PHYS_TO_DMA(__addr);		\
-		HUB_S(_bte->bte_notify_addr, __addr);			\
-})
-
-#define BTE_START_TRANSFER(_bte, _len, _mode)				\
-	is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
-		: BTE_LNSTAT_STORE(_bte, _len);				\
-		  BTE_CTRL_STORE(_bte, _mode)
-
-/* Possible results from bte_copy and bte_unaligned_copy */
-/* The following error codes map into the BTE hardware codes
- * IIO_ICRB_ECODE_* (in shubio.h). The hardware uses
- * an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero
- * to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error
- * codes to give the following error codes.
- */
-#define BTEFAIL_OFFSET	1
-
-typedef enum {
-	BTE_SUCCESS,		/* 0 is success */
-	BTEFAIL_DIR,		/* Directory error due to IIO access*/
-	BTEFAIL_POISON,		/* poison error on IO access (write to poison page) */
-	BTEFAIL_WERR,		/* Write error (ie WINV to a Read only line) */
-	BTEFAIL_ACCESS,		/* access error (protection violation) */
-	BTEFAIL_PWERR,		/* Partial Write Error */
-	BTEFAIL_PRERR,		/* Partial Read Error */
-	BTEFAIL_TOUT,		/* CRB Time out */
-	BTEFAIL_XTERR,		/* Incoming xtalk pkt had error bit */
-	BTEFAIL_NOTAVAIL,	/* BTE not available */
-} bte_result_t;
-
-#define BTEFAIL_SH2_RESP_SHORT	0x1	/* bit 000001 */
-#define BTEFAIL_SH2_RESP_LONG	0x2	/* bit 000010 */
-#define BTEFAIL_SH2_RESP_DSP	0x4	/* bit 000100 */
-#define BTEFAIL_SH2_RESP_ACCESS	0x8	/* bit 001000 */
-#define BTEFAIL_SH2_CRB_TO	0x10	/* bit 010000 */
-#define BTEFAIL_SH2_NACK_LIMIT	0x20	/* bit 100000 */
-#define BTEFAIL_SH2_ALL		0x3F	/* bit 111111 */
-
-#define	BTE_ERR_BITS	0x3FUL
-#define	BTE_ERR_SHIFT	36
-#define BTE_ERR_MASK	(BTE_ERR_BITS << BTE_ERR_SHIFT)
-
-#define BTE_ERROR_RETRY(value)						\
-	(is_shub2() ? (value != BTEFAIL_SH2_CRB_TO)			\
-		: (value != BTEFAIL_TOUT))
-
-/*
- * On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2()
- */
-#define BTE_SHUB2_ERROR(_status)					\
-	((_status & BTE_ERR_MASK) 					\
-	   ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
-	   : _status)
-
-#define BTE_GET_ERROR_STATUS(_status)					\
-	(BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
-
-#define BTE_VALID_SH2_ERROR(value)					\
-	((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
-
-/*
- * Structure defining a bte.  An instance of this
- * structure is created in the nodepda for each
- * bte on that node (as defined by BTES_PER_NODE)
- * This structure contains everything necessary
- * to work with a BTE.
- */
-struct bteinfo_s {
-	volatile u64 notify ____cacheline_aligned;
-	u64 *bte_base_addr ____cacheline_aligned;
-	u64 *bte_source_addr;
-	u64 *bte_destination_addr;
-	u64 *bte_control_addr;
-	u64 *bte_notify_addr;
-	spinlock_t spinlock;
-	cnodeid_t bte_cnode;	/* cnode                            */
-	int bte_error_count;	/* Number of errors encountered     */
-	int bte_num;		/* 0 --> BTE0, 1 --> BTE1           */
-	int cleanup_active;	/* Interface is locked for cleanup  */
-	volatile bte_result_t bh_error;	/* error while processing   */
-	volatile u64 *most_rcnt_na;
-	struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
-};
-
-
-/*
- * Function prototypes (functions defined in bte.c, used elsewhere)
- */
-extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
-extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
-extern void bte_error_handler(struct nodepda_s *);
-
-#define bte_zero(dest, len, mode, notification) \
-	bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
-
-/*
- * The following is the preferred way of calling bte_unaligned_copy
- * If the copy is fully cache line aligned, then bte_copy is
- * used instead.  Since bte_copy is inlined, this saves a call
- * stack.  NOTE: bte_copy is called synchronously and does block
- * until the transfer is complete.  In order to get the asynch
- * version of bte_copy, you must perform this check yourself.
- */
-#define BTE_UNALIGNED_COPY(src, dest, len, mode)			\
-	(((len & (L1_CACHE_BYTES - 1)) ||				\
-	  (src & (L1_CACHE_BYTES - 1)) ||				\
-	  (dest & (L1_CACHE_BYTES - 1))) ?				\
-	 bte_unaligned_copy(src, dest, len, mode) :			\
-	 bte_copy(src, dest, len, mode, NULL))
-
-
-#endif	/* _ASM_IA64_SN_BTE_H */
diff --git a/arch/ia64/include/asm/sn/clksupport.h b/arch/ia64/include/asm/sn/clksupport.h
deleted file mode 100644
index d340c365a824..000000000000
--- a/arch/ia64/include/asm/sn/clksupport.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
- */
-
-/*
- * This file contains definitions for accessing a platform supported high resolution
- * clock. The clock is monitonically increasing and can be accessed from any node
- * in the system. The clock is synchronized across nodes - all nodes see the
- * same value.
- * 
- *	RTC_COUNTER_ADDR - contains the address of the counter 
- *
- */
-
-#ifndef _ASM_IA64_SN_CLKSUPPORT_H
-#define _ASM_IA64_SN_CLKSUPPORT_H
-
-extern unsigned long sn_rtc_cycles_per_second;
-
-#define RTC_COUNTER_ADDR	((long *)LOCAL_MMR_ADDR(SH_RTC))
-
-#define rtc_time()		(*RTC_COUNTER_ADDR)
-
-#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff --git a/arch/ia64/include/asm/sn/geo.h b/arch/ia64/include/asm/sn/geo.h
deleted file mode 100644
index f083c9434066..000000000000
--- a/arch/ia64/include/asm/sn/geo.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_GEO_H
-#define _ASM_IA64_SN_GEO_H
-
-/* The geoid_t implementation below is based loosely on the pcfg_t
-   implementation in sys/SN/promcfg.h. */
-
-/* Type declaractions */
-
-/* Size of a geoid_t structure (must be before decl. of geoid_u) */
-#define GEOID_SIZE	8	/* Would 16 be better?  The size can
-				   be different on different platforms. */
-
-#define MAX_SLOTS	0xf	/* slots per module */
-#define MAX_SLABS	0xf	/* slabs per slot */
-
-typedef unsigned char	geo_type_t;
-
-/* Fields common to all substructures */
-typedef struct geo_common_s {
-    moduleid_t	module;		/* The module (box) this h/w lives in */
-    geo_type_t	type;		/* What type of h/w is named by this geoid_t */
-    slabid_t	slab:4;		/* slab (ASIC), 0 .. 15 within slot */
-    slotid_t	slot:4;		/* slot (Blade), 0 .. 15 within module */
-} geo_common_t;
-
-/* Additional fields for particular types of hardware */
-typedef struct geo_node_s {
-    geo_common_t	common;		/* No additional fields needed */
-} geo_node_t;
-
-typedef struct geo_rtr_s {
-    geo_common_t	common;		/* No additional fields needed */
-} geo_rtr_t;
-
-typedef struct geo_iocntl_s {
-    geo_common_t	common;		/* No additional fields needed */
-} geo_iocntl_t;
-
-typedef struct geo_pcicard_s {
-    geo_iocntl_t	common;
-    char		bus;	/* Bus/widget number */
-    char		slot;	/* PCI slot number */
-} geo_pcicard_t;
-
-/* Subcomponents of a node */
-typedef struct geo_cpu_s {
-    geo_node_t	node;
-    char	slice;		/* Which CPU on the node */
-} geo_cpu_t;
-
-typedef struct geo_mem_s {
-    geo_node_t	node;
-    char	membus;		/* The memory bus on the node */
-    char	memslot;	/* The memory slot on the bus */
-} geo_mem_t;
-
-
-typedef union geoid_u {
-    geo_common_t	common;
-    geo_node_t		node;
-    geo_iocntl_t	iocntl;
-    geo_pcicard_t	pcicard;
-    geo_rtr_t		rtr;
-    geo_cpu_t		cpu;
-    geo_mem_t		mem;
-    char		padsize[GEOID_SIZE];
-} geoid_t;
-
-
-/* Preprocessor macros */
-
-#define GEO_MAX_LEN	48	/* max. formatted length, plus some pad:
-				   module/001c07/slab/5/node/memory/2/slot/4 */
-
-/* Values for geo_type_t */
-#define GEO_TYPE_INVALID	0
-#define GEO_TYPE_MODULE		1
-#define GEO_TYPE_NODE		2
-#define GEO_TYPE_RTR		3
-#define GEO_TYPE_IOCNTL		4
-#define GEO_TYPE_IOCARD		5
-#define GEO_TYPE_CPU		6
-#define GEO_TYPE_MEM		7
-#define GEO_TYPE_MAX		(GEO_TYPE_MEM+1)
-
-/* Parameter for hwcfg_format_geoid_compt() */
-#define GEO_COMPT_MODULE	1
-#define GEO_COMPT_SLAB		2
-#define GEO_COMPT_IOBUS		3
-#define GEO_COMPT_IOSLOT	4
-#define GEO_COMPT_CPU		5
-#define GEO_COMPT_MEMBUS	6
-#define GEO_COMPT_MEMSLOT	7
-
-#define GEO_INVALID_STR		"<invalid>"
-
-#define INVALID_NASID           ((nasid_t)-1)
-#define INVALID_CNODEID         ((cnodeid_t)-1)
-#define INVALID_PNODEID         ((pnodeid_t)-1)
-#define INVALID_SLAB            (slabid_t)-1
-#define INVALID_SLOT            (slotid_t)-1
-#define INVALID_MODULE          ((moduleid_t)-1)
-
-static inline slabid_t geo_slab(geoid_t g)
-{
-	return (g.common.type == GEO_TYPE_INVALID) ?
-		INVALID_SLAB : g.common.slab;
-}
-
-static inline slotid_t geo_slot(geoid_t g)
-{
-	return (g.common.type == GEO_TYPE_INVALID) ?
-		INVALID_SLOT : g.common.slot;
-}
-
-static inline moduleid_t geo_module(geoid_t g)
-{
-	return (g.common.type == GEO_TYPE_INVALID) ?
-		INVALID_MODULE : g.common.module;
-}
-
-extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
-
-#endif /* _ASM_IA64_SN_GEO_H */
diff --git a/arch/ia64/include/asm/sn/intr.h b/arch/ia64/include/asm/sn/intr.h
index e0487aa97418..3885a77b21df 100644
--- a/arch/ia64/include/asm/sn/intr.h
+++ b/arch/ia64/include/asm/sn/intr.h
@@ -9,60 +9,7 @@
 #ifndef _ASM_IA64_SN_INTR_H
 #define _ASM_IA64_SN_INTR_H
 
-#include <linux/rcupdate.h>
-#include <asm/sn/types.h>
-
-#define SGI_UART_VECTOR		0xe9
-
-/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
 #define SGI_XPC_ACTIVATE	0x30
-#define SGI_II_ERROR		0x31
-#define SGI_XBOW_ERROR		0x32
-#define SGI_PCIASIC_ERROR	0x33
-#define SGI_ACPI_SCI_INT	0x34
-#define SGI_TIOCA_ERROR		0x35
-#define SGI_TIO_ERROR		0x36
-#define SGI_TIOCX_ERROR		0x37
-#define SGI_MMTIMER_VECTOR	0x38
 #define SGI_XPC_NOTIFY		0xe7
 
-#define IA64_SN2_FIRST_DEVICE_VECTOR	0x3c
-#define IA64_SN2_LAST_DEVICE_VECTOR	0xe6
-
-#define SN2_IRQ_RESERVED	0x1
-#define SN2_IRQ_CONNECTED	0x2
-#define SN2_IRQ_SHARED		0x4
-
-// The SN PROM irq struct
-struct sn_irq_info {
-	struct sn_irq_info *irq_next;	/* deprecated DO NOT USE     */
-	short		irq_nasid;	/* Nasid IRQ is assigned to  */
-	int		irq_slice;	/* slice IRQ is assigned to  */
-	int		irq_cpuid;	/* kernel logical cpuid	     */
-	int		irq_irq;	/* the IRQ number */
-	int		irq_int_bit;	/* Bridge interrupt pin */
-					/* <0 means MSI */
-	u64	irq_xtalkaddr;	/* xtalkaddr IRQ is sent to  */
-	int		irq_bridge_type;/* pciio asic type (pciio.h) */
-	void	       *irq_bridge;	/* bridge generating irq     */
-	void	       *irq_pciioinfo;	/* associated pciio_info_t   */
-	int		irq_last_intr;	/* For Shub lb lost intr WAR */
-	int		irq_cookie;	/* unique cookie 	     */
-	int		irq_flags;	/* flags */
-	int		irq_share_cnt;	/* num devices sharing IRQ   */
-	struct list_head	list;	/* list of sn_irq_info structs */
-	struct rcu_head		rcu;	/* rcu callback list */
-};
-
-extern void sn_send_IPI_phys(int, long, int, int);
-extern u64 sn_intr_alloc(nasid_t, int,
-			      struct sn_irq_info *,
-			      int, nasid_t, int);
-extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
-extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
-extern void sn_set_err_irq_affinity(unsigned int);
-extern struct list_head **sn_irq_lh;
-
-#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
-
 #endif /* _ASM_IA64_SN_INTR_H */
diff --git a/arch/ia64/include/asm/sn/io.h b/arch/ia64/include/asm/sn/io.h
deleted file mode 100644
index 41c73a735628..000000000000
--- a/arch/ia64/include/asm/sn/io.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_SN_IO_H
-#define _ASM_SN_IO_H
-#include <linux/compiler.h>
-#include <asm/intrinsics.h>
-
-extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
-extern void __sn_mmiowb(void); /* Forward definition */
-
-extern int num_cnodes;
-
-#define __sn_mf_a()   ia64_mfa()
-
-extern void sn_dma_flush(unsigned long);
-
-#define __sn_inb ___sn_inb
-#define __sn_inw ___sn_inw
-#define __sn_inl ___sn_inl
-#define __sn_outb ___sn_outb
-#define __sn_outw ___sn_outw
-#define __sn_outl ___sn_outl
-#define __sn_readb ___sn_readb
-#define __sn_readw ___sn_readw
-#define __sn_readl ___sn_readl
-#define __sn_readq ___sn_readq
-#define __sn_readb_relaxed ___sn_readb_relaxed
-#define __sn_readw_relaxed ___sn_readw_relaxed
-#define __sn_readl_relaxed ___sn_readl_relaxed
-#define __sn_readq_relaxed ___sn_readq_relaxed
-
-/*
- * Convenience macros for setting/clearing bits using the above accessors
- */
-
-#define __sn_setq_relaxed(addr, val) \
-	writeq((__sn_readq_relaxed(addr) | (val)), (addr))
-#define __sn_clrq_relaxed(addr, val) \
-	writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
-
-/*
- * The following routines are SN Platform specific, called when
- * a reference is made to inX/outX set macros.  SN Platform
- * inX set of macros ensures that Posted DMA writes on the
- * Bridge is flushed.
- *
- * The routines should be self explainatory.
- */
-
-static inline unsigned int
-___sn_inb (unsigned long port)
-{
-	volatile unsigned char *addr;
-	unsigned char ret = -1;
-
-	if ((addr = sn_io_addr(port))) {
-		ret = *addr;
-		__sn_mf_a();
-		sn_dma_flush((unsigned long)addr);
-	}
-	return ret;
-}
-
-static inline unsigned int
-___sn_inw (unsigned long port)
-{
-	volatile unsigned short *addr;
-	unsigned short ret = -1;
-
-	if ((addr = sn_io_addr(port))) {
-		ret = *addr;
-		__sn_mf_a();
-		sn_dma_flush((unsigned long)addr);
-	}
-	return ret;
-}
-
-static inline unsigned int
-___sn_inl (unsigned long port)
-{
-	volatile unsigned int *addr;
-	unsigned int ret = -1;
-
-	if ((addr = sn_io_addr(port))) {
-		ret = *addr;
-		__sn_mf_a();
-		sn_dma_flush((unsigned long)addr);
-	}
-	return ret;
-}
-
-static inline void
-___sn_outb (unsigned char val, unsigned long port)
-{
-	volatile unsigned char *addr;
-
-	if ((addr = sn_io_addr(port))) {
-		*addr = val;
-		__sn_mmiowb();
-	}
-}
-
-static inline void
-___sn_outw (unsigned short val, unsigned long port)
-{
-	volatile unsigned short *addr;
-
-	if ((addr = sn_io_addr(port))) {
-		*addr = val;
-		__sn_mmiowb();
-	}
-}
-
-static inline void
-___sn_outl (unsigned int val, unsigned long port)
-{
-	volatile unsigned int *addr;
-
-	if ((addr = sn_io_addr(port))) {
-		*addr = val;
-		__sn_mmiowb();
-	}
-}
-
-/*
- * The following routines are SN Platform specific, called when 
- * a reference is made to readX/writeX set macros.  SN Platform 
- * readX set of macros ensures that Posted DMA writes on the 
- * Bridge is flushed.
- * 
- * The routines should be self explainatory.
- */
-
-static inline unsigned char
-___sn_readb (const volatile void __iomem *addr)
-{
-	unsigned char val;
-
-	val = *(volatile unsigned char __force *)addr;
-	__sn_mf_a();
-	sn_dma_flush((unsigned long)addr);
-        return val;
-}
-
-static inline unsigned short
-___sn_readw (const volatile void __iomem *addr)
-{
-	unsigned short val;
-
-	val = *(volatile unsigned short __force *)addr;
-	__sn_mf_a();
-	sn_dma_flush((unsigned long)addr);
-        return val;
-}
-
-static inline unsigned int
-___sn_readl (const volatile void __iomem *addr)
-{
-	unsigned int val;
-
-	val = *(volatile unsigned int __force *)addr;
-	__sn_mf_a();
-	sn_dma_flush((unsigned long)addr);
-        return val;
-}
-
-static inline unsigned long
-___sn_readq (const volatile void __iomem *addr)
-{
-	unsigned long val;
-
-	val = *(volatile unsigned long __force *)addr;
-	__sn_mf_a();
-	sn_dma_flush((unsigned long)addr);
-        return val;
-}
-
-/*
- * For generic and SN2 kernels, we have a set of fast access
- * PIO macros.	These macros are provided on SN Platform
- * because the normal inX and readX macros perform an
- * additional task of flushing Post DMA request on the Bridge.
- *
- * These routines should be self explainatory.
- */
-
-static inline unsigned int
-sn_inb_fast (unsigned long port)
-{
-	volatile unsigned char *addr = (unsigned char *)port;
-	unsigned char ret;
-
-	ret = *addr;
-	__sn_mf_a();
-	return ret;
-}
-
-static inline unsigned int
-sn_inw_fast (unsigned long port)
-{
-	volatile unsigned short *addr = (unsigned short *)port;
-	unsigned short ret;
-
-	ret = *addr;
-	__sn_mf_a();
-	return ret;
-}
-
-static inline unsigned int
-sn_inl_fast (unsigned long port)
-{
-	volatile unsigned int *addr = (unsigned int *)port;
-	unsigned int ret;
-
-	ret = *addr;
-	__sn_mf_a();
-	return ret;
-}
-
-static inline unsigned char
-___sn_readb_relaxed (const volatile void __iomem *addr)
-{
-	return *(volatile unsigned char __force *)addr;
-}
-
-static inline unsigned short
-___sn_readw_relaxed (const volatile void __iomem *addr)
-{
-	return *(volatile unsigned short __force *)addr;
-}
-
-static inline unsigned int
-___sn_readl_relaxed (const volatile void __iomem *addr)
-{
-	return *(volatile unsigned int __force *) addr;
-}
-
-static inline unsigned long
-___sn_readq_relaxed (const volatile void __iomem *addr)
-{
-	return *(volatile unsigned long __force *) addr;
-}
-
-struct pci_dev;
-
-static inline int
-sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
-{
-
-	if (vchan > 1) {
-		return -1;
-	}
-
-	if (!(*addr >> 32))	/* Using a mask here would be cleaner */
-		return 0;	/* but this generates better code */
-
-	if (vchan == 1) {
-		/* Set Bit 57 */
-		*addr |= (1UL << 57);
-	} else {
-		/* Clear Bit 57 */
-		*addr &= ~(1UL << 57);
-	}
-
-	return 0;
-}
-
-#endif	/* _ASM_SN_IO_H */
diff --git a/arch/ia64/include/asm/sn/ioc3.h b/arch/ia64/include/asm/sn/ioc3.h
deleted file mode 100644
index d4a524951df3..000000000000
--- a/arch/ia64/include/asm/sn/ioc3.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2005 Silicon Graphics, Inc.
- */
-#ifndef IA64_SN_IOC3_H
-#define IA64_SN_IOC3_H
-
-/* serial port register map */
-struct ioc3_serialregs {
-	uint32_t sscr;
-	uint32_t stpir;
-	uint32_t stcir;
-	uint32_t srpir;
-	uint32_t srcir;
-	uint32_t srtr;
-	uint32_t shadow;
-};
-
-/* SUPERIO uart register map */
-struct ioc3_uartregs {
-	char iu_lcr;
-	union {
-		char iir;	/* read only */
-		char fcr;	/* write only */
-	} u3;
-	union {
-		char ier;	/* DLAB == 0 */
-		char dlm;	/* DLAB == 1 */
-	} u2;
-	union {
-		char rbr;	/* read only, DLAB == 0 */
-		char thr;	/* write only, DLAB == 0 */
-		char dll;	/* DLAB == 1 */
-	} u1;
-	char iu_scr;
-	char iu_msr;
-	char iu_lsr;
-	char iu_mcr;
-};
-
-#define iu_rbr u1.rbr
-#define iu_thr u1.thr
-#define iu_dll u1.dll
-#define iu_ier u2.ier
-#define iu_dlm u2.dlm
-#define iu_iir u3.iir
-#define iu_fcr u3.fcr
-
-struct ioc3_sioregs {
-	char fill[0x170];
-	struct ioc3_uartregs uartb;
-	struct ioc3_uartregs uarta;
-};
-
-/* PCI IO/mem space register map */
-struct ioc3 {
-	uint32_t pci_id;
-	uint32_t pci_scr;
-	uint32_t pci_rev;
-	uint32_t pci_lat;
-	uint32_t pci_addr;
-	uint32_t pci_err_addr_l;
-	uint32_t pci_err_addr_h;
-
-	uint32_t sio_ir;
-	/* these registers are read-only for general kernel code. To
-	 * modify them use the functions in ioc3.c
-	 */
-	uint32_t sio_ies;
-	uint32_t sio_iec;
-	uint32_t sio_cr;
-	uint32_t int_out;
-	uint32_t mcr;
-	uint32_t gpcr_s;
-	uint32_t gpcr_c;
-	uint32_t gpdr;
-	uint32_t gppr[9];
-	char fill[0x4c];
-
-	/* serial port registers */
-	uint32_t sbbr_h;
-	uint32_t sbbr_l;
-
-	struct ioc3_serialregs port_a;
-	struct ioc3_serialregs port_b;
-	char fill1[0x1ff10];
-	/* superio registers */
-	struct ioc3_sioregs sregs;
-};
-
-/* These don't exist on the ioc3 serial card... */
-#define eier	fill1[8]
-#define eisr	fill1[4]
-
-#define PCI_LAT			0xc	/* Latency Timer */
-#define PCI_SCR_DROP_MODE_EN	0x00008000 /* drop pios on parity err */
-#define UARTA_BASE		0x178
-#define UARTB_BASE		0x170
-
-
-/* bitmasks for serial RX status byte */
-#define RXSB_OVERRUN		0x01	/* char(s) lost */
-#define RXSB_PAR_ERR		0x02	/* parity error */
-#define RXSB_FRAME_ERR		0x04	/* framing error */
-#define RXSB_BREAK		0x08	/* break character */
-#define RXSB_CTS		0x10	/* state of CTS */
-#define RXSB_DCD		0x20	/* state of DCD */
-#define RXSB_MODEM_VALID	0x40	/* DCD, CTS and OVERRUN are valid */
-#define RXSB_DATA_VALID		0x80	/* FRAME_ERR PAR_ERR & BREAK valid */
-
-/* bitmasks for serial TX control byte */
-#define TXCB_INT_WHEN_DONE	0x20	/* interrupt after this byte is sent */
-#define TXCB_INVALID		0x00	/* byte is invalid */
-#define TXCB_VALID		0x40	/* byte is valid */
-#define TXCB_MCR		0x80	/* data<7:0> to modem cntrl register */
-#define TXCB_DELAY		0xc0	/* delay data<7:0> mSec */
-
-/* bitmasks for SBBR_L */
-#define SBBR_L_SIZE		0x00000001	/* 0 1KB rings, 1 4KB rings */
-
-/* bitmasks for SSCR_<A:B> */
-#define SSCR_RX_THRESHOLD	0x000001ff	/* hiwater mark */
-#define SSCR_TX_TIMER_BUSY	0x00010000	/* TX timer in progress */
-#define SSCR_HFC_EN		0x00020000	/* h/w flow cntrl enabled */
-#define SSCR_RX_RING_DCD	0x00040000	/* postRX record on delta-DCD */
-#define SSCR_RX_RING_CTS	0x00080000	/* postRX record on delta-CTS */
-#define SSCR_HIGH_SPD		0x00100000	/* 4X speed */
-#define SSCR_DIAG		0x00200000	/* bypass clock divider */
-#define SSCR_RX_DRAIN		0x08000000	/* drain RX buffer to memory */
-#define SSCR_DMA_EN		0x10000000	/* enable ring buffer DMA */
-#define SSCR_DMA_PAUSE		0x20000000	/* pause DMA */
-#define SSCR_PAUSE_STATE	0x40000000	/* set when PAUSE takes effect*/
-#define SSCR_RESET		0x80000000	/* reset DMA channels */
-
-/* all producer/consumer pointers are the same bitfield */
-#define PROD_CONS_PTR_4K	0x00000ff8	/* for 4K buffers */
-#define PROD_CONS_PTR_1K	0x000003f8	/* for 1K buffers */
-#define PROD_CONS_PTR_OFF	3
-
-/* bitmasks for SRCIR_<A:B> */
-#define SRCIR_ARM		0x80000000	/* arm RX timer */
-
-/* bitmasks for SHADOW_<A:B> */
-#define SHADOW_DR		0x00000001	/* data ready */
-#define SHADOW_OE		0x00000002	/* overrun error */
-#define SHADOW_PE		0x00000004	/* parity error */
-#define SHADOW_FE		0x00000008	/* framing error */
-#define SHADOW_BI		0x00000010	/* break interrupt */
-#define SHADOW_THRE		0x00000020	/* transmit holding reg empty */
-#define SHADOW_TEMT		0x00000040	/* transmit shift reg empty */
-#define SHADOW_RFCE		0x00000080	/* char in RX fifo has error */
-#define SHADOW_DCTS		0x00010000	/* delta clear to send */
-#define SHADOW_DDCD		0x00080000	/* delta data carrier detect */
-#define SHADOW_CTS		0x00100000	/* clear to send */
-#define SHADOW_DCD		0x00800000	/* data carrier detect */
-#define SHADOW_DTR		0x01000000	/* data terminal ready */
-#define SHADOW_RTS		0x02000000	/* request to send */
-#define SHADOW_OUT1		0x04000000	/* 16550 OUT1 bit */
-#define SHADOW_OUT2		0x08000000	/* 16550 OUT2 bit */
-#define SHADOW_LOOP		0x10000000	/* loopback enabled */
-
-/* bitmasks for SRTR_<A:B> */
-#define SRTR_CNT		0x00000fff	/* reload value for RX timer */
-#define SRTR_CNT_VAL		0x0fff0000	/* current value of RX timer */
-#define SRTR_CNT_VAL_SHIFT	16
-#define SRTR_HZ			16000		/* SRTR clock frequency */
-
-/* bitmasks for SIO_IR, SIO_IEC and SIO_IES  */
-#define SIO_IR_SA_TX_MT		0x00000001	/* Serial port A TX empty */
-#define SIO_IR_SA_RX_FULL	0x00000002	/* port A RX buf full */
-#define SIO_IR_SA_RX_HIGH	0x00000004	/* port A RX hiwat */
-#define SIO_IR_SA_RX_TIMER	0x00000008	/* port A RX timeout */
-#define SIO_IR_SA_DELTA_DCD	0x00000010	/* port A delta DCD */
-#define SIO_IR_SA_DELTA_CTS	0x00000020	/* port A delta CTS */
-#define SIO_IR_SA_INT		0x00000040	/* port A pass-thru intr */
-#define SIO_IR_SA_TX_EXPLICIT	0x00000080	/* port A explicit TX thru */
-#define SIO_IR_SA_MEMERR	0x00000100	/* port A PCI error */
-#define SIO_IR_SB_TX_MT		0x00000200
-#define SIO_IR_SB_RX_FULL	0x00000400
-#define SIO_IR_SB_RX_HIGH	0x00000800
-#define SIO_IR_SB_RX_TIMER	0x00001000
-#define SIO_IR_SB_DELTA_DCD	0x00002000
-#define SIO_IR_SB_DELTA_CTS	0x00004000
-#define SIO_IR_SB_INT		0x00008000
-#define SIO_IR_SB_TX_EXPLICIT	0x00010000
-#define SIO_IR_SB_MEMERR	0x00020000
-#define SIO_IR_PP_INT		0x00040000	/* P port pass-thru intr */
-#define SIO_IR_PP_INTA		0x00080000	/* PP context A thru */
-#define SIO_IR_PP_INTB		0x00100000	/* PP context B thru */
-#define SIO_IR_PP_MEMERR	0x00200000	/* PP PCI error */
-#define SIO_IR_KBD_INT		0x00400000	/* kbd/mouse intr */
-#define SIO_IR_RT_INT		0x08000000	/* RT output pulse */
-#define SIO_IR_GEN_INT1		0x10000000	/* RT input pulse */
-#define SIO_IR_GEN_INT_SHIFT	28
-
-/* per device interrupt masks */
-#define SIO_IR_SA		(SIO_IR_SA_TX_MT | \
-				 SIO_IR_SA_RX_FULL | \
-				 SIO_IR_SA_RX_HIGH | \
-				 SIO_IR_SA_RX_TIMER | \
-				 SIO_IR_SA_DELTA_DCD | \
-				 SIO_IR_SA_DELTA_CTS | \
-				 SIO_IR_SA_INT | \
-				 SIO_IR_SA_TX_EXPLICIT | \
-				 SIO_IR_SA_MEMERR)
-
-#define SIO_IR_SB		(SIO_IR_SB_TX_MT | \
-				 SIO_IR_SB_RX_FULL | \
-				 SIO_IR_SB_RX_HIGH | \
-				 SIO_IR_SB_RX_TIMER | \
-				 SIO_IR_SB_DELTA_DCD | \
-				 SIO_IR_SB_DELTA_CTS | \
-				 SIO_IR_SB_INT | \
-				 SIO_IR_SB_TX_EXPLICIT | \
-				 SIO_IR_SB_MEMERR)
-
-#define SIO_IR_PP		(SIO_IR_PP_INT | SIO_IR_PP_INTA | \
-				 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
-#define SIO_IR_RT		(SIO_IR_RT_INT | SIO_IR_GEN_INT1)
-
-/* bitmasks for SIO_CR */
-#define SIO_CR_CMD_PULSE_SHIFT 15
-#define SIO_CR_SER_A_BASE_SHIFT 1
-#define SIO_CR_SER_B_BASE_SHIFT 8
-#define SIO_CR_ARB_DIAG		0x00380000	/* cur !enet PCI requet (ro) */
-#define SIO_CR_ARB_DIAG_TXA	0x00000000
-#define SIO_CR_ARB_DIAG_RXA	0x00080000
-#define SIO_CR_ARB_DIAG_TXB	0x00100000
-#define SIO_CR_ARB_DIAG_RXB	0x00180000
-#define SIO_CR_ARB_DIAG_PP	0x00200000
-#define SIO_CR_ARB_DIAG_IDLE	0x00400000	/* 0 -> active request (ro) */
-
-/* defs for some of the generic I/O pins */
-#define GPCR_PHY_RESET		0x20	/* pin is output to PHY reset */
-#define GPCR_UARTB_MODESEL	0x40	/* pin is output to port B mode sel */
-#define GPCR_UARTA_MODESEL	0x80	/* pin is output to port A mode sel */
-
-#define GPPR_PHY_RESET_PIN	5	/* GIO pin controlling phy reset */
-#define GPPR_UARTB_MODESEL_PIN	6	/* GIO pin cntrling uartb modeselect */
-#define GPPR_UARTA_MODESEL_PIN	7	/* GIO pin cntrling uarta modeselect */
-
-#endif /* IA64_SN_IOC3_H */
diff --git a/arch/ia64/include/asm/sn/klconfig.h b/arch/ia64/include/asm/sn/klconfig.h
deleted file mode 100644
index bcbf209d63be..000000000000
--- a/arch/ia64/include/asm/sn/klconfig.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/klconfig.h>.
- *
- * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc.  All Rights Reserved.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_IA64_SN_KLCONFIG_H
-#define _ASM_IA64_SN_KLCONFIG_H
-
-/*
- * The KLCONFIG structures store info about the various BOARDs found
- * during Hardware Discovery. In addition, it stores info about the
- * components found on the BOARDs.
- */
-
-typedef s32 klconf_off_t;
-
-
-/* Functions/macros needed to use this structure */
-
-typedef struct kl_config_hdr {
-	char		pad[20];
-	klconf_off_t	ch_board_info;	/* the link list of boards */
-	char		pad0[88];
-} kl_config_hdr_t;
-
-
-#define NODE_OFFSET_TO_LBOARD(nasid,off)        (lboard_t*)(GLOBAL_CAC_ADDR((nasid), (off)))
-
-/*
- * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
- * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to 
- * the LOCAL/current NODE. REMOTE means it is attached to a different
- * node.(TBD - Need a way to treat ROUTER boards.)
- *
- * There are 2 different structures to represent these boards -
- * lboard - Local board, rboard - remote board. These 2 structures
- * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
- * Figure below). The first byte of the rboard or lboard structure
- * is used to find out its type - no unions are used.
- * If it is a lboard, then the config info of this board will be found
- * on the local node. (LOCAL NODE BASE + offset value gives pointer to 
- * the structure.
- * If it is a rboard, the local structure contains the node number
- * and the offset of the beginning of the LINKED LIST on the remote node.
- * The details of the hardware on a remote node can be built locally,
- * if required, by reading the LINKED LIST on the remote node and 
- * ignoring all the rboards on that node.
- *
- * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the 
- * First board info on the remote node. The remote node list is 
- * traversed as the local list, using the REMOTE BASE ADDRESS and not
- * the local base address and ignoring all rboard values.
- *
- * 
- KLCONFIG
-
- +------------+      +------------+      +------------+      +------------+
- |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
- +------------+  |   +------------+  |   +------------+  |   +------------+
- | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
- +------------+  |   +------------+  |   +------------+  |   +------------+
- | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
- +------------+      +------------+      +------------+      +------------+
-
-
- +------------+
- | board info |
- +------------+       +--------------------------------+
- | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
- +------------+       +--------------------------------+
- | compt 2    |--+
- +------------+  |    +--------------------------------+
- |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
- +------------+       +--------------------------------+
- | errinfo    |--+
- +------------+  |    +--------------------------------+
-                 +--->|r/l brd errinfo,compt err flags |
-                      +--------------------------------+
-
- *
- * Each BOARD consists of COMPONENTs and the BOARD structure has 
- * pointers (offsets) to its COMPONENT structure.
- * The COMPONENT structure has version info, size and speed info, revision,
- * error info and the NIC info. This structure can accommodate any
- * BOARD with arbitrary COMPONENT composition.
- *
- * The ERRORINFO part of each BOARD has error information
- * that describes errors about the BOARD itself. It also has flags to
- * indicate the COMPONENT(s) on the board that have errors. The error 
- * information specific to the COMPONENT is present in the respective 
- * COMPONENT structure.
- *
- * The ERRORINFO structure is also treated like a COMPONENT, ie. the 
- * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
- * structure also has a pointer to the ERRORINFO structure. This is 
- * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
- * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where 
- * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
- * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info 
- * which is present on the REMOTE NODE.(TBD)
- * REMOTE ERRINFO can be stored on any of the nearest nodes 
- * or on all the nearest nodes.(TBD)
- * Like BOARD structures, REMOTE ERRINFO structures can be built locally
- * using the rboard errinfo pointer.
- *
- * In order to get useful information from this Data organization, a set of
- * interface routines are provided (TBD). The important thing to remember while
- * manipulating the structures, is that, the NODE number information should
- * be used. If the NODE is non-zero (remote) then each offset should
- * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR. 
- * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
- * 
- * Note that these structures do not provide much info about connectivity.
- * That info will be part of HWGRAPH, which is an extension of the cfg_t
- * data structure. (ref IP27prom/cfg.h) It has to be extended to include
- * the IO part of the Network(TBD).
- *
- * The data structures below define the above concepts.
- */
-
-
-/*
- * BOARD classes
- */
-
-#define KLCLASS_MASK	0xf0   
-#define KLCLASS_NONE	0x00
-#define KLCLASS_NODE	0x10             /* CPU, Memory and HUB board */
-#define KLCLASS_CPU	KLCLASS_NODE	
-#define KLCLASS_IO	0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI 
-					    and the non-graphics widget boards */
-#define KLCLASS_ROUTER	0x30             /* Router board */
-#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
-                                            so that we can record error info */
-#define KLCLASS_IOBRICK	0x70		/* IP35 iobrick */
-#define KLCLASS_MAX	8		/* Bump this if a new CLASS is added */
-
-#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
-
-
-/*
- * board types
- */
-
-#define KLTYPE_MASK	0x0f
-#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
-
-#define KLTYPE_SNIA	(KLCLASS_CPU | 0x1)
-#define KLTYPE_TIO	(KLCLASS_CPU | 0x2)
-
-#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
-#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
-#define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
-
-#define KLTYPE_IOBRICK_XBOW	(KLCLASS_MIDPLANE | 0x2)
-
-#define KLTYPE_IOBRICK		(KLCLASS_IOBRICK | 0x0)
-#define KLTYPE_NBRICK		(KLCLASS_IOBRICK | 0x4)
-#define KLTYPE_PXBRICK		(KLCLASS_IOBRICK | 0x6)
-#define KLTYPE_IXBRICK		(KLCLASS_IOBRICK | 0x7)
-#define KLTYPE_CGBRICK		(KLCLASS_IOBRICK | 0x8)
-#define KLTYPE_OPUSBRICK	(KLCLASS_IOBRICK | 0x9)
-#define KLTYPE_SABRICK          (KLCLASS_IOBRICK | 0xa)
-#define KLTYPE_IABRICK		(KLCLASS_IOBRICK | 0xb)
-#define KLTYPE_PABRICK          (KLCLASS_IOBRICK | 0xc)
-#define KLTYPE_GABRICK		(KLCLASS_IOBRICK | 0xd)
-
-
-/* 
- * board structures
- */
-
-#define MAX_COMPTS_PER_BRD 24
-
-typedef struct lboard_s {
-	klconf_off_t 	brd_next_any;     /* Next BOARD */
-	unsigned char 	struct_type;      /* type of structure, local or remote */
-	unsigned char 	brd_type;         /* type+class */
-	unsigned char 	brd_sversion;     /* version of this structure */
-        unsigned char 	brd_brevision;    /* board revision */
-        unsigned char 	brd_promver;      /* board prom version, if any */
- 	unsigned char 	brd_flags;        /* Enabled, Disabled etc */
-	unsigned char 	brd_slot;         /* slot number */
-	unsigned short	brd_debugsw;      /* Debug switches */
-	geoid_t		brd_geoid;	  /* geo id */
-	partid_t 	brd_partition;    /* Partition number */
-        unsigned short 	brd_diagval;      /* diagnostic value */
-        unsigned short 	brd_diagparm;     /* diagnostic parameter */
-        unsigned char 	brd_inventory;    /* inventory history */
-        unsigned char 	brd_numcompts;    /* Number of components */
-        nic_t         	brd_nic;          /* Number in CAN */
-	nasid_t		brd_nasid;        /* passed parameter */
-	klconf_off_t 	brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
-	klconf_off_t 	brd_errinfo;      /* Board's error information */
-	struct lboard_s *brd_parent;	  /* Logical parent for this brd */
-	char            pad0[4];
-	unsigned char	brd_confidence;	  /* confidence that the board is bad */
-	nasid_t		brd_owner;        /* who owns this board */
-	unsigned char 	brd_nic_flags;    /* To handle 8 more NICs */
-	char		pad1[24];	  /* future expansion */
-	char		brd_name[32];
-	nasid_t		brd_next_same_host; /* host of next brd w/same nasid */
-	klconf_off_t	brd_next_same;    /* Next BOARD with same nasid */
-} lboard_t;
-
-/*
- * Generic info structure. This stores common info about a 
- * component.
- */
- 
-typedef struct klinfo_s {                  /* Generic info */
-        unsigned char   struct_type;       /* type of this structure */
-        unsigned char   struct_version;    /* version of this structure */
-        unsigned char   flags;            /* Enabled, disabled etc */
-        unsigned char   revision;         /* component revision */
-        unsigned short  diagval;          /* result of diagnostics */
-        unsigned short  diagparm;         /* diagnostic parameter */
-        unsigned char   inventory;        /* previous inventory status */
-        unsigned short  partid;		   /* widget part number */
-	nic_t 		nic;              /* MUst be aligned properly */
-        unsigned char   physid;           /* physical id of component */
-        unsigned int    virtid;           /* virtual id as seen by system */
-	unsigned char	widid;	          /* Widget id - if applicable */
-	nasid_t		nasid;            /* node number - from parent */
-	char		pad1;		  /* pad out structure. */
-	char		pad2;		  /* pad out structure. */
-	void		*data;
-        klconf_off_t	errinfo;          /* component specific errors */
-        unsigned short  pad3;             /* pci fields have moved over to */
-        unsigned short  pad4;             /* klbri_t */
-} klinfo_t ;
-
-
-static inline lboard_t *find_lboard_next(lboard_t * brd)
-{
-	if (brd && brd->brd_next_any)
-		return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
-        return NULL;
-}
-
-#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/arch/ia64/include/asm/sn/l1.h b/arch/ia64/include/asm/sn/l1.h
deleted file mode 100644
index 344bf44bb356..000000000000
--- a/arch/ia64/include/asm/sn/l1.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#ifndef _ASM_IA64_SN_L1_H
-#define _ASM_IA64_SN_L1_H
-
-/* brick type response codes */
-#define L1_BRICKTYPE_PX         0x23            /* # */
-#define L1_BRICKTYPE_PE         0x25            /* % */
-#define L1_BRICKTYPE_N_p0       0x26            /* & */
-#define L1_BRICKTYPE_IP45       0x34            /* 4 */
-#define L1_BRICKTYPE_IP41       0x35            /* 5 */
-#define L1_BRICKTYPE_TWISTER    0x36            /* 6 */ /* IP53 & ROUTER */
-#define L1_BRICKTYPE_IX         0x3d            /* = */
-#define L1_BRICKTYPE_IP34       0x61            /* a */
-#define L1_BRICKTYPE_GA		0x62            /* b */
-#define L1_BRICKTYPE_C          0x63            /* c */
-#define L1_BRICKTYPE_OPUS_TIO	0x66		/* f */
-#define L1_BRICKTYPE_I          0x69            /* i */
-#define L1_BRICKTYPE_N          0x6e            /* n */
-#define L1_BRICKTYPE_OPUS       0x6f		/* o */
-#define L1_BRICKTYPE_P          0x70            /* p */
-#define L1_BRICKTYPE_R          0x72            /* r */
-#define L1_BRICKTYPE_CHI_CG     0x76            /* v */
-#define L1_BRICKTYPE_X          0x78            /* x */
-#define L1_BRICKTYPE_X2         0x79            /* y */
-#define L1_BRICKTYPE_SA		0x5e            /* ^ */
-#define L1_BRICKTYPE_PA		0x6a            /* j */
-#define L1_BRICKTYPE_IA		0x6b            /* k */
-#define L1_BRICKTYPE_ATHENA	0x2b            /* + */
-#define L1_BRICKTYPE_DAYTONA	0x7a            /* z */
-#define L1_BRICKTYPE_1932	0x2c		/* . */
-#define L1_BRICKTYPE_191010	0x2e		/* , */
-
-/* board type response codes */
-#define L1_BOARDTYPE_IP69       0x0100          /* CA */
-#define L1_BOARDTYPE_IP63       0x0200          /* CB */
-#define L1_BOARDTYPE_BASEIO     0x0300          /* IB */
-#define L1_BOARDTYPE_PCIE2SLOT  0x0400          /* IC */
-#define L1_BOARDTYPE_PCIX3SLOT  0x0500          /* ID */
-#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600       /* IE */
-#define L1_BOARDTYPE_ABACUS     0x0700          /* AB */
-#define L1_BOARDTYPE_DAYTONA    0x0800          /* AD */
-#define L1_BOARDTYPE_INVAL      (-1)            /* invalid brick type */
-
-#endif /* _ASM_IA64_SN_L1_H */
diff --git a/arch/ia64/include/asm/sn/leds.h b/arch/ia64/include/asm/sn/leds.h
deleted file mode 100644
index 66cf8c4d92c9..000000000000
--- a/arch/ia64/include/asm/sn/leds.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_LEDS_H
-#define _ASM_IA64_SN_LEDS_H
-
-#include <asm/sn/addrs.h>
-#include <asm/sn/pda.h>
-#include <asm/sn/shub_mmr.h>
-
-#define LED0		(LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
-#define LED_CPU_SHIFT	16
-
-#define LED_CPU_HEARTBEAT	0x01
-#define LED_CPU_ACTIVITY	0x02
-#define LED_ALWAYS_SET		0x00
-
-/*
- * Basic macros for flashing the LEDS on an SGI SN.
- */
-
-static __inline__ void
-set_led_bits(u8 value, u8 mask)
-{
-	pda->led_state = (pda->led_state & ~mask) | (value & mask);
-	*pda->led_address = (short) pda->led_state;
-}
-
-#endif /* _ASM_IA64_SN_LEDS_H */
-
diff --git a/arch/ia64/include/asm/sn/module.h b/arch/ia64/include/asm/sn/module.h
deleted file mode 100644
index 734e980ece2f..000000000000
--- a/arch/ia64/include/asm/sn/module.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_MODULE_H
-#define _ASM_IA64_SN_MODULE_H
-
-/* parameter for format_module_id() */
-#define MODULE_FORMAT_BRIEF	1
-#define MODULE_FORMAT_LONG	2
-#define MODULE_FORMAT_LCD	3
-
-/*
- *	Module id format
- *
- *	31-16	Rack ID (encoded class, group, number - 16-bit unsigned int)
- *	 15-8	Brick type (8-bit ascii character)
- *	  7-0	Bay (brick position in rack (0-63) - 8-bit unsigned int)
- *
- */
-
-/*
- * Macros for getting the brick type
- */
-#define MODULE_BTYPE_MASK	0xff00
-#define MODULE_BTYPE_SHFT	8
-#define MODULE_GET_BTYPE(_m)	(((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
-#define MODULE_BT_TO_CHAR(_b)	((char)(_b))
-#define MODULE_GET_BTCHAR(_m)	(MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
-
-/*
- * Macros for getting the rack ID.
- */
-#define MODULE_RACK_MASK	0xffff0000
-#define MODULE_RACK_SHFT	16
-#define MODULE_GET_RACK(_m)	(((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
-
-/*
- * Macros for getting the brick position
- */
-#define MODULE_BPOS_MASK	0x00ff
-#define MODULE_BPOS_SHFT	0
-#define MODULE_GET_BPOS(_m)	(((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
-
-/*
- * Macros for encoding and decoding rack IDs
- * A rack number consists of three parts:
- *   class (0==CPU/mixed, 1==I/O), group, number
- *
- * Rack number is stored just as it is displayed on the screen:
- * a 3-decimal-digit number.
- */
-#define RACK_CLASS_DVDR         100
-#define RACK_GROUP_DVDR         10
-#define RACK_NUM_DVDR           1
-
-#define RACK_CREATE_RACKID(_c, _g, _n)  ((_c) * RACK_CLASS_DVDR +       \
-        (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR)
-
-#define RACK_GET_CLASS(_r)              ((_r) / RACK_CLASS_DVDR)
-#define RACK_GET_GROUP(_r)              (((_r) - RACK_GET_CLASS(_r) *   \
-            RACK_CLASS_DVDR) / RACK_GROUP_DVDR)
-#define RACK_GET_NUM(_r)                (((_r) - RACK_GET_CLASS(_r) *   \
-            RACK_CLASS_DVDR - RACK_GET_GROUP(_r) *      \
-            RACK_GROUP_DVDR) / RACK_NUM_DVDR)
-
-/*
- * Macros for encoding and decoding rack IDs
- * A rack number consists of three parts:
- *   class      1 bit, 0==CPU/mixed, 1==I/O
- *   group      2 bits for CPU/mixed, 3 bits for I/O
- *   number     3 bits for CPU/mixed, 2 bits for I/O (1 based)
- */
-#define RACK_GROUP_BITS(_r)     (RACK_GET_CLASS(_r) ? 3 : 2)
-#define RACK_NUM_BITS(_r)       (RACK_GET_CLASS(_r) ? 2 : 3)
-
-#define RACK_CLASS_MASK(_r)     0x20
-#define RACK_CLASS_SHFT(_r)     5
-#define RACK_ADD_CLASS(_r, _c)  \
-        ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
-
-#define RACK_GROUP_SHFT(_r)     RACK_NUM_BITS(_r)
-#define RACK_GROUP_MASK(_r)     \
-        ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
-#define RACK_ADD_GROUP(_r, _g)  \
-        ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
-
-#define RACK_NUM_SHFT(_r)       0
-#define RACK_NUM_MASK(_r)       \
-        ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
-#define RACK_ADD_NUM(_r, _n)    \
-        ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
-
-
-/*
- * Brick type definitions
- */
-#define MAX_BRICK_TYPES         256 /* brick type is stored as uchar */
-
-extern char brick_types[];
-
-#define MODULE_CBRICK           0
-#define MODULE_RBRICK           1
-#define MODULE_IBRICK           2
-#define MODULE_KBRICK           3
-#define MODULE_XBRICK           4
-#define MODULE_DBRICK           5
-#define MODULE_PBRICK           6
-#define MODULE_NBRICK           7
-#define MODULE_PEBRICK          8
-#define MODULE_PXBRICK          9
-#define MODULE_IXBRICK          10
-#define MODULE_CGBRICK		11
-#define MODULE_OPUSBRICK        12
-#define MODULE_SABRICK		13	/* TIO BringUp Brick */
-#define MODULE_IABRICK		14
-#define MODULE_PABRICK		15
-#define MODULE_GABRICK		16
-#define MODULE_OPUS_TIO		17	/* OPUS TIO Riser */
-
-extern char brick_types[];
-extern void format_module_id(char *, moduleid_t, int);
-
-#endif /* _ASM_IA64_SN_MODULE_H */
diff --git a/arch/ia64/include/asm/sn/mspec.h b/arch/ia64/include/asm/sn/mspec.h
deleted file mode 100644
index c1d3c50c3223..000000000000
--- a/arch/ia64/include/asm/sn/mspec.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2001-2008 Silicon Graphics, Inc.  All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_MSPEC_H
-#define _ASM_IA64_SN_MSPEC_H
-
-#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
-
-#define FETCHOP_LOAD		0
-#define FETCHOP_INCREMENT	8
-#define FETCHOP_DECREMENT	16
-#define FETCHOP_CLEAR		24
-
-#define FETCHOP_STORE		0
-#define FETCHOP_AND		24
-#define FETCHOP_OR		32
-
-#define FETCHOP_CLEAR_CACHE	56
-
-#define FETCHOP_LOAD_OP(addr, op) ( \
-         *(volatile long *)((char*) (addr) + (op)))
-
-#define FETCHOP_STORE_OP(addr, op, x) ( \
-         *(volatile long *)((char*) (addr) + (op)) = (long) (x))
-
-#ifdef __KERNEL__
-
-/*
- * Each Atomic Memory Operation (amo, formerly known as fetchop)
- * variable is 64 bytes long.  The first 8 bytes are used.  The
- * remaining 56 bytes are unaddressable due to the operation taking
- * that portion of the address.
- *
- * NOTE: The amo structure _MUST_ be placed in either the first or second
- * half of the cache line.  The cache line _MUST NOT_ be used for anything
- * other than additional amo entries.  This is because there are two
- * addresses which reference the same physical cache line.  One will
- * be a cached entry with the memory type bits all set.  This address
- * may be loaded into processor cache.  The amo will be referenced
- * uncached via the memory special memory type.  If any portion of the
- * cached cache-line is modified, when that line is flushed, it will
- * overwrite the uncached value in physical memory and lead to
- * inconsistency.
- */
-struct amo {
-        u64 variable;
-        u64 unused[7];
-};
-
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IA64_SN_MSPEC_H */
diff --git a/arch/ia64/include/asm/sn/nodepda.h b/arch/ia64/include/asm/sn/nodepda.h
deleted file mode 100644
index 7c8b4710f071..000000000000
--- a/arch/ia64/include/asm/sn/nodepda.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_NODEPDA_H
-#define _ASM_IA64_SN_NODEPDA_H
-
-
-#include <asm/irq.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/bte.h>
-
-/*
- * NUMA Node-Specific Data structures are defined in this file.
- * In particular, this is the location of the node PDA.
- * A pointer to the right node PDA is saved in each CPU PDA.
- */
-
-/*
- * Node-specific data structure.
- *
- * One of these structures is allocated on each node of a NUMA system.
- *
- * This structure provides a convenient way of keeping together 
- * all per-node data structures. 
- */
-struct phys_cpuid {
-	short			nasid;
-	char			subnode;
-	char			slice;
-};
-
-struct nodepda_s {
-	void 		*pdinfo;	/* Platform-dependent per-node info */
-
-	/*
-	 * The BTEs on this node are shared by the local cpus
-	 */
-	struct bteinfo_s	bte_if[MAX_BTES_PER_NODE];	/* Virtual Interface */
-	struct timer_list	bte_recovery_timer;
-	spinlock_t		bte_recovery_lock;
-
-	/* 
-	 * Array of pointers to the nodepdas for each node.
-	 */
-	struct nodepda_s	*pernode_pdaindr[MAX_COMPACT_NODES]; 
-
-	/*
-	 * Array of physical cpu identifiers. Indexed by cpuid.
-	 */
-	struct phys_cpuid	phys_cpuid[NR_CPUS];
-	spinlock_t		ptc_lock ____cacheline_aligned_in_smp;
-};
-
-typedef struct nodepda_s nodepda_t;
-
-/*
- * Access Functions for node PDA.
- * Since there is one nodepda for each node, we need a convenient mechanism
- * to access these nodepdas without cluttering code with #ifdefs.
- * The next set of definitions provides this.
- * Routines are expected to use 
- *
- *	sn_nodepda   - to access node PDA for the node on which code is running
- *	NODEPDA(cnodeid)   - to access node PDA for cnodeid
- */
-
-DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
-#define sn_nodepda		__this_cpu_read(__sn_nodepda)
-#define	NODEPDA(cnodeid)	(sn_nodepda->pernode_pdaindr[cnodeid])
-
-/*
- * Check if given a compact node id the corresponding node has all the
- * cpus disabled. 
- */
-#define is_headless_node(cnodeid)	(nr_cpus_node(cnodeid) == 0)
-
-#endif /* _ASM_IA64_SN_NODEPDA_H */
diff --git a/arch/ia64/include/asm/sn/pcibr_provider.h b/arch/ia64/include/asm/sn/pcibr_provider.h
deleted file mode 100644
index da205b7cdaac..000000000000
--- a/arch/ia64/include/asm/sn/pcibr_provider.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
-#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
-
-#include <asm/sn/intr.h>
-#include <asm/sn/pcibus_provider_defs.h>
-
-/* Workarounds */
-#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
-
-#define BUSTYPE_MASK                    0x1
-
-/* Macros given a pcibus structure */
-#define IS_PCIX(ps)     ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
-#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
-                asic == PCIIO_ASIC_TYPE_TIOCP)
-#define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
-#define IS_TIOCP_SOFT(ps)   (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
-
-
-/*
- * The different PCI Bridge types supported on the SGI Altix platforms
- */
-#define PCIBR_BRIDGETYPE_UNKNOWN       -1
-#define PCIBR_BRIDGETYPE_PIC            2
-#define PCIBR_BRIDGETYPE_TIOCP          3
-
-/*
- * Bridge 64bit Direct Map Attributes
- */
-#define PCI64_ATTR_PREF                 (1ull << 59)
-#define PCI64_ATTR_PREC                 (1ull << 58)
-#define PCI64_ATTR_VIRTUAL              (1ull << 57)
-#define PCI64_ATTR_BAR                  (1ull << 56)
-#define PCI64_ATTR_SWAP                 (1ull << 55)
-#define PCI64_ATTR_VIRTUAL1             (1ull << 54)
-
-#define PCI32_LOCAL_BASE                0
-#define PCI32_MAPPED_BASE               0x40000000
-#define PCI32_DIRECT_BASE               0x80000000
-
-#define IS_PCI32_MAPPED(x)              ((u64)(x) < PCI32_DIRECT_BASE && \
-                                         (u64)(x) >= PCI32_MAPPED_BASE)
-#define IS_PCI32_DIRECT(x)              ((u64)(x) >= PCI32_MAPPED_BASE)
-
-
-/*
- * Bridge PMU Address Transaltion Entry Attibutes
- */
-#define PCI32_ATE_V                     (0x1 << 0)
-#define PCI32_ATE_CO                    (0x1 << 1)	/* PIC ASIC ONLY */
-#define PCI32_ATE_PIO                   (0x1 << 1)	/* TIOCP ASIC ONLY */
-#define PCI32_ATE_MSI                   (0x1 << 2)
-#define PCI32_ATE_PREF                  (0x1 << 3)
-#define PCI32_ATE_BAR                   (0x1 << 4)
-#define PCI32_ATE_ADDR_SHFT             12
-
-#define MINIMAL_ATES_REQUIRED(addr, size) \
-	(IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
-
-#define MINIMAL_ATE_FLAG(addr, size) \
-	(MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
-
-/* bit 29 of the pci address is the SWAP bit */
-#define ATE_SWAPSHIFT                   29
-#define ATE_SWAP_ON(x)                  ((x) |= (1 << ATE_SWAPSHIFT))
-#define ATE_SWAP_OFF(x)                 ((x) &= ~(1 << ATE_SWAPSHIFT))
-
-/*
- * I/O page size
- */
-#if PAGE_SIZE < 16384
-#define IOPFNSHIFT                      12      /* 4K per mapped page */
-#else
-#define IOPFNSHIFT                      14      /* 16K per mapped page */
-#endif
-
-#define IOPGSIZE                        (1 << IOPFNSHIFT)
-#define IOPG(x)                         ((x) >> IOPFNSHIFT)
-#define IOPGOFF(x)                      ((x) & (IOPGSIZE-1))
-
-#define PCIBR_DEV_SWAP_DIR              (1ull << 19)
-#define PCIBR_CTRL_PAGE_SIZE            (0x1 << 21)
-
-/*
- * PMU resources.
- */
-struct ate_resource{
-	u64 *ate;
-	u64 num_ate;
-	u64 lowest_free_index;
-};
-
-struct pcibus_info {
-	struct pcibus_bussoft	pbi_buscommon;   /* common header */
-	u32                pbi_moduleid;
-	short                   pbi_bridge_type;
-	short                   pbi_bridge_mode;
-
-	struct ate_resource     pbi_int_ate_resource;
-	u64                pbi_int_ate_size;
-
-	u64                pbi_dir_xbase;
-	char                    pbi_hub_xid;
-
-	u64                pbi_devreg[8];
-
-	u32		pbi_valid_devices;
-	u32		pbi_enabled_devices;
-
-	spinlock_t              pbi_lock;
-};
-
-extern int  pcibr_init_provider(void);
-extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
-extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
-extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
-extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
-
-/*
- * prototypes for the bridge asic register access routines in pcibr_reg.c
- */
-extern void             pcireg_control_bit_clr(struct pcibus_info *, u64);
-extern void             pcireg_control_bit_set(struct pcibus_info *, u64);
-extern u64         pcireg_tflush_get(struct pcibus_info *);
-extern u64         pcireg_intr_status_get(struct pcibus_info *);
-extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
-extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
-extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
-extern void             pcireg_force_intr_set(struct pcibus_info *, int);
-extern u64         pcireg_wrb_flush_get(struct pcibus_info *, int);
-extern void             pcireg_int_ate_set(struct pcibus_info *, int, u64);
-extern u64 __iomem *	pcireg_int_ate_addr(struct pcibus_info *, int);
-extern void 		pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
-extern void 		pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
-extern int 		pcibr_ate_alloc(struct pcibus_info *, int);
-extern void 		pcibr_ate_free(struct pcibus_info *, int);
-extern void 		ate_write(struct pcibus_info *, int, int, u64);
-extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
-				 void *resp, char **ssdt);
-extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
-				  int action, void *resp);
-extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
-#endif
diff --git a/arch/ia64/include/asm/sn/pcibus_provider_defs.h b/arch/ia64/include/asm/sn/pcibus_provider_defs.h
deleted file mode 100644
index 8f7c83d0f6d3..000000000000
--- a/arch/ia64/include/asm/sn/pcibus_provider_defs.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
-#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
-
-/*
- * SN pci asic types.  Do not ever renumber these or reuse values.  The
- * values must agree with what prom thinks they are.
- */
-
-#define PCIIO_ASIC_TYPE_UNKNOWN	0
-#define PCIIO_ASIC_TYPE_PPB	1
-#define PCIIO_ASIC_TYPE_PIC	2
-#define PCIIO_ASIC_TYPE_TIOCP	3
-#define PCIIO_ASIC_TYPE_TIOCA	4
-#define PCIIO_ASIC_TYPE_TIOCE	5
-
-#define PCIIO_ASIC_MAX_TYPES	6
-
-/*
- * Common pciio bus provider data.  There should be one of these as the
- * first field in any pciio based provider soft structure (e.g. pcibr_soft
- * tioca_soft, etc).
- */
-
-struct pcibus_bussoft {
-	u32		bs_asic_type;	/* chipset type */
-	u32		bs_xid;		/* xwidget id */
-	u32		bs_persist_busnum; /* Persistent Bus Number */
-	u32		bs_persist_segment; /* Segment Number */
-	u64		bs_legacy_io;	/* legacy io pio addr */
-	u64		bs_legacy_mem;	/* legacy mem pio addr */
-	u64		bs_base;	/* widget base */
-	struct xwidget_info	*bs_xwidget_info;
-};
-
-struct pci_controller;
-/*
- * SN pci bus indirection
- */
-
-struct sn_pcibus_provider {
-	dma_addr_t	(*dma_map)(struct pci_dev *, unsigned long, size_t, int flags);
-	dma_addr_t	(*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags);
-	void		(*dma_unmap)(struct pci_dev *, dma_addr_t, int);
-	void *		(*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
- 	void		(*force_interrupt)(struct sn_irq_info *);
- 	void		(*target_interrupt)(struct sn_irq_info *);
-};
-
-/*
- * Flags used by the map interfaces
- * bits 3:0 specifies format of passed in address
- * bit  4   specifies that address is to be used for MSI
- */
-
-#define SN_DMA_ADDRTYPE(x)	((x) & 0xf)
-#define     SN_DMA_ADDR_PHYS	1	/* address is an xio address. */
-#define     SN_DMA_ADDR_XIO	2	/* address is phys memory */
-#define SN_DMA_MSI		0x10	/* Bus address is to be used for MSI */
-
-extern struct sn_pcibus_provider *sn_pci_provider[];
-#endif				/* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/pcidev.h b/arch/ia64/include/asm/sn/pcidev.h
deleted file mode 100644
index 1c2382cea807..000000000000
--- a/arch/ia64/include/asm/sn/pcidev.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
-#define _ASM_IA64_SN_PCI_PCIDEV_H
-
-#include <linux/pci.h>
-
-/*
- * In ia64, pci_dev->sysdata must be a *pci_controller. To provide access to
- * the pcidev_info structs for all devices under a controller, we keep a
- * list of pcidev_info under pci_controller->platform_data.
- */
-struct sn_platform_data {
-	void *provider_soft;
-	struct list_head pcidev_info;
-};
-
-#define SN_PLATFORM_DATA(busdev) \
-	((struct sn_platform_data *)(PCI_CONTROLLER(busdev)->platform_data))
-
-#define SN_PCIDEV_INFO(dev)	sn_pcidev_info_get(dev)
-
-/*
- * Given a pci_bus, return the sn pcibus_bussoft struct.  Note that
- * this only works for root busses, not for busses represented by PPB's.
- */
-
-#define SN_PCIBUS_BUSSOFT(pci_bus) \
-	((struct pcibus_bussoft *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
-
-#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
-	((struct pcibus_info *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
-/*
- * Given a struct pci_dev, return the sn pcibus_bussoft struct.  Note
- * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
- * due to possible PPB's in the path.
- */
-
-#define SN_PCIDEV_BUSSOFT(pci_dev) \
-	(SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
-
-#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
-	(SN_PCIDEV_INFO(pci_dev)->pdi_provider)
-
-#define PCIIO_BUS_NONE	255      /* bus 255 reserved */
-#define PCIIO_SLOT_NONE 255
-#define PCIIO_FUNC_NONE 255
-#define PCIIO_VENDOR_ID_NONE	(-1)
-
-struct pcidev_info {
-	u64		pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
-	u64		pdi_slot_host_handle;	/* Bus and devfn Host pci_dev */
-
-	struct pcibus_bussoft	*pdi_pcibus_info;	/* Kernel common bus soft */
-	struct pcidev_info	*pdi_host_pcidev_info;	/* Kernel Host pci_dev */
-	struct pci_dev		*pdi_linux_pcidev;	/* Kernel pci_dev */
-
-	struct sn_irq_info	*pdi_sn_irq_info;
-	struct sn_pcibus_provider *pdi_provider;	/* sn pci ops */
-	struct pci_dev 		*host_pci_dev;		/* host bus link */
-	struct list_head	pdi_list;		/* List of pcidev_info */
-};
-
-extern void sn_irq_fixup(struct pci_dev *pci_dev,
-			 struct sn_irq_info *sn_irq_info);
-extern void sn_irq_unfixup(struct pci_dev *pci_dev);
-extern struct pcidev_info * sn_pcidev_info_get(struct pci_dev *);
-extern void sn_bus_fixup(struct pci_bus *);
-extern void sn_acpi_bus_fixup(struct pci_bus *);
-extern void sn_common_bus_fixup(struct pci_bus *, struct pcibus_bussoft *);
-extern void sn_bus_store_sysdata(struct pci_dev *dev);
-extern void sn_bus_free_sysdata(void);
-extern void sn_generate_path(struct pci_bus *pci_bus, char *address);
-extern void sn_io_slot_fixup(struct pci_dev *);
-extern void sn_acpi_slot_fixup(struct pci_dev *);
-extern void sn_pci_fixup_slot(struct pci_dev *dev, struct pcidev_info *,
-			      struct sn_irq_info *);
-extern void sn_pci_unfixup_slot(struct pci_dev *dev);
-extern void sn_irq_lh_init(void);
-#endif				/* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/arch/ia64/include/asm/sn/pda.h b/arch/ia64/include/asm/sn/pda.h
deleted file mode 100644
index 22ae358c8d16..000000000000
--- a/arch/ia64/include/asm/sn/pda.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_PDA_H
-#define _ASM_IA64_SN_PDA_H
-
-#include <linux/cache.h>
-#include <asm/percpu.h>
-
-
-/*
- * CPU-specific data structure.
- *
- * One of these structures is allocated for each cpu of a NUMA system.
- *
- * This structure provides a convenient way of keeping together 
- * all SN per-cpu data structures. 
- */
-
-typedef struct pda_s {
-
-	/*
-	 * Support for SN LEDs
-	 */
-	volatile short	*led_address;
-	u8		led_state;
-	u8		hb_state;	/* supports blinking heartbeat leds */
-	unsigned int	hb_count;
-
-	unsigned int	idle_flag;
-	
-	volatile unsigned long *bedrock_rev_id;
-	volatile unsigned long *pio_write_status_addr;
-	unsigned long pio_write_status_val;
-	volatile unsigned long *pio_shub_war_cam_addr;
-
-	unsigned long	sn_in_service_ivecs[4];
-	int		sn_lb_int_war_ticks;
-	int		sn_last_irq;
-	int		sn_first_irq;
-} pda_t;
-
-
-#define CACHE_ALIGN(x)	(((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
-
-/*
- * PDA
- * Per-cpu private data area for each cpu. The PDA is located immediately after
- * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
- * cpu but only a small amout of the page is actually used. We put the SNIA PDA
- * in the same page as the cpu_data area. Note that there is a check in the setup
- * code to verify that we don't overflow the page.
- *
- * Seems like we should should cache-line align the pda so that any changes in the
- * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
- * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
- */
-DECLARE_PER_CPU(struct pda_s, pda_percpu);
-
-#define pda		(&__ia64_per_cpu_var(pda_percpu))
-
-#define pdacpu(cpu)	(&per_cpu(pda_percpu, cpu))
-
-#endif /* _ASM_IA64_SN_PDA_H */
diff --git a/arch/ia64/include/asm/sn/pic.h b/arch/ia64/include/asm/sn/pic.h
deleted file mode 100644
index 5f9da5fd6e56..000000000000
--- a/arch/ia64/include/asm/sn/pic.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_PCI_PIC_H
-#define _ASM_IA64_SN_PCI_PIC_H
-
-/*
- * PIC AS DEVICE ZERO
- * ------------------
- *
- * PIC handles PCI/X busses.  PCI/X requires that the 'bridge' (i.e. PIC)
- * be designated as 'device 0'.   That is a departure from earlier SGI
- * PCI bridges.  Because of that we use config space 1 to access the
- * config space of the first actual PCI device on the bus.
- * Here's what the PIC manual says:
- *
- *     The current PCI-X bus specification now defines that the parent
- *     hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
- *     reduced the total number of devices from 8 to 4 and removed the
- *     device registers and windows, now only supporting devices 0,1,2, and
- *     3. PIC did leave all 8 configuration space windows. The reason was
- *     there was nothing to gain by removing them. Here in lies the problem.
- *     The device numbering we do using 0 through 3 is unrelated to the device
- *     numbering which PCI-X requires in configuration space. In the past we
- *     correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
- *     PCI-X requires we start a 1, not 0 and currently the PX brick
- *     does associate our:
- *
- *         device 0 with configuration space window 1,
- *         device 1 with configuration space window 2,
- *         device 2 with configuration space window 3,
- *         device 3 with configuration space window 4.
- *
- * The net effect is that all config space access are off-by-one with
- * relation to other per-slot accesses on the PIC.
- * Here is a table that shows some of that:
- *
- *                               Internal Slot#
- *           |
- *           |     0         1        2         3
- * ----------|---------------------------------------
- * config    |  0x21000   0x22000  0x23000   0x24000
- *           |
- * even rrb  |  0[0]      n/a      1[0]      n/a	[] == implied even/odd
- *           |
- * odd rrb   |  n/a       0[1]     n/a       1[1]
- *           |
- * int dev   |  00       01        10        11
- *           |
- * ext slot# |  1        2         3         4
- * ----------|---------------------------------------
- */
-
-#define PIC_ATE_TARGETID_SHFT           8
-#define PIC_HOST_INTR_ADDR              0x0000FFFFFFFFFFFFUL
-#define PIC_PCI64_ATTR_TARG_SHFT        60
-
-
-/*****************************************************************************
- *********************** PIC MMR structure mapping ***************************
- *****************************************************************************/
-
-/* NOTE: PIC WAR. PV#854697.  PIC does not allow writes just to [31:0]
- * of a 64-bit register.  When writing PIC registers, always write the
- * entire 64 bits.
- */
-
-struct pic {
-
-    /* 0x000000-0x00FFFF -- Local Registers */
-
-    /* 0x000000-0x000057 -- Standard Widget Configuration */
-    u64		p_wid_id;			/* 0x000000 */
-    u64		p_wid_stat;			/* 0x000008 */
-    u64		p_wid_err_upper;		/* 0x000010 */
-    u64		p_wid_err_lower;		/* 0x000018 */
-    #define p_wid_err p_wid_err_lower
-    u64		p_wid_control;			/* 0x000020 */
-    u64		p_wid_req_timeout;		/* 0x000028 */
-    u64		p_wid_int_upper;		/* 0x000030 */
-    u64		p_wid_int_lower;		/* 0x000038 */
-    #define p_wid_int p_wid_int_lower
-    u64		p_wid_err_cmdword;		/* 0x000040 */
-    u64		p_wid_llp;			/* 0x000048 */
-    u64		p_wid_tflush;			/* 0x000050 */
-
-    /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
-    u64		p_wid_aux_err;			/* 0x000058 */
-    u64		p_wid_resp_upper;		/* 0x000060 */
-    u64		p_wid_resp_lower;		/* 0x000068 */
-    #define p_wid_resp p_wid_resp_lower
-    u64		p_wid_tst_pin_ctrl;		/* 0x000070 */
-    u64		p_wid_addr_lkerr;		/* 0x000078 */
-
-    /* 0x000080-0x00008F -- PMU & MAP */
-    u64		p_dir_map;			/* 0x000080 */
-    u64		_pad_000088;			/* 0x000088 */
-
-    /* 0x000090-0x00009F -- SSRAM */
-    u64		p_map_fault;			/* 0x000090 */
-    u64		_pad_000098;			/* 0x000098 */
-
-    /* 0x0000A0-0x0000AF -- Arbitration */
-    u64		p_arb;				/* 0x0000A0 */
-    u64		_pad_0000A8;			/* 0x0000A8 */
-
-    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
-    u64		p_ate_parity_err;		/* 0x0000B0 */
-    u64		_pad_0000B8;			/* 0x0000B8 */
-
-    /* 0x0000C0-0x0000FF -- PCI/GIO */
-    u64		p_bus_timeout;			/* 0x0000C0 */
-    u64		p_pci_cfg;			/* 0x0000C8 */
-    u64		p_pci_err_upper;		/* 0x0000D0 */
-    u64		p_pci_err_lower;		/* 0x0000D8 */
-    #define p_pci_err p_pci_err_lower
-    u64		_pad_0000E0[4];			/* 0x0000{E0..F8} */
-
-    /* 0x000100-0x0001FF -- Interrupt */
-    u64		p_int_status;			/* 0x000100 */
-    u64		p_int_enable;			/* 0x000108 */
-    u64		p_int_rst_stat;			/* 0x000110 */
-    u64		p_int_mode;			/* 0x000118 */
-    u64		p_int_device;			/* 0x000120 */
-    u64		p_int_host_err;			/* 0x000128 */
-    u64		p_int_addr[8];			/* 0x0001{30,,,68} */
-    u64		p_err_int_view;			/* 0x000170 */
-    u64		p_mult_int;			/* 0x000178 */
-    u64		p_force_always[8];		/* 0x0001{80,,,B8} */
-    u64		p_force_pin[8];			/* 0x0001{C0,,,F8} */
-
-    /* 0x000200-0x000298 -- Device */
-    u64		p_device[4];			/* 0x0002{00,,,18} */
-    u64		_pad_000220[4];			/* 0x0002{20,,,38} */
-    u64		p_wr_req_buf[4];		/* 0x0002{40,,,58} */
-    u64		_pad_000260[4];			/* 0x0002{60,,,78} */
-    u64		p_rrb_map[2];			/* 0x0002{80,,,88} */
-    #define p_even_resp p_rrb_map[0]			/* 0x000280 */
-    #define p_odd_resp  p_rrb_map[1]			/* 0x000288 */
-    u64		p_resp_status;			/* 0x000290 */
-    u64		p_resp_clear;			/* 0x000298 */
-
-    u64		_pad_0002A0[12];		/* 0x0002{A0..F8} */
-
-    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
-    struct {
-	u64	upper;				/* 0x0003{00,,,F0} */
-	u64	lower;				/* 0x0003{08,,,F8} */
-    } p_buf_addr_match[16];
-
-    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
-    struct {
-	u64	flush_w_touch;			/* 0x000{400,,,5C0} */
-	u64	flush_wo_touch;			/* 0x000{408,,,5C8} */
-	u64	inflight;			/* 0x000{410,,,5D0} */
-	u64	prefetch;			/* 0x000{418,,,5D8} */
-	u64	total_pci_retry;		/* 0x000{420,,,5E0} */
-	u64	max_pci_retry;			/* 0x000{428,,,5E8} */
-	u64	max_latency;			/* 0x000{430,,,5F0} */
-	u64	clear_all;			/* 0x000{438,,,5F8} */
-    } p_buf_count[8];
-
-
-    /* 0x000600-0x0009FF -- PCI/X registers */
-    u64		p_pcix_bus_err_addr;		/* 0x000600 */
-    u64		p_pcix_bus_err_attr;		/* 0x000608 */
-    u64		p_pcix_bus_err_data;		/* 0x000610 */
-    u64		p_pcix_pio_split_addr;		/* 0x000618 */
-    u64		p_pcix_pio_split_attr;		/* 0x000620 */
-    u64		p_pcix_dma_req_err_attr;	/* 0x000628 */
-    u64		p_pcix_dma_req_err_addr;	/* 0x000630 */
-    u64		p_pcix_timeout;			/* 0x000638 */
-
-    u64		_pad_000640[120];		/* 0x000{640,,,9F8} */
-
-    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
-    struct {
-	u64	p_buf_addr;			/* 0x000{A00,,,AF0} */
-	u64	p_buf_attr;			/* 0X000{A08,,,AF8} */
-    } p_pcix_read_buf_64[16];
-
-    struct {
-	u64	p_buf_addr;			/* 0x000{B00,,,BE0} */
-	u64	p_buf_attr;			/* 0x000{B08,,,BE8} */
-	u64	p_buf_valid;			/* 0x000{B10,,,BF0} */
-	u64	__pad1;				/* 0x000{B18,,,BF8} */
-    } p_pcix_write_buf_64[8];
-
-    /* End of Local Registers -- Start of Address Map space */
-
-    char		_pad_000c00[0x010000 - 0x000c00];
-
-    /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
-    u64		p_int_ate_ram[1024];		/* 0x010000-0x011fff */
-
-    /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
-    u64		p_int_ate_ram_mp[1024];		/* 0x012000-0x013fff */
-
-    char		_pad_014000[0x18000 - 0x014000];
-
-    /* 0x18000-0x197F8 -- PIC Write Request Ram */
-    u64		p_wr_req_lower[256];		/* 0x18000 - 0x187F8 */
-    u64		p_wr_req_upper[256];		/* 0x18800 - 0x18FF8 */
-    u64		p_wr_req_parity[256];		/* 0x19000 - 0x197F8 */
-
-    char		_pad_019800[0x20000 - 0x019800];
-
-    /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
-    union {
-	u8		c[0x1000 / 1];			/* 0x02{0000,,,7FFF} */
-	u16	s[0x1000 / 2];			/* 0x02{0000,,,7FFF} */
-	u32	l[0x1000 / 4];			/* 0x02{0000,,,7FFF} */
-	u64	d[0x1000 / 8];			/* 0x02{0000,,,7FFF} */
-	union {
-	    u8	c[0x100 / 1];
-	    u16	s[0x100 / 2];
-	    u32	l[0x100 / 4];
-	    u64	d[0x100 / 8];
-	} f[8];
-    } p_type0_cfg_dev[8];				/* 0x02{0000,,,7FFF} */
-
-    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
-    union {
-	u8		c[0x1000 / 1];			/* 0x028000-0x029000 */
-	u16	s[0x1000 / 2];			/* 0x028000-0x029000 */
-	u32	l[0x1000 / 4];			/* 0x028000-0x029000 */
-	u64	d[0x1000 / 8];			/* 0x028000-0x029000 */
-	union {
-	    u8	c[0x100 / 1];
-	    u16	s[0x100 / 2];
-	    u32	l[0x100 / 4];
-	    u64	d[0x100 / 8];
-	} f[8];
-    } p_type1_cfg;					/* 0x028000-0x029000 */
-
-    char		_pad_029000[0x030000-0x029000];
-
-    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
-    union {
-	u8		c[8 / 1];
-	u16	s[8 / 2];
-	u32	l[8 / 4];
-	u64	d[8 / 8];
-    } p_pci_iack;					/* 0x030000-0x030007 */
-
-    char		_pad_030007[0x040000-0x030008];
-
-    /* 0x040000-0x030007 -- PCIX Special Cycle */
-    union {
-	u8		c[8 / 1];
-	u16	s[8 / 2];
-	u32	l[8 / 4];
-	u64	d[8 / 8];
-    } p_pcix_cycle;					/* 0x040000-0x040007 */
-};
-
-#endif                          /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/arch/ia64/include/asm/sn/rw_mmr.h b/arch/ia64/include/asm/sn/rw_mmr.h
deleted file mode 100644
index 2d78f4c5a45e..000000000000
--- a/arch/ia64/include/asm/sn/rw_mmr.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002-2006 Silicon Graphics, Inc.  All Rights Reserved.
- */
-#ifndef _ASM_IA64_SN_RW_MMR_H
-#define _ASM_IA64_SN_RW_MMR_H
-
-
-/*
- * This file that access MMRs via uncached physical addresses.
- * 	pio_phys_read_mmr  - read an MMR
- * 	pio_phys_write_mmr - write an MMR
- * 	pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
- *		Second MMR will be skipped if address is NULL
- *
- * Addresses passed to these routines should be uncached physical addresses
- * ie., 0x80000....
- */
-
-
-extern long pio_phys_read_mmr(volatile long *mmr); 
-extern void pio_phys_write_mmr(volatile long *mmr, long val);
-extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2); 
-
-#endif /* _ASM_IA64_SN_RW_MMR_H */
diff --git a/arch/ia64/include/asm/sn/shub_mmr.h b/arch/ia64/include/asm/sn/shub_mmr.h
deleted file mode 100644
index a84d870f4294..000000000000
--- a/arch/ia64/include/asm/sn/shub_mmr.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2001-2005 Silicon Graphics, Inc.  All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_SHUB_MMR_H
-#define _ASM_IA64_SN_SHUB_MMR_H
-
-/* ==================================================================== */
-/*                        Register "SH_IPI_INT"                         */
-/*               SHub Inter-Processor Interrupt Registers               */
-/* ==================================================================== */
-#define SH1_IPI_INT			__IA64_UL_CONST(0x0000000110000380)
-#define SH2_IPI_INT			__IA64_UL_CONST(0x0000000010000380)
-
-/*   SH_IPI_INT_TYPE                                                    */
-/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
-#define SH_IPI_INT_TYPE_SHFT				0
-#define SH_IPI_INT_TYPE_MASK		__IA64_UL_CONST(0x0000000000000007)
-
-/*   SH_IPI_INT_AGT                                                     */
-/*   Description:  Agent, must be 0 for SHub                            */
-#define SH_IPI_INT_AGT_SHFT				3
-#define SH_IPI_INT_AGT_MASK		__IA64_UL_CONST(0x0000000000000008)
-
-/*   SH_IPI_INT_PID                                                     */
-/*   Description:  Processor ID, same setting as on targeted McKinley  */
-#define SH_IPI_INT_PID_SHFT                      	4
-#define SH_IPI_INT_PID_MASK		__IA64_UL_CONST(0x00000000000ffff0)
-
-/*   SH_IPI_INT_BASE                                                    */
-/*   Description:  Optional interrupt vector area, 2MB aligned          */
-#define SH_IPI_INT_BASE_SHFT				21
-#define SH_IPI_INT_BASE_MASK 		__IA64_UL_CONST(0x0003ffffffe00000)
-
-/*   SH_IPI_INT_IDX                                                     */
-/*   Description:  Targeted McKinley interrupt vector                   */
-#define SH_IPI_INT_IDX_SHFT				52
-#define SH_IPI_INT_IDX_MASK		__IA64_UL_CONST(0x0ff0000000000000)
-
-/*   SH_IPI_INT_SEND                                                    */
-/*   Description:  Send Interrupt Message to PI, This generates a puls  */
-#define SH_IPI_INT_SEND_SHFT				63
-#define SH_IPI_INT_SEND_MASK		__IA64_UL_CONST(0x8000000000000000)
-
-/* ==================================================================== */
-/*                     Register "SH_EVENT_OCCURRED"                     */
-/*                    SHub Interrupt Event Occurred                     */
-/* ==================================================================== */
-#define SH1_EVENT_OCCURRED		__IA64_UL_CONST(0x0000000110010000)
-#define SH1_EVENT_OCCURRED_ALIAS	__IA64_UL_CONST(0x0000000110010008)
-#define SH2_EVENT_OCCURRED		__IA64_UL_CONST(0x0000000010010000)
-#define SH2_EVENT_OCCURRED_ALIAS 	__IA64_UL_CONST(0x0000000010010008)
-
-/* ==================================================================== */
-/*                     Register "SH_PI_CAM_CONTROL"                     */
-/*                      CRB CAM MMR Access Control                      */
-/* ==================================================================== */
-#define SH1_PI_CAM_CONTROL		__IA64_UL_CONST(0x0000000120050300)
-
-/* ==================================================================== */
-/*                        Register "SH_SHUB_ID"                         */
-/*                            SHub ID Number                            */
-/* ==================================================================== */
-#define SH1_SHUB_ID			__IA64_UL_CONST(0x0000000110060580)
-#define SH1_SHUB_ID_REVISION_SHFT			28
-#define SH1_SHUB_ID_REVISION_MASK	__IA64_UL_CONST(0x00000000f0000000)
-
-/* ==================================================================== */
-/*                          Register "SH_RTC"                           */
-/*                           Real-time Clock                            */
-/* ==================================================================== */
-#define SH1_RTC				__IA64_UL_CONST(0x00000001101c0000)
-#define SH2_RTC				__IA64_UL_CONST(0x00000002101c0000)
-#define SH_RTC_MASK			__IA64_UL_CONST(0x007fffffffffffff)
-
-/* ==================================================================== */
-/*                   Register "SH_PIO_WRITE_STATUS_0|1"                 */
-/*                      PIO Write Status for CPU 0 & 1                  */
-/* ==================================================================== */
-#define SH1_PIO_WRITE_STATUS_0		__IA64_UL_CONST(0x0000000120070200)
-#define SH1_PIO_WRITE_STATUS_1		__IA64_UL_CONST(0x0000000120070280)
-#define SH2_PIO_WRITE_STATUS_0		__IA64_UL_CONST(0x0000000020070200)
-#define SH2_PIO_WRITE_STATUS_1		__IA64_UL_CONST(0x0000000020070280)
-#define SH2_PIO_WRITE_STATUS_2		__IA64_UL_CONST(0x0000000020070300)
-#define SH2_PIO_WRITE_STATUS_3		__IA64_UL_CONST(0x0000000020070380)
-
-/*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
-/*   Description:  Deadlock response detected                           */
-#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT		1
-#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
-					__IA64_UL_CONST(0x0000000000000002)
-
-/*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
-/*   Description:  Count of currently pending PIO writes                */
-#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT	56
-#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
-					__IA64_UL_CONST(0x3f00000000000000)
-
-/* ==================================================================== */
-/*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
-/* ==================================================================== */
-#define SH1_PIO_WRITE_STATUS_0_ALIAS	__IA64_UL_CONST(0x0000000120070208)
-#define SH2_PIO_WRITE_STATUS_0_ALIAS	__IA64_UL_CONST(0x0000000020070208)
-
-/* ==================================================================== */
-/*                     Register "SH_EVENT_OCCURRED"                     */
-/*                    SHub Interrupt Event Occurred                     */
-/* ==================================================================== */
-/*   SH_EVENT_OCCURRED_UART_INT                                         */
-/*   Description:  Pending Junk Bus UART Interrupt                      */
-#define SH_EVENT_OCCURRED_UART_INT_SHFT			20
-#define SH_EVENT_OCCURRED_UART_INT_MASK	__IA64_UL_CONST(0x0000000000100000)
-
-/*   SH_EVENT_OCCURRED_IPI_INT                                          */
-/*   Description:  Pending IPI Interrupt                                */
-#define SH_EVENT_OCCURRED_IPI_INT_SHFT			28
-#define SH_EVENT_OCCURRED_IPI_INT_MASK	__IA64_UL_CONST(0x0000000010000000)
-
-/*   SH_EVENT_OCCURRED_II_INT0                                          */
-/*   Description:  Pending II 0 Interrupt                               */
-#define SH_EVENT_OCCURRED_II_INT0_SHFT			29
-#define SH_EVENT_OCCURRED_II_INT0_MASK	__IA64_UL_CONST(0x0000000020000000)
-
-/*   SH_EVENT_OCCURRED_II_INT1                                          */
-/*   Description:  Pending II 1 Interrupt                               */
-#define SH_EVENT_OCCURRED_II_INT1_SHFT			30
-#define SH_EVENT_OCCURRED_II_INT1_MASK	__IA64_UL_CONST(0x0000000040000000)
-
-/*   SH2_EVENT_OCCURRED_EXTIO_INT2                                      */
-/*   Description:  Pending SHUB 2 EXT IO INT2                           */
-#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT		33
-#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
-
-/*   SH2_EVENT_OCCURRED_EXTIO_INT3                                      */
-/*   Description:  Pending SHUB 2 EXT IO INT3                           */
-#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT		34
-#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
-
-#define SH_ALL_INT_MASK \
-	(SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
-	 SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
-	 SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
-	 SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
-
-
-/* ==================================================================== */
-/*                         LEDS                                         */
-/* ==================================================================== */
-#define SH1_REAL_JUNK_BUS_LED0			0x7fed00000UL
-#define SH1_REAL_JUNK_BUS_LED1			0x7fed10000UL
-#define SH1_REAL_JUNK_BUS_LED2			0x7fed20000UL
-#define SH1_REAL_JUNK_BUS_LED3			0x7fed30000UL
-
-#define SH2_REAL_JUNK_BUS_LED0			0xf0000000UL
-#define SH2_REAL_JUNK_BUS_LED1			0xf0010000UL
-#define SH2_REAL_JUNK_BUS_LED2			0xf0020000UL
-#define SH2_REAL_JUNK_BUS_LED3			0xf0030000UL
-
-/* ==================================================================== */
-/*                         Register "SH1_PTC_0"                         */
-/*       Puge Translation Cache Message Configuration Information       */
-/* ==================================================================== */
-#define SH1_PTC_0			__IA64_UL_CONST(0x00000001101a0000)
-
-/*   SH1_PTC_0_A                                                        */
-/*   Description:  Type                                                 */
-#define SH1_PTC_0_A_SHFT				0
-
-/*   SH1_PTC_0_PS                                                       */
-/*   Description:  Page Size                                            */
-#define SH1_PTC_0_PS_SHFT				2
-
-/*   SH1_PTC_0_RID                                                      */
-/*   Description:  Region ID                                            */
-#define SH1_PTC_0_RID_SHFT				8
-
-/*   SH1_PTC_0_START                                                    */
-/*   Description:  Start                                                */
-#define SH1_PTC_0_START_SHFT				63
-
-/* ==================================================================== */
-/*                         Register "SH1_PTC_1"                         */
-/*       Puge Translation Cache Message Configuration Information       */
-/* ==================================================================== */
-#define SH1_PTC_1			__IA64_UL_CONST(0x00000001101a0080)
-
-/*   SH1_PTC_1_START                                                    */
-/*   Description:  PTC_1 Start                                          */
-#define SH1_PTC_1_START_SHFT				63
-
-/* ==================================================================== */
-/*                         Register "SH2_PTC"                           */
-/*       Puge Translation Cache Message Configuration Information       */
-/* ==================================================================== */
-#define SH2_PTC				__IA64_UL_CONST(0x0000000170000000)
-
-/*   SH2_PTC_A                                                          */
-/*   Description:  Type                                                 */
-#define SH2_PTC_A_SHFT					0
-
-/*   SH2_PTC_PS                                                         */
-/*   Description:  Page Size                                            */
-#define SH2_PTC_PS_SHFT					2
-
-/*   SH2_PTC_RID                                                      */
-/*   Description:  Region ID                                            */
-#define SH2_PTC_RID_SHFT				4
-
-/*   SH2_PTC_START                                                      */
-/*   Description:  Start                                                */
-#define SH2_PTC_START_SHFT				63
-
-/*   SH2_PTC_ADDR_RID                                                   */
-/*   Description:  Region ID                                            */
-#define SH2_PTC_ADDR_SHFT				4
-#define SH2_PTC_ADDR_MASK		__IA64_UL_CONST(0x1ffffffffffff000)
-
-/* ==================================================================== */
-/*                    Register "SH_RTC1_INT_CONFIG"                     */
-/*                SHub RTC 1 Interrupt Config Registers                 */
-/* ==================================================================== */
-
-#define SH1_RTC1_INT_CONFIG		__IA64_UL_CONST(0x0000000110001480)
-#define SH2_RTC1_INT_CONFIG		__IA64_UL_CONST(0x0000000010001480)
-#define SH_RTC1_INT_CONFIG_MASK		__IA64_UL_CONST(0x0ff3ffffffefffff)
-#define SH_RTC1_INT_CONFIG_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_RTC1_INT_CONFIG_TYPE                                            */
-/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
-#define SH_RTC1_INT_CONFIG_TYPE_SHFT			0
-#define SH_RTC1_INT_CONFIG_TYPE_MASK	__IA64_UL_CONST(0x0000000000000007)
-
-/*   SH_RTC1_INT_CONFIG_AGT                                             */
-/*   Description:  Agent, must be 0 for SHub                            */
-#define SH_RTC1_INT_CONFIG_AGT_SHFT			3
-#define SH_RTC1_INT_CONFIG_AGT_MASK	__IA64_UL_CONST(0x0000000000000008)
-
-/*   SH_RTC1_INT_CONFIG_PID                                             */
-/*   Description:  Processor ID, same setting as on targeted McKinley  */
-#define SH_RTC1_INT_CONFIG_PID_SHFT			4
-#define SH_RTC1_INT_CONFIG_PID_MASK	__IA64_UL_CONST(0x00000000000ffff0)
-
-/*   SH_RTC1_INT_CONFIG_BASE                                            */
-/*   Description:  Optional interrupt vector area, 2MB aligned          */
-#define SH_RTC1_INT_CONFIG_BASE_SHFT			21
-#define SH_RTC1_INT_CONFIG_BASE_MASK	__IA64_UL_CONST(0x0003ffffffe00000)
-
-/*   SH_RTC1_INT_CONFIG_IDX                                             */
-/*   Description:  Targeted McKinley interrupt vector                   */
-#define SH_RTC1_INT_CONFIG_IDX_SHFT			52
-#define SH_RTC1_INT_CONFIG_IDX_MASK	__IA64_UL_CONST(0x0ff0000000000000)
-
-/* ==================================================================== */
-/*                    Register "SH_RTC1_INT_ENABLE"                     */
-/*                SHub RTC 1 Interrupt Enable Registers                 */
-/* ==================================================================== */
-
-#define SH1_RTC1_INT_ENABLE		__IA64_UL_CONST(0x0000000110001500)
-#define SH2_RTC1_INT_ENABLE		__IA64_UL_CONST(0x0000000010001500)
-#define SH_RTC1_INT_ENABLE_MASK		__IA64_UL_CONST(0x0000000000000001)
-#define SH_RTC1_INT_ENABLE_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
-/*   Description:  Enable RTC 1 Interrupt                               */
-#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT		0
-#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
-					__IA64_UL_CONST(0x0000000000000001)
-
-/* ==================================================================== */
-/*                    Register "SH_RTC2_INT_CONFIG"                     */
-/*                SHub RTC 2 Interrupt Config Registers                 */
-/* ==================================================================== */
-
-#define SH1_RTC2_INT_CONFIG		__IA64_UL_CONST(0x0000000110001580)
-#define SH2_RTC2_INT_CONFIG		__IA64_UL_CONST(0x0000000010001580)
-#define SH_RTC2_INT_CONFIG_MASK		__IA64_UL_CONST(0x0ff3ffffffefffff)
-#define SH_RTC2_INT_CONFIG_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_RTC2_INT_CONFIG_TYPE                                            */
-/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
-#define SH_RTC2_INT_CONFIG_TYPE_SHFT			0
-#define SH_RTC2_INT_CONFIG_TYPE_MASK	__IA64_UL_CONST(0x0000000000000007)
-
-/*   SH_RTC2_INT_CONFIG_AGT                                             */
-/*   Description:  Agent, must be 0 for SHub                            */
-#define SH_RTC2_INT_CONFIG_AGT_SHFT			3
-#define SH_RTC2_INT_CONFIG_AGT_MASK	__IA64_UL_CONST(0x0000000000000008)
-
-/*   SH_RTC2_INT_CONFIG_PID                                             */
-/*   Description:  Processor ID, same setting as on targeted McKinley  */
-#define SH_RTC2_INT_CONFIG_PID_SHFT			4
-#define SH_RTC2_INT_CONFIG_PID_MASK	__IA64_UL_CONST(0x00000000000ffff0)
-
-/*   SH_RTC2_INT_CONFIG_BASE                                            */
-/*   Description:  Optional interrupt vector area, 2MB aligned          */
-#define SH_RTC2_INT_CONFIG_BASE_SHFT			21
-#define SH_RTC2_INT_CONFIG_BASE_MASK	__IA64_UL_CONST(0x0003ffffffe00000)
-
-/*   SH_RTC2_INT_CONFIG_IDX                                             */
-/*   Description:  Targeted McKinley interrupt vector                   */
-#define SH_RTC2_INT_CONFIG_IDX_SHFT			52
-#define SH_RTC2_INT_CONFIG_IDX_MASK	__IA64_UL_CONST(0x0ff0000000000000)
-
-/* ==================================================================== */
-/*                    Register "SH_RTC2_INT_ENABLE"                     */
-/*                SHub RTC 2 Interrupt Enable Registers                 */
-/* ==================================================================== */
-
-#define SH1_RTC2_INT_ENABLE		__IA64_UL_CONST(0x0000000110001600)
-#define SH2_RTC2_INT_ENABLE		__IA64_UL_CONST(0x0000000010001600)
-#define SH_RTC2_INT_ENABLE_MASK		__IA64_UL_CONST(0x0000000000000001)
-#define SH_RTC2_INT_ENABLE_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
-/*   Description:  Enable RTC 2 Interrupt                               */
-#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT		0
-#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
-					__IA64_UL_CONST(0x0000000000000001)
-
-/* ==================================================================== */
-/*                    Register "SH_RTC3_INT_CONFIG"                     */
-/*                SHub RTC 3 Interrupt Config Registers                 */
-/* ==================================================================== */
-
-#define SH1_RTC3_INT_CONFIG		__IA64_UL_CONST(0x0000000110001680)
-#define SH2_RTC3_INT_CONFIG		__IA64_UL_CONST(0x0000000010001680)
-#define SH_RTC3_INT_CONFIG_MASK		__IA64_UL_CONST(0x0ff3ffffffefffff)
-#define SH_RTC3_INT_CONFIG_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_RTC3_INT_CONFIG_TYPE                                            */
-/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
-#define SH_RTC3_INT_CONFIG_TYPE_SHFT			0
-#define SH_RTC3_INT_CONFIG_TYPE_MASK	__IA64_UL_CONST(0x0000000000000007)
-
-/*   SH_RTC3_INT_CONFIG_AGT                                             */
-/*   Description:  Agent, must be 0 for SHub                            */
-#define SH_RTC3_INT_CONFIG_AGT_SHFT			3
-#define SH_RTC3_INT_CONFIG_AGT_MASK	__IA64_UL_CONST(0x0000000000000008)
-
-/*   SH_RTC3_INT_CONFIG_PID                                             */
-/*   Description:  Processor ID, same setting as on targeted McKinley  */
-#define SH_RTC3_INT_CONFIG_PID_SHFT			4
-#define SH_RTC3_INT_CONFIG_PID_MASK	__IA64_UL_CONST(0x00000000000ffff0)
-
-/*   SH_RTC3_INT_CONFIG_BASE                                            */
-/*   Description:  Optional interrupt vector area, 2MB aligned          */
-#define SH_RTC3_INT_CONFIG_BASE_SHFT			21
-#define SH_RTC3_INT_CONFIG_BASE_MASK	__IA64_UL_CONST(0x0003ffffffe00000)
-
-/*   SH_RTC3_INT_CONFIG_IDX                                             */
-/*   Description:  Targeted McKinley interrupt vector                   */
-#define SH_RTC3_INT_CONFIG_IDX_SHFT			52
-#define SH_RTC3_INT_CONFIG_IDX_MASK	__IA64_UL_CONST(0x0ff0000000000000)
-
-/* ==================================================================== */
-/*                    Register "SH_RTC3_INT_ENABLE"                     */
-/*                SHub RTC 3 Interrupt Enable Registers                 */
-/* ==================================================================== */
-
-#define SH1_RTC3_INT_ENABLE		__IA64_UL_CONST(0x0000000110001700)
-#define SH2_RTC3_INT_ENABLE		__IA64_UL_CONST(0x0000000010001700)
-#define SH_RTC3_INT_ENABLE_MASK		__IA64_UL_CONST(0x0000000000000001)
-#define SH_RTC3_INT_ENABLE_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
-/*   Description:  Enable RTC 3 Interrupt                               */
-#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT		0
-#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
-					__IA64_UL_CONST(0x0000000000000001)
-
-/*   SH_EVENT_OCCURRED_RTC1_INT                                         */
-/*   Description:  Pending RTC 1 Interrupt                              */
-#define SH_EVENT_OCCURRED_RTC1_INT_SHFT			24
-#define SH_EVENT_OCCURRED_RTC1_INT_MASK	__IA64_UL_CONST(0x0000000001000000)
-
-/*   SH_EVENT_OCCURRED_RTC2_INT                                         */
-/*   Description:  Pending RTC 2 Interrupt                              */
-#define SH_EVENT_OCCURRED_RTC2_INT_SHFT			25
-#define SH_EVENT_OCCURRED_RTC2_INT_MASK	__IA64_UL_CONST(0x0000000002000000)
-
-/*   SH_EVENT_OCCURRED_RTC3_INT                                         */
-/*   Description:  Pending RTC 3 Interrupt                              */
-#define SH_EVENT_OCCURRED_RTC3_INT_SHFT			26
-#define SH_EVENT_OCCURRED_RTC3_INT_MASK	__IA64_UL_CONST(0x0000000004000000)
-
-/* ==================================================================== */
-/*                       Register "SH_IPI_ACCESS"                       */
-/*                 CPU interrupt Access Permission Bits                 */
-/* ==================================================================== */
-
-#define SH1_IPI_ACCESS			__IA64_UL_CONST(0x0000000110060480)
-#define SH2_IPI_ACCESS0			__IA64_UL_CONST(0x0000000010060c00)
-#define SH2_IPI_ACCESS1			__IA64_UL_CONST(0x0000000010060c80)
-#define SH2_IPI_ACCESS2			__IA64_UL_CONST(0x0000000010060d00)
-#define SH2_IPI_ACCESS3			__IA64_UL_CONST(0x0000000010060d80)
-
-/* ==================================================================== */
-/*                        Register "SH_INT_CMPB"                        */
-/*                  RTC Compare Value for Processor B                   */
-/* ==================================================================== */
-
-#define SH1_INT_CMPB			__IA64_UL_CONST(0x00000001101b0080)
-#define SH2_INT_CMPB			__IA64_UL_CONST(0x00000000101b0080)
-#define SH_INT_CMPB_MASK		__IA64_UL_CONST(0x007fffffffffffff)
-#define SH_INT_CMPB_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
-/*   Description:  Real Time Clock Compare                              */
-#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT			0
-#define SH_INT_CMPB_REAL_TIME_CMPB_MASK	__IA64_UL_CONST(0x007fffffffffffff)
-
-/* ==================================================================== */
-/*                        Register "SH_INT_CMPC"                        */
-/*                  RTC Compare Value for Processor C                   */
-/* ==================================================================== */
-
-#define SH1_INT_CMPC			__IA64_UL_CONST(0x00000001101b0100)
-#define SH2_INT_CMPC			__IA64_UL_CONST(0x00000000101b0100)
-#define SH_INT_CMPC_MASK		__IA64_UL_CONST(0x007fffffffffffff)
-#define SH_INT_CMPC_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
-/*   Description:  Real Time Clock Compare                              */
-#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT			0
-#define SH_INT_CMPC_REAL_TIME_CMPC_MASK	__IA64_UL_CONST(0x007fffffffffffff)
-
-/* ==================================================================== */
-/*                        Register "SH_INT_CMPD"                        */
-/*                  RTC Compare Value for Processor D                   */
-/* ==================================================================== */
-
-#define SH1_INT_CMPD			__IA64_UL_CONST(0x00000001101b0180)
-#define SH2_INT_CMPD			__IA64_UL_CONST(0x00000000101b0180)
-#define SH_INT_CMPD_MASK		__IA64_UL_CONST(0x007fffffffffffff)
-#define SH_INT_CMPD_INIT		__IA64_UL_CONST(0x0000000000000000)
-
-/*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
-/*   Description:  Real Time Clock Compare                              */
-#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT			0
-#define SH_INT_CMPD_REAL_TIME_CMPD_MASK	__IA64_UL_CONST(0x007fffffffffffff)
-
-/* ==================================================================== */
-/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
-/*                      privilege vector for acc=0                      */
-/* ==================================================================== */
-#define SH1_MD_DQLP_MMR_DIR_PRIVEC0	__IA64_UL_CONST(0x0000000100030300)
-
-/* ==================================================================== */
-/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
-/*                      privilege vector for acc=0                      */
-/* ==================================================================== */
-#define SH1_MD_DQRP_MMR_DIR_PRIVEC0	__IA64_UL_CONST(0x0000000100050300)
-
-/* ==================================================================== */
-/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
-/* and SHUB2 that it makes sense to define a geberic name for the MMR.  */
-/* It is acceptable to use (for example) SH_IPI_INT to reference the    */
-/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based  */
-/* on the type of the SHUB. Do not use these #defines in performance    */
-/* critical code  or loops - there is a small performance penalty.      */
-/* ==================================================================== */
-#define shubmmr(a,b) 		(is_shub2() ? a##2_##b : a##1_##b)
-
-#define SH_REAL_JUNK_BUS_LED0	shubmmr(SH, REAL_JUNK_BUS_LED0)
-#define SH_IPI_INT		shubmmr(SH, IPI_INT)
-#define SH_EVENT_OCCURRED	shubmmr(SH, EVENT_OCCURRED)
-#define SH_EVENT_OCCURRED_ALIAS	shubmmr(SH, EVENT_OCCURRED_ALIAS)
-#define SH_RTC			shubmmr(SH, RTC)
-#define SH_RTC1_INT_CONFIG	shubmmr(SH, RTC1_INT_CONFIG)
-#define SH_RTC1_INT_ENABLE	shubmmr(SH, RTC1_INT_ENABLE)
-#define SH_RTC2_INT_CONFIG	shubmmr(SH, RTC2_INT_CONFIG)
-#define SH_RTC2_INT_ENABLE	shubmmr(SH, RTC2_INT_ENABLE)
-#define SH_RTC3_INT_CONFIG	shubmmr(SH, RTC3_INT_CONFIG)
-#define SH_RTC3_INT_ENABLE	shubmmr(SH, RTC3_INT_ENABLE)
-#define SH_INT_CMPB		shubmmr(SH, INT_CMPB)
-#define SH_INT_CMPC		shubmmr(SH, INT_CMPC)
-#define SH_INT_CMPD		shubmmr(SH, INT_CMPD)
-
-/* ========================================================================== */
-/*                        Register "SH2_BT_ENG_CSR_0"                         */
-/*                    Engine 0 Control and Status Register                    */
-/* ========================================================================== */
-
-#define SH2_BT_ENG_CSR_0		__IA64_UL_CONST(0x0000000030040000)
-#define SH2_BT_ENG_SRC_ADDR_0		__IA64_UL_CONST(0x0000000030040080)
-#define SH2_BT_ENG_DEST_ADDR_0		__IA64_UL_CONST(0x0000000030040100)
-#define SH2_BT_ENG_NOTIF_ADDR_0		__IA64_UL_CONST(0x0000000030040180)
-
-/* ========================================================================== */
-/*                       BTE interfaces 1-3                                   */
-/* ========================================================================== */
-
-#define SH2_BT_ENG_CSR_1		__IA64_UL_CONST(0x0000000030050000)
-#define SH2_BT_ENG_CSR_2		__IA64_UL_CONST(0x0000000030060000)
-#define SH2_BT_ENG_CSR_3		__IA64_UL_CONST(0x0000000030070000)
-
-#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/arch/ia64/include/asm/sn/shubio.h b/arch/ia64/include/asm/sn/shubio.h
deleted file mode 100644
index 8a1ec139f977..000000000000
--- a/arch/ia64/include/asm/sn/shubio.h
+++ /dev/null
@@ -1,3358 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_SHUBIO_H
-#define _ASM_IA64_SN_SHUBIO_H
-
-#define HUB_WIDGET_ID_MAX	0xf
-#define IIO_NUM_ITTES		7
-#define HUB_NUM_BIG_WINDOW	(IIO_NUM_ITTES - 1)
-
-#define		IIO_WID			0x00400000	/* Crosstalk Widget Identification */
-							/* This register is also accessible from
-							 * Crosstalk at address 0x0.  */
-#define		IIO_WSTAT		0x00400008	/* Crosstalk Widget Status */
-#define		IIO_WCR			0x00400020	/* Crosstalk Widget Control Register */
-#define		IIO_ILAPR		0x00400100	/* IO Local Access Protection Register */
-#define		IIO_ILAPO		0x00400108	/* IO Local Access Protection Override */
-#define		IIO_IOWA		0x00400110	/* IO Outbound Widget Access */
-#define		IIO_IIWA		0x00400118	/* IO Inbound Widget Access */
-#define		IIO_IIDEM		0x00400120	/* IO Inbound Device Error Mask */
-#define		IIO_ILCSR		0x00400128	/* IO LLP Control and Status Register */
-#define		IIO_ILLR		0x00400130	/* IO LLP Log Register    */
-#define		IIO_IIDSR		0x00400138	/* IO Interrupt Destination */
-
-#define		IIO_IGFX0		0x00400140	/* IO Graphics Node-Widget Map 0 */
-#define		IIO_IGFX1		0x00400148	/* IO Graphics Node-Widget Map 1 */
-
-#define		IIO_ISCR0		0x00400150	/* IO Scratch Register 0 */
-#define		IIO_ISCR1		0x00400158	/* IO Scratch Register 1 */
-
-#define		IIO_ITTE1		0x00400160	/* IO Translation Table Entry 1 */
-#define		IIO_ITTE2		0x00400168	/* IO Translation Table Entry 2 */
-#define		IIO_ITTE3		0x00400170	/* IO Translation Table Entry 3 */
-#define		IIO_ITTE4		0x00400178	/* IO Translation Table Entry 4 */
-#define		IIO_ITTE5		0x00400180	/* IO Translation Table Entry 5 */
-#define		IIO_ITTE6		0x00400188	/* IO Translation Table Entry 6 */
-#define		IIO_ITTE7		0x00400190	/* IO Translation Table Entry 7 */
-
-#define		IIO_IPRB0		0x00400198	/* IO PRB Entry 0   */
-#define		IIO_IPRB8		0x004001A0	/* IO PRB Entry 8   */
-#define		IIO_IPRB9		0x004001A8	/* IO PRB Entry 9   */
-#define		IIO_IPRBA		0x004001B0	/* IO PRB Entry A   */
-#define		IIO_IPRBB		0x004001B8	/* IO PRB Entry B   */
-#define		IIO_IPRBC		0x004001C0	/* IO PRB Entry C   */
-#define		IIO_IPRBD		0x004001C8	/* IO PRB Entry D   */
-#define		IIO_IPRBE		0x004001D0	/* IO PRB Entry E   */
-#define		IIO_IPRBF		0x004001D8	/* IO PRB Entry F   */
-
-#define		IIO_IXCC		0x004001E0	/* IO Crosstalk Credit Count Timeout */
-#define		IIO_IMEM		0x004001E8	/* IO Miscellaneous Error Mask */
-#define		IIO_IXTT		0x004001F0	/* IO Crosstalk Timeout Threshold */
-#define		IIO_IECLR		0x004001F8	/* IO Error Clear Register */
-#define		IIO_IBCR		0x00400200	/* IO BTE Control Register */
-
-#define		IIO_IXSM		0x00400208	/* IO Crosstalk Spurious Message */
-#define		IIO_IXSS		0x00400210	/* IO Crosstalk Spurious Sideband */
-
-#define		IIO_ILCT		0x00400218	/* IO LLP Channel Test    */
-
-#define		IIO_IIEPH1 		0x00400220	/* IO Incoming Error Packet Header, Part 1 */
-#define		IIO_IIEPH2 		0x00400228	/* IO Incoming Error Packet Header, Part 2 */
-
-#define		IIO_ISLAPR 		0x00400230	/* IO SXB Local Access Protection Regster */
-#define		IIO_ISLAPO 		0x00400238	/* IO SXB Local Access Protection Override */
-
-#define		IIO_IWI			0x00400240	/* IO Wrapper Interrupt Register */
-#define		IIO_IWEL		0x00400248	/* IO Wrapper Error Log Register */
-#define		IIO_IWC			0x00400250	/* IO Wrapper Control Register */
-#define		IIO_IWS			0x00400258	/* IO Wrapper Status Register */
-#define		IIO_IWEIM		0x00400260	/* IO Wrapper Error Interrupt Masking Register */
-
-#define		IIO_IPCA		0x00400300	/* IO PRB Counter Adjust */
-
-#define		IIO_IPRTE0_A		0x00400308	/* IO PIO Read Address Table Entry 0, Part A */
-#define		IIO_IPRTE1_A		0x00400310	/* IO PIO Read Address Table Entry 1, Part A */
-#define		IIO_IPRTE2_A		0x00400318	/* IO PIO Read Address Table Entry 2, Part A */
-#define		IIO_IPRTE3_A		0x00400320	/* IO PIO Read Address Table Entry 3, Part A */
-#define		IIO_IPRTE4_A		0x00400328	/* IO PIO Read Address Table Entry 4, Part A */
-#define		IIO_IPRTE5_A		0x00400330	/* IO PIO Read Address Table Entry 5, Part A */
-#define		IIO_IPRTE6_A		0x00400338	/* IO PIO Read Address Table Entry 6, Part A */
-#define		IIO_IPRTE7_A		0x00400340	/* IO PIO Read Address Table Entry 7, Part A */
-
-#define		IIO_IPRTE0_B		0x00400348	/* IO PIO Read Address Table Entry 0, Part B */
-#define		IIO_IPRTE1_B		0x00400350	/* IO PIO Read Address Table Entry 1, Part B */
-#define		IIO_IPRTE2_B		0x00400358	/* IO PIO Read Address Table Entry 2, Part B */
-#define		IIO_IPRTE3_B		0x00400360	/* IO PIO Read Address Table Entry 3, Part B */
-#define		IIO_IPRTE4_B		0x00400368	/* IO PIO Read Address Table Entry 4, Part B */
-#define		IIO_IPRTE5_B		0x00400370	/* IO PIO Read Address Table Entry 5, Part B */
-#define		IIO_IPRTE6_B		0x00400378	/* IO PIO Read Address Table Entry 6, Part B */
-#define		IIO_IPRTE7_B		0x00400380	/* IO PIO Read Address Table Entry 7, Part B */
-
-#define		IIO_IPDR		0x00400388	/* IO PIO Deallocation Register */
-#define		IIO_ICDR		0x00400390	/* IO CRB Entry Deallocation Register */
-#define		IIO_IFDR		0x00400398	/* IO IOQ FIFO Depth Register */
-#define		IIO_IIAP		0x004003A0	/* IO IIQ Arbitration Parameters */
-#define		IIO_ICMR		0x004003A8	/* IO CRB Management Register */
-#define		IIO_ICCR		0x004003B0	/* IO CRB Control Register */
-#define		IIO_ICTO		0x004003B8	/* IO CRB Timeout   */
-#define		IIO_ICTP		0x004003C0	/* IO CRB Timeout Prescalar */
-
-#define		IIO_ICRB0_A		0x00400400	/* IO CRB Entry 0_A */
-#define		IIO_ICRB0_B		0x00400408	/* IO CRB Entry 0_B */
-#define		IIO_ICRB0_C		0x00400410	/* IO CRB Entry 0_C */
-#define		IIO_ICRB0_D		0x00400418	/* IO CRB Entry 0_D */
-#define		IIO_ICRB0_E		0x00400420	/* IO CRB Entry 0_E */
-
-#define		IIO_ICRB1_A		0x00400430	/* IO CRB Entry 1_A */
-#define		IIO_ICRB1_B		0x00400438	/* IO CRB Entry 1_B */
-#define		IIO_ICRB1_C		0x00400440	/* IO CRB Entry 1_C */
-#define		IIO_ICRB1_D		0x00400448	/* IO CRB Entry 1_D */
-#define		IIO_ICRB1_E		0x00400450	/* IO CRB Entry 1_E */
-
-#define		IIO_ICRB2_A		0x00400460	/* IO CRB Entry 2_A */
-#define		IIO_ICRB2_B		0x00400468	/* IO CRB Entry 2_B */
-#define		IIO_ICRB2_C		0x00400470	/* IO CRB Entry 2_C */
-#define		IIO_ICRB2_D		0x00400478	/* IO CRB Entry 2_D */
-#define		IIO_ICRB2_E		0x00400480	/* IO CRB Entry 2_E */
-
-#define		IIO_ICRB3_A		0x00400490	/* IO CRB Entry 3_A */
-#define		IIO_ICRB3_B		0x00400498	/* IO CRB Entry 3_B */
-#define		IIO_ICRB3_C		0x004004a0	/* IO CRB Entry 3_C */
-#define		IIO_ICRB3_D		0x004004a8	/* IO CRB Entry 3_D */
-#define		IIO_ICRB3_E		0x004004b0	/* IO CRB Entry 3_E */
-
-#define		IIO_ICRB4_A		0x004004c0	/* IO CRB Entry 4_A */
-#define		IIO_ICRB4_B		0x004004c8	/* IO CRB Entry 4_B */
-#define		IIO_ICRB4_C		0x004004d0	/* IO CRB Entry 4_C */
-#define		IIO_ICRB4_D		0x004004d8	/* IO CRB Entry 4_D */
-#define		IIO_ICRB4_E		0x004004e0	/* IO CRB Entry 4_E */
-
-#define		IIO_ICRB5_A		0x004004f0	/* IO CRB Entry 5_A */
-#define		IIO_ICRB5_B		0x004004f8	/* IO CRB Entry 5_B */
-#define		IIO_ICRB5_C		0x00400500	/* IO CRB Entry 5_C */
-#define		IIO_ICRB5_D		0x00400508	/* IO CRB Entry 5_D */
-#define		IIO_ICRB5_E		0x00400510	/* IO CRB Entry 5_E */
-
-#define		IIO_ICRB6_A		0x00400520	/* IO CRB Entry 6_A */
-#define		IIO_ICRB6_B		0x00400528	/* IO CRB Entry 6_B */
-#define		IIO_ICRB6_C		0x00400530	/* IO CRB Entry 6_C */
-#define		IIO_ICRB6_D		0x00400538	/* IO CRB Entry 6_D */
-#define		IIO_ICRB6_E		0x00400540	/* IO CRB Entry 6_E */
-
-#define		IIO_ICRB7_A		0x00400550	/* IO CRB Entry 7_A */
-#define		IIO_ICRB7_B		0x00400558	/* IO CRB Entry 7_B */
-#define		IIO_ICRB7_C		0x00400560	/* IO CRB Entry 7_C */
-#define		IIO_ICRB7_D		0x00400568	/* IO CRB Entry 7_D */
-#define		IIO_ICRB7_E		0x00400570	/* IO CRB Entry 7_E */
-
-#define		IIO_ICRB8_A		0x00400580	/* IO CRB Entry 8_A */
-#define		IIO_ICRB8_B		0x00400588	/* IO CRB Entry 8_B */
-#define		IIO_ICRB8_C		0x00400590	/* IO CRB Entry 8_C */
-#define		IIO_ICRB8_D		0x00400598	/* IO CRB Entry 8_D */
-#define		IIO_ICRB8_E		0x004005a0	/* IO CRB Entry 8_E */
-
-#define		IIO_ICRB9_A		0x004005b0	/* IO CRB Entry 9_A */
-#define		IIO_ICRB9_B		0x004005b8	/* IO CRB Entry 9_B */
-#define		IIO_ICRB9_C		0x004005c0	/* IO CRB Entry 9_C */
-#define		IIO_ICRB9_D		0x004005c8	/* IO CRB Entry 9_D */
-#define		IIO_ICRB9_E		0x004005d0	/* IO CRB Entry 9_E */
-
-#define		IIO_ICRBA_A		0x004005e0	/* IO CRB Entry A_A */
-#define		IIO_ICRBA_B		0x004005e8	/* IO CRB Entry A_B */
-#define		IIO_ICRBA_C		0x004005f0	/* IO CRB Entry A_C */
-#define		IIO_ICRBA_D		0x004005f8	/* IO CRB Entry A_D */
-#define		IIO_ICRBA_E		0x00400600	/* IO CRB Entry A_E */
-
-#define		IIO_ICRBB_A		0x00400610	/* IO CRB Entry B_A */
-#define		IIO_ICRBB_B		0x00400618	/* IO CRB Entry B_B */
-#define		IIO_ICRBB_C		0x00400620	/* IO CRB Entry B_C */
-#define		IIO_ICRBB_D		0x00400628	/* IO CRB Entry B_D */
-#define		IIO_ICRBB_E		0x00400630	/* IO CRB Entry B_E */
-
-#define		IIO_ICRBC_A		0x00400640	/* IO CRB Entry C_A */
-#define		IIO_ICRBC_B		0x00400648	/* IO CRB Entry C_B */
-#define		IIO_ICRBC_C		0x00400650	/* IO CRB Entry C_C */
-#define		IIO_ICRBC_D		0x00400658	/* IO CRB Entry C_D */
-#define		IIO_ICRBC_E		0x00400660	/* IO CRB Entry C_E */
-
-#define		IIO_ICRBD_A		0x00400670	/* IO CRB Entry D_A */
-#define		IIO_ICRBD_B		0x00400678	/* IO CRB Entry D_B */
-#define		IIO_ICRBD_C		0x00400680	/* IO CRB Entry D_C */
-#define		IIO_ICRBD_D		0x00400688	/* IO CRB Entry D_D */
-#define		IIO_ICRBD_E		0x00400690	/* IO CRB Entry D_E */
-
-#define		IIO_ICRBE_A		0x004006a0	/* IO CRB Entry E_A */
-#define		IIO_ICRBE_B		0x004006a8	/* IO CRB Entry E_B */
-#define		IIO_ICRBE_C		0x004006b0	/* IO CRB Entry E_C */
-#define		IIO_ICRBE_D		0x004006b8	/* IO CRB Entry E_D */
-#define		IIO_ICRBE_E		0x004006c0	/* IO CRB Entry E_E */
-
-#define		IIO_ICSML		0x00400700	/* IO CRB Spurious Message Low */
-#define		IIO_ICSMM		0x00400708	/* IO CRB Spurious Message Middle */
-#define		IIO_ICSMH		0x00400710	/* IO CRB Spurious Message High */
-
-#define		IIO_IDBSS		0x00400718	/* IO Debug Submenu Select */
-
-#define		IIO_IBLS0		0x00410000	/* IO BTE Length Status 0 */
-#define		IIO_IBSA0		0x00410008	/* IO BTE Source Address 0 */
-#define		IIO_IBDA0		0x00410010	/* IO BTE Destination Address 0 */
-#define		IIO_IBCT0		0x00410018	/* IO BTE Control Terminate 0 */
-#define		IIO_IBNA0		0x00410020	/* IO BTE Notification Address 0 */
-#define		IIO_IBIA0		0x00410028	/* IO BTE Interrupt Address 0 */
-#define		IIO_IBLS1		0x00420000	/* IO BTE Length Status 1 */
-#define		IIO_IBSA1		0x00420008	/* IO BTE Source Address 1 */
-#define		IIO_IBDA1		0x00420010	/* IO BTE Destination Address 1 */
-#define		IIO_IBCT1		0x00420018	/* IO BTE Control Terminate 1 */
-#define		IIO_IBNA1		0x00420020	/* IO BTE Notification Address 1 */
-#define		IIO_IBIA1		0x00420028	/* IO BTE Interrupt Address 1 */
-
-#define		IIO_IPCR		0x00430000	/* IO Performance Control */
-#define		IIO_IPPR		0x00430008	/* IO Performance Profiling */
-
-/************************************************************************
- *									*
- * Description:  This register echoes some information from the         *
- * LB_REV_ID register. It is available through Crosstalk as described   *
- * above. The REV_NUM and MFG_NUM fields receive their values from      *
- * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
- * The PART_NUM field's value is the Crosstalk device ID number that    *
- * Steve Miller assigned to the SHub chip.                              *
- *									*
- ************************************************************************/
-
-typedef union ii_wid_u {
-	u64 ii_wid_regval;
-	struct {
-		u64 w_rsvd_1:1;
-		u64 w_mfg_num:11;
-		u64 w_part_num:16;
-		u64 w_rev_num:4;
-		u64 w_rsvd:32;
-	} ii_wid_fld_s;
-} ii_wid_u_t;
-
-/************************************************************************
- *									*
- *  The fields in this register are set upon detection of an error      *
- * and cleared by various mechanisms, as explained in the               *
- * description.                                                         *
- *									*
- ************************************************************************/
-
-typedef union ii_wstat_u {
-	u64 ii_wstat_regval;
-	struct {
-		u64 w_pending:4;
-		u64 w_xt_crd_to:1;
-		u64 w_xt_tail_to:1;
-		u64 w_rsvd_3:3;
-		u64 w_tx_mx_rty:1;
-		u64 w_rsvd_2:6;
-		u64 w_llp_tx_cnt:8;
-		u64 w_rsvd_1:8;
-		u64 w_crazy:1;
-		u64 w_rsvd:31;
-	} ii_wstat_fld_s;
-} ii_wstat_u_t;
-
-/************************************************************************
- *									*
- * Description:  This is a read-write enabled register. It controls     *
- * various aspects of the Crosstalk flow control.                       *
- *									*
- ************************************************************************/
-
-typedef union ii_wcr_u {
-	u64 ii_wcr_regval;
-	struct {
-		u64 w_wid:4;
-		u64 w_tag:1;
-		u64 w_rsvd_1:8;
-		u64 w_dst_crd:3;
-		u64 w_f_bad_pkt:1;
-		u64 w_dir_con:1;
-		u64 w_e_thresh:5;
-		u64 w_rsvd:41;
-	} ii_wcr_fld_s;
-} ii_wcr_u_t;
-
-/************************************************************************
- *									*
- * Description:  This register's value is a bit vector that guards      *
- * access to local registers within the II as well as to external       *
- * Crosstalk widgets. Each bit in the register corresponds to a         *
- * particular region in the system; a region consists of one, two or    *
- * four nodes (depending on the value of the REGION_SIZE field in the   *
- * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
- * protection provided by this register applies to PIO read             *
- * operations as well as PIO write operations. The II will perform a    *
- * PIO read or write request only if the bit for the requestor's        *
- * region is set; otherwise, the II will not perform the requested      *
- * operation and will return an error response. When a PIO read or      *
- * write request targets an external Crosstalk widget, then not only    *
- * must the bit for the requestor's region be set in the ILAPR, but     *
- * also the target widget's bit in the IOWA register must be set in     *
- * order for the II to perform the requested operation; otherwise,      *
- * the II will return an error response. Hence, the protection          *
- * provided by the IOWA register supplements the protection provided    *
- * by the ILAPR for requests that target external Crosstalk widgets.    *
- * This register itself can be accessed only by the nodes whose         *
- * region ID bits are enabled in this same register. It can also be     *
- * accessed through the IAlias space by the local processors.           *
- * The reset value of this register allows access by all nodes.         *
- *									*
- ************************************************************************/
-
-typedef union ii_ilapr_u {
-	u64 ii_ilapr_regval;
-	struct {
-		u64 i_region:64;
-	} ii_ilapr_fld_s;
-} ii_ilapr_u_t;
-
-/************************************************************************
- *									*
- * Description:  A write to this register of the 64-bit value           *
- * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
- * corresponding to the region of the requestor to be set (allow        *
- * access). A write of any other value will be ignored. Access          *
- * protection for this register is "SGIrules".                          *
- * This register can also be accessed through the IAlias space.         *
- * However, this access will not change the access permissions in the   *
- * ILAPR.                                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_ilapo_u {
-	u64 ii_ilapo_regval;
-	struct {
-		u64 i_io_ovrride:64;
-	} ii_ilapo_fld_s;
-} ii_ilapo_u_t;
-
-/************************************************************************
- *									*
- *  This register qualifies all the PIO and Graphics writes launched    *
- * from the SHUB towards a widget.                                      *
- *									*
- ************************************************************************/
-
-typedef union ii_iowa_u {
-	u64 ii_iowa_regval;
-	struct {
-		u64 i_w0_oac:1;
-		u64 i_rsvd_1:7;
-		u64 i_wx_oac:8;
-		u64 i_rsvd:48;
-	} ii_iowa_fld_s;
-} ii_iowa_u_t;
-
-/************************************************************************
- *									*
- * Description:  This register qualifies all the requests launched      *
- * from a widget towards the Shub. This register is intended to be      *
- * used by software in case of misbehaving widgets.                     *
- *									*
- *									*
- ************************************************************************/
-
-typedef union ii_iiwa_u {
-	u64 ii_iiwa_regval;
-	struct {
-		u64 i_w0_iac:1;
-		u64 i_rsvd_1:7;
-		u64 i_wx_iac:8;
-		u64 i_rsvd:48;
-	} ii_iiwa_fld_s;
-} ii_iiwa_u_t;
-
-/************************************************************************
- *									*
- * Description:  This register qualifies all the operations launched    *
- * from a widget towards the SHub. It allows individual access          *
- * control for up to 8 devices per widget. A device refers to           *
- * individual DMA master hosted by a widget.                            *
- * The bits in each field of this register are cleared by the Shub      *
- * upon detection of an error which requires the device to be           *
- * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
- * Crosstalk). Whether or not a device has access rights to this        *
- * Shub is determined by an AND of the device enable bit in the         *
- * appropriate field of this register and the corresponding bit in      *
- * the Wx_IAC field (for the widget which this device belongs to).      *
- * The bits in this field are set by writing a 1 to them. Incoming      *
- * replies from Crosstalk are not subject to this access control        *
- * mechanism.                                                           *
- *									*
- ************************************************************************/
-
-typedef union ii_iidem_u {
-	u64 ii_iidem_regval;
-	struct {
-		u64 i_w8_dxs:8;
-		u64 i_w9_dxs:8;
-		u64 i_wa_dxs:8;
-		u64 i_wb_dxs:8;
-		u64 i_wc_dxs:8;
-		u64 i_wd_dxs:8;
-		u64 i_we_dxs:8;
-		u64 i_wf_dxs:8;
-	} ii_iidem_fld_s;
-} ii_iidem_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the various programmable fields necessary    *
- * for controlling and observing the LLP signals.                       *
- *									*
- ************************************************************************/
-
-typedef union ii_ilcsr_u {
-	u64 ii_ilcsr_regval;
-	struct {
-		u64 i_nullto:6;
-		u64 i_rsvd_4:2;
-		u64 i_wrmrst:1;
-		u64 i_rsvd_3:1;
-		u64 i_llp_en:1;
-		u64 i_bm8:1;
-		u64 i_llp_stat:2;
-		u64 i_remote_power:1;
-		u64 i_rsvd_2:1;
-		u64 i_maxrtry:10;
-		u64 i_d_avail_sel:2;
-		u64 i_rsvd_1:4;
-		u64 i_maxbrst:10;
-		u64 i_rsvd:22;
-
-	} ii_ilcsr_fld_s;
-} ii_ilcsr_u_t;
-
-/************************************************************************
- *									*
- *  This is simply a status registers that monitors the LLP error       *
- * rate.								*
- *									*
- ************************************************************************/
-
-typedef union ii_illr_u {
-	u64 ii_illr_regval;
-	struct {
-		u64 i_sn_cnt:16;
-		u64 i_cb_cnt:16;
-		u64 i_rsvd:32;
-	} ii_illr_fld_s;
-} ii_illr_u_t;
-
-/************************************************************************
- *									*
- * Description:  All II-detected non-BTE error interrupts are           *
- * specified via this register.                                         *
- * NOTE: The PI interrupt register address is hardcoded in the II. If   *
- * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
- * packet) to address offset 0x0180_0090 within the local register      *
- * address space of PI0 on the node specified by the NODE field. If     *
- * PI_ID==1, then the II sends the interrupt request to address         *
- * offset 0x01A0_0090 within the local register address space of PI1    *
- * on the node specified by the NODE field.                             *
- *									*
- ************************************************************************/
-
-typedef union ii_iidsr_u {
-	u64 ii_iidsr_regval;
-	struct {
-		u64 i_level:8;
-		u64 i_pi_id:1;
-		u64 i_node:11;
-		u64 i_rsvd_3:4;
-		u64 i_enable:1;
-		u64 i_rsvd_2:3;
-		u64 i_int_sent:2;
-		u64 i_rsvd_1:2;
-		u64 i_pi0_forward_int:1;
-		u64 i_pi1_forward_int:1;
-		u64 i_rsvd:30;
-	} ii_iidsr_fld_s;
-} ii_iidsr_u_t;
-
-/************************************************************************
- *									*
- *  There are two instances of this register. This register is used     *
- * for matching up the incoming responses from the graphics widget to   *
- * the processor that initiated the graphics operation. The             *
- * write-responses are converted to graphics credits and returned to    *
- * the processor so that the processor interface can manage the flow    *
- * control.                                                             *
- *									*
- ************************************************************************/
-
-typedef union ii_igfx0_u {
-	u64 ii_igfx0_regval;
-	struct {
-		u64 i_w_num:4;
-		u64 i_pi_id:1;
-		u64 i_n_num:12;
-		u64 i_p_num:1;
-		u64 i_rsvd:46;
-	} ii_igfx0_fld_s;
-} ii_igfx0_u_t;
-
-/************************************************************************
- *									*
- *  There are two instances of this register. This register is used     *
- * for matching up the incoming responses from the graphics widget to   *
- * the processor that initiated the graphics operation. The             *
- * write-responses are converted to graphics credits and returned to    *
- * the processor so that the processor interface can manage the flow    *
- * control.                                                             *
- *									*
- ************************************************************************/
-
-typedef union ii_igfx1_u {
-	u64 ii_igfx1_regval;
-	struct {
-		u64 i_w_num:4;
-		u64 i_pi_id:1;
-		u64 i_n_num:12;
-		u64 i_p_num:1;
-		u64 i_rsvd:46;
-	} ii_igfx1_fld_s;
-} ii_igfx1_u_t;
-
-/************************************************************************
- *									*
- *  There are two instances of this registers. These registers are      *
- * used as scratch registers for software use.                          *
- *									*
- ************************************************************************/
-
-typedef union ii_iscr0_u {
-	u64 ii_iscr0_regval;
-	struct {
-		u64 i_scratch:64;
-	} ii_iscr0_fld_s;
-} ii_iscr0_u_t;
-
-/************************************************************************
- *									*
- *  There are two instances of this registers. These registers are      *
- * used as scratch registers for software use.                          *
- *									*
- ************************************************************************/
-
-typedef union ii_iscr1_u {
-	u64 ii_iscr1_regval;
-	struct {
-		u64 i_scratch:64;
-	} ii_iscr1_fld_s;
-} ii_iscr1_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the SHub is thus the lower 16 GBytes per widget       * 
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the Shub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *									*
- ************************************************************************/
-
-typedef union ii_itte1_u {
-	u64 ii_itte1_regval;
-	struct {
-		u64 i_offset:5;
-		u64 i_rsvd_1:3;
-		u64 i_w_num:4;
-		u64 i_iosp:1;
-		u64 i_rsvd:51;
-	} ii_itte1_fld_s;
-} ii_itte1_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the Shub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *									*
- ************************************************************************/
-
-typedef union ii_itte2_u {
-	u64 ii_itte2_regval;
-	struct {
-		u64 i_offset:5;
-		u64 i_rsvd_1:3;
-		u64 i_w_num:4;
-		u64 i_iosp:1;
-		u64 i_rsvd:51;
-	} ii_itte2_fld_s;
-} ii_itte2_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the SHub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *									*
- ************************************************************************/
-
-typedef union ii_itte3_u {
-	u64 ii_itte3_regval;
-	struct {
-		u64 i_offset:5;
-		u64 i_rsvd_1:3;
-		u64 i_w_num:4;
-		u64 i_iosp:1;
-		u64 i_rsvd:51;
-	} ii_itte3_fld_s;
-} ii_itte3_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a SHub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the SHub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the SHub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *									*
- ************************************************************************/
-
-typedef union ii_itte4_u {
-	u64 ii_itte4_regval;
-	struct {
-		u64 i_offset:5;
-		u64 i_rsvd_1:3;
-		u64 i_w_num:4;
-		u64 i_iosp:1;
-		u64 i_rsvd:51;
-	} ii_itte4_fld_s;
-} ii_itte4_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a SHub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the Shub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *									*
- ************************************************************************/
-
-typedef union ii_itte5_u {
-	u64 ii_itte5_regval;
-	struct {
-		u64 i_offset:5;
-		u64 i_rsvd_1:3;
-		u64 i_w_num:4;
-		u64 i_iosp:1;
-		u64 i_rsvd:51;
-	} ii_itte5_fld_s;
-} ii_itte5_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the Shub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *									*
- ************************************************************************/
-
-typedef union ii_itte6_u {
-	u64 ii_itte6_regval;
-	struct {
-		u64 i_offset:5;
-		u64 i_rsvd_1:3;
-		u64 i_w_num:4;
-		u64 i_iosp:1;
-		u64 i_rsvd:51;
-	} ii_itte6_fld_s;
-} ii_itte6_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are seven instances of translation table entry   *
- * registers. Each register maps a Shub Big Window to a 48-bit          *
- * address on Crosstalk.                                                *
- * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
- * number) are used to select one of these 7 registers. The Widget      *
- * number field is then derived from the W_NUM field for synthesizing   *
- * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
- * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
- * are padded with zeros. Although the maximum Crosstalk space          *
- * addressable by the Shub is thus the lower 16 GBytes per widget       *
- * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
- * space can be accessed.                                               *
- * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
- * Window number) are used to select one of these 7 registers. The      *
- * Widget number field is then derived from the W_NUM field for         *
- * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
- * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
- * field is used as Crosstalk[47], and remainder of the Crosstalk       *
- * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
- * Crosstalk space addressable by the SHub is thus the lower            *
- * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
- * of this space can be accessed.                                       *
- *									*
- ************************************************************************/
-
-typedef union ii_itte7_u {
-	u64 ii_itte7_regval;
-	struct {
-		u64 i_offset:5;
-		u64 i_rsvd_1:3;
-		u64 i_w_num:4;
-		u64 i_iosp:1;
-		u64 i_rsvd:51;
-	} ii_itte7_fld_s;
-} ii_itte7_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .    								*
- *									*
- ************************************************************************/
-
-typedef union ii_iprb0_u {
-	u64 ii_iprb0_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprb0_fld_s;
-} ii_iprb0_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .    								*
- *									*
- ************************************************************************/
-
-typedef union ii_iprb8_u {
-	u64 ii_iprb8_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprb8_fld_s;
-} ii_iprb8_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .    								*
- *									*
- ************************************************************************/
-
-typedef union ii_iprb9_u {
-	u64 ii_iprb9_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprb9_fld_s;
-} ii_iprb9_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.        *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- *									*
- *									*
- ************************************************************************/
-
-typedef union ii_iprba_u {
-	u64 ii_iprba_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprba_fld_s;
-} ii_iprba_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .    								*
- *									*
- ************************************************************************/
-
-typedef union ii_iprbb_u {
-	u64 ii_iprbb_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprbb_fld_s;
-} ii_iprbb_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .    								*
- *									*
- ************************************************************************/
-
-typedef union ii_iprbc_u {
-	u64 ii_iprbc_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprbc_fld_s;
-} ii_iprbc_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .    								*
- *									*
- ************************************************************************/
-
-typedef union ii_iprbd_u {
-	u64 ii_iprbd_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprbd_fld_s;
-} ii_iprbd_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of SHub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .    								*
- *									*
- ************************************************************************/
-
-typedef union ii_iprbe_u {
-	u64 ii_iprbe_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprbe_fld_s;
-} ii_iprbe_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 9 instances of this register, one per        *
- * actual widget in this implementation of Shub and Crossbow.           *
- * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
- * refers to Crossbow's internal space.                                 *
- * This register contains the state elements per widget that are        *
- * necessary to manage the PIO flow control on Crosstalk and on the     *
- * Router Network. See the PIO Flow Control chapter for a complete      *
- * description of this register                                         *
- * The SPUR_WR bit requires some explanation. When this register is     *
- * written, the new value of the C field is captured in an internal     *
- * register so the hardware can remember what the programmer wrote      *
- * into the credit counter. The SPUR_WR bit sets whenever the C field   *
- * increments above this stored value, which indicates that there       *
- * have been more responses received than requests sent. The SPUR_WR    *
- * bit cannot be cleared until a value is written to the IPRBx          *
- * register; the write will correct the C field and capture its new     *
- * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
- * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
- * .    								*
- *									*
- ************************************************************************/
-
-typedef union ii_iprbf_u {
-	u64 ii_iprbf_regval;
-	struct {
-		u64 i_c:8;
-		u64 i_na:14;
-		u64 i_rsvd_2:2;
-		u64 i_nb:14;
-		u64 i_rsvd_1:2;
-		u64 i_m:2;
-		u64 i_f:1;
-		u64 i_of_cnt:5;
-		u64 i_error:1;
-		u64 i_rd_to:1;
-		u64 i_spur_wr:1;
-		u64 i_spur_rd:1;
-		u64 i_rsvd:11;
-		u64 i_mult_err:1;
-	} ii_iprbe_fld_s;
-} ii_iprbf_u_t;
-
-/************************************************************************
- *									*
- *  This register specifies the timeout value to use for monitoring     *
- * Crosstalk credits which are used outbound to Crosstalk. An           *
- * internal counter called the Crosstalk Credit Timeout Counter         *
- * increments every 128 II clocks. The counter starts counting          *
- * anytime the credit count drops below a threshold, and resets to      *
- * zero (stops counting) anytime the credit count is at or above the    *
- * threshold. The threshold is 1 credit in direct connect mode and 2    *
- * in Crossbow connect mode. When the internal Crosstalk Credit         *
- * Timeout Counter reaches the value programmed in this register, a     *
- * Crosstalk Credit Timeout has occurred. The internal counter is not   *
- * readable from software, and stops counting at its maximum value,     *
- * so it cannot cause more than one interrupt.                          *
- *									*
- ************************************************************************/
-
-typedef union ii_ixcc_u {
-	u64 ii_ixcc_regval;
-	struct {
-		u64 i_time_out:26;
-		u64 i_rsvd:38;
-	} ii_ixcc_fld_s;
-} ii_ixcc_u_t;
-
-/************************************************************************
- *									*
- * Description:  This register qualifies all the PIO and DMA            *
- * operations launched from widget 0 towards the SHub. In               *
- * addition, it also qualifies accesses by the BTE streams.             *
- * The bits in each field of this register are cleared by the SHub      *
- * upon detection of an error which requires widget 0 or the BTE        *
- * streams to be terminated. Whether or not widget x has access         *
- * rights to this SHub is determined by an AND of the device            *
- * enable bit in the appropriate field of this register and bit 0 in    *
- * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
- * them. Incoming replies from Crosstalk are not subject to this        *
- * access control mechanism.                                            *
- *									*
- ************************************************************************/
-
-typedef union ii_imem_u {
-	u64 ii_imem_regval;
-	struct {
-		u64 i_w0_esd:1;
-		u64 i_rsvd_3:3;
-		u64 i_b0_esd:1;
-		u64 i_rsvd_2:3;
-		u64 i_b1_esd:1;
-		u64 i_rsvd_1:3;
-		u64 i_clr_precise:1;
-		u64 i_rsvd:51;
-	} ii_imem_fld_s;
-} ii_imem_u_t;
-
-/************************************************************************
- *									*
- * Description:  This register specifies the timeout value to use for   *
- * monitoring Crosstalk tail flits coming into the Shub in the          *
- * TAIL_TO field. An internal counter associated with this register     *
- * is incremented every 128 II internal clocks (7 bits). The counter    *
- * starts counting anytime a header micropacket is received and stops   *
- * counting (and resets to zero) any time a micropacket with a Tail     *
- * bit is received. Once the counter reaches the threshold value        *
- * programmed in this register, it generates an interrupt to the        *
- * processor that is programmed into the IIDSR. The counter saturates   *
- * (does not roll over) at its maximum value, so it cannot cause        *
- * another interrupt until after it is cleared.                         *
- * The register also contains the Read Response Timeout values. The     *
- * Prescalar is 23 bits, and counts II clocks. An internal counter      *
- * increments on every II clock and when it reaches the value in the    *
- * Prescalar field, all IPRTE registers with their valid bits set       *
- * have their Read Response timers bumped. Whenever any of them match   *
- * the value in the RRSP_TO field, a Read Response Timeout has          *
- * occurred, and error handling occurs as described in the Error        *
- * Handling section of this document.                                   *
- *									*
- ************************************************************************/
-
-typedef union ii_ixtt_u {
-	u64 ii_ixtt_regval;
-	struct {
-		u64 i_tail_to:26;
-		u64 i_rsvd_1:6;
-		u64 i_rrsp_ps:23;
-		u64 i_rrsp_to:5;
-		u64 i_rsvd:4;
-	} ii_ixtt_fld_s;
-} ii_ixtt_u_t;
-
-/************************************************************************
- *									*
- *  Writing a 1 to the fields of this register clears the appropriate   *
- * error bits in other areas of SHub. Note that when the                *
- * E_PRB_x bits are used to clear error bits in PRB registers,          *
- * SPUR_RD and SPUR_WR may persist, because they require additional     *
- * action to clear them. See the IPRBx and IXSS Register                *
- * specifications.                                                      *
- *									*
- ************************************************************************/
-
-typedef union ii_ieclr_u {
-	u64 ii_ieclr_regval;
-	struct {
-		u64 i_e_prb_0:1;
-		u64 i_rsvd:7;
-		u64 i_e_prb_8:1;
-		u64 i_e_prb_9:1;
-		u64 i_e_prb_a:1;
-		u64 i_e_prb_b:1;
-		u64 i_e_prb_c:1;
-		u64 i_e_prb_d:1;
-		u64 i_e_prb_e:1;
-		u64 i_e_prb_f:1;
-		u64 i_e_crazy:1;
-		u64 i_e_bte_0:1;
-		u64 i_e_bte_1:1;
-		u64 i_reserved_1:10;
-		u64 i_spur_rd_hdr:1;
-		u64 i_cam_intr_to:1;
-		u64 i_cam_overflow:1;
-		u64 i_cam_read_miss:1;
-		u64 i_ioq_rep_underflow:1;
-		u64 i_ioq_req_underflow:1;
-		u64 i_ioq_rep_overflow:1;
-		u64 i_ioq_req_overflow:1;
-		u64 i_iiq_rep_overflow:1;
-		u64 i_iiq_req_overflow:1;
-		u64 i_ii_xn_rep_cred_overflow:1;
-		u64 i_ii_xn_req_cred_overflow:1;
-		u64 i_ii_xn_invalid_cmd:1;
-		u64 i_xn_ii_invalid_cmd:1;
-		u64 i_reserved_2:21;
-	} ii_ieclr_fld_s;
-} ii_ieclr_u_t;
-
-/************************************************************************
- *									*
- *  This register controls both BTEs. SOFT_RESET is intended for        *
- * recovery after an error. COUNT controls the total number of CRBs     *
- * that both BTEs (combined) can use, which affects total BTE           *
- * bandwidth.                                                           *
- *									*
- ************************************************************************/
-
-typedef union ii_ibcr_u {
-	u64 ii_ibcr_regval;
-	struct {
-		u64 i_count:4;
-		u64 i_rsvd_1:4;
-		u64 i_soft_reset:1;
-		u64 i_rsvd:55;
-	} ii_ibcr_fld_s;
-} ii_ibcr_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the header of a spurious read response       *
- * received from Crosstalk. A spurious read response is defined as a    *
- * read response received by II from a widget for which (1) the SIDN    *
- * has a value between 1 and 7, inclusive (II never sends requests to   *
- * these widgets (2) there is no valid IPRTE register which             *
- * corresponds to the TNUM, or (3) the widget indicated in SIDN is      *
- * not the same as the widget recorded in the IPRTE register            *
- * referenced by the TNUM. If this condition is true, and if the        *
- * IXSS[VALID] bit is clear, then the header of the spurious read       *
- * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The    *
- * errant header is thereby captured, and no further spurious read      *
- * respones are captured until IXSS[VALID] is cleared by setting the    *
- * appropriate bit in IECLR. Every time a spurious read response is     *
- * detected, the SPUR_RD bit of the PRB corresponding to the incoming   *
- * message's SIDN field is set. This always happens, regardless of       *
- * whether a header is captured. The programmer should check            *
- * IXSM[SIDN] to determine which widget sent the spurious response,     *
- * because there may be more than one SPUR_RD bit set in the PRB        *
- * registers. The widget indicated by IXSM[SIDN] was the first          *
- * spurious read response to be received since the last time            *
- * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB      *
- * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
- * spurious messages from other widets which were detected after the    *
- * header was captured..                                                *
- *									*
- ************************************************************************/
-
-typedef union ii_ixsm_u {
-	u64 ii_ixsm_regval;
-	struct {
-		u64 i_byte_en:32;
-		u64 i_reserved:1;
-		u64 i_tag:3;
-		u64 i_alt_pactyp:4;
-		u64 i_bo:1;
-		u64 i_error:1;
-		u64 i_vbpm:1;
-		u64 i_gbr:1;
-		u64 i_ds:2;
-		u64 i_ct:1;
-		u64 i_tnum:5;
-		u64 i_pactyp:4;
-		u64 i_sidn:4;
-		u64 i_didn:4;
-	} ii_ixsm_fld_s;
-} ii_ixsm_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the sideband bits of a spurious read         *
- * response received from Crosstalk.                                    *
- *									*
- ************************************************************************/
-
-typedef union ii_ixss_u {
-	u64 ii_ixss_regval;
-	struct {
-		u64 i_sideband:8;
-		u64 i_rsvd:55;
-		u64 i_valid:1;
-	} ii_ixss_fld_s;
-} ii_ixss_u_t;
-
-/************************************************************************
- *									*
- *  This register enables software to access the II LLP's test port.    *
- * Refer to the LLP 2.5 documentation for an explanation of the test    *
- * port. Software can write to this register to program the values      *
- * for the control fields (TestErrCapture, TestClear, TestFlit,         *
- * TestMask and TestSeed). Similarly, software can read from this       *
- * register to obtain the values of the test port's status outputs      *
- * (TestCBerr, TestValid and TestData).                                 *
- *									*
- ************************************************************************/
-
-typedef union ii_ilct_u {
-	u64 ii_ilct_regval;
-	struct {
-		u64 i_test_seed:20;
-		u64 i_test_mask:8;
-		u64 i_test_data:20;
-		u64 i_test_valid:1;
-		u64 i_test_cberr:1;
-		u64 i_test_flit:3;
-		u64 i_test_clear:1;
-		u64 i_test_err_capture:1;
-		u64 i_rsvd:9;
-	} ii_ilct_fld_s;
-} ii_ilct_u_t;
-
-/************************************************************************
- *									*
- *  If the II detects an illegal incoming Duplonet packet (request or   *
- * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
- * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
- * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit,     *
- * and assigns a value to the ERR_TYPE field which indicates the        *
- * specific nature of the error. The II recognizes four different       *
- * types of errors: short request packets (ERR_TYPE==2), short reply    *
- * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long   *
- * reply packets (ERR_TYPE==5). The encodings for these types of        *
- * errors were chosen to be consistent with the same types of errors    *
- * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in    *
- * the LB unit). If the II detects an illegal incoming Duplonet         *
- * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
- * the OVERRUN bit to indicate that a subsequent error has happened,    *
- * and does nothing further.                                            *
- *									*
- ************************************************************************/
-
-typedef union ii_iieph1_u {
-	u64 ii_iieph1_regval;
-	struct {
-		u64 i_command:7;
-		u64 i_rsvd_5:1;
-		u64 i_suppl:14;
-		u64 i_rsvd_4:1;
-		u64 i_source:14;
-		u64 i_rsvd_3:1;
-		u64 i_err_type:4;
-		u64 i_rsvd_2:4;
-		u64 i_overrun:1;
-		u64 i_rsvd_1:3;
-		u64 i_valid:1;
-		u64 i_rsvd:13;
-	} ii_iieph1_fld_s;
-} ii_iieph1_u_t;
-
-/************************************************************************
- *									*
- *  This register holds the Address field from the header flit of an    *
- * incoming erroneous Duplonet packet, along with the tail bit which    *
- * accompanied this header flit. This register is essentially an        *
- * extension of IIEPH1. Two registers were necessary because the 64     *
- * bits available in only a single register were insufficient to        *
- * capture the entire header flit of an erroneous packet.               *
- *									*
- ************************************************************************/
-
-typedef union ii_iieph2_u {
-	u64 ii_iieph2_regval;
-	struct {
-		u64 i_rsvd_0:3;
-		u64 i_address:47;
-		u64 i_rsvd_1:10;
-		u64 i_tail:1;
-		u64 i_rsvd:3;
-	} ii_iieph2_fld_s;
-} ii_iieph2_u_t;
-
-/******************************/
-
-/************************************************************************
- *									*
- *  This register's value is a bit vector that guards access from SXBs  *
- * to local registers within the II as well as to external Crosstalk    *
- * widgets								*
- *									*
- ************************************************************************/
-
-typedef union ii_islapr_u {
-	u64 ii_islapr_regval;
-	struct {
-		u64 i_region:64;
-	} ii_islapr_fld_s;
-} ii_islapr_u_t;
-
-/************************************************************************
- *									*
- *  A write to this register of the 56-bit value "Pup+Bun" will cause	*
- * the bit in the ISLAPR register corresponding to the region of the	*
- * requestor to be set (access allowed).				(
- *									*
- ************************************************************************/
-
-typedef union ii_islapo_u {
-	u64 ii_islapo_regval;
-	struct {
-		u64 i_io_sbx_ovrride:56;
-		u64 i_rsvd:8;
-	} ii_islapo_fld_s;
-} ii_islapo_u_t;
-
-/************************************************************************
- *									*
- *  Determines how long the wrapper will wait aftr an interrupt is	*
- * initially issued from the II before it times out the outstanding	*
- * interrupt and drops it from the interrupt queue.			* 
- *									*
- ************************************************************************/
-
-typedef union ii_iwi_u {
-	u64 ii_iwi_regval;
-	struct {
-		u64 i_prescale:24;
-		u64 i_rsvd:8;
-		u64 i_timeout:8;
-		u64 i_rsvd1:8;
-		u64 i_intrpt_retry_period:8;
-		u64 i_rsvd2:8;
-	} ii_iwi_fld_s;
-} ii_iwi_u_t;
-
-/************************************************************************
- *									*
- *  Log errors which have occurred in the II wrapper. The errors are	*
- * cleared by writing to the IECLR register.				* 
- *									*
- ************************************************************************/
-
-typedef union ii_iwel_u {
-	u64 ii_iwel_regval;
-	struct {
-		u64 i_intr_timed_out:1;
-		u64 i_rsvd:7;
-		u64 i_cam_overflow:1;
-		u64 i_cam_read_miss:1;
-		u64 i_rsvd1:2;
-		u64 i_ioq_rep_underflow:1;
-		u64 i_ioq_req_underflow:1;
-		u64 i_ioq_rep_overflow:1;
-		u64 i_ioq_req_overflow:1;
-		u64 i_iiq_rep_overflow:1;
-		u64 i_iiq_req_overflow:1;
-		u64 i_rsvd2:6;
-		u64 i_ii_xn_rep_cred_over_under:1;
-		u64 i_ii_xn_req_cred_over_under:1;
-		u64 i_rsvd3:6;
-		u64 i_ii_xn_invalid_cmd:1;
-		u64 i_xn_ii_invalid_cmd:1;
-		u64 i_rsvd4:30;
-	} ii_iwel_fld_s;
-} ii_iwel_u_t;
-
-/************************************************************************
- *									*
- *  Controls the II wrapper.						* 
- *									*
- ************************************************************************/
-
-typedef union ii_iwc_u {
-	u64 ii_iwc_regval;
-	struct {
-		u64 i_dma_byte_swap:1;
-		u64 i_rsvd:3;
-		u64 i_cam_read_lines_reset:1;
-		u64 i_rsvd1:3;
-		u64 i_ii_xn_cred_over_under_log:1;
-		u64 i_rsvd2:19;
-		u64 i_xn_rep_iq_depth:5;
-		u64 i_rsvd3:3;
-		u64 i_xn_req_iq_depth:5;
-		u64 i_rsvd4:3;
-		u64 i_iiq_depth:6;
-		u64 i_rsvd5:12;
-		u64 i_force_rep_cred:1;
-		u64 i_force_req_cred:1;
-	} ii_iwc_fld_s;
-} ii_iwc_u_t;
-
-/************************************************************************
- *									*
- *  Status in the II wrapper.						* 
- *									*
- ************************************************************************/
-
-typedef union ii_iws_u {
-	u64 ii_iws_regval;
-	struct {
-		u64 i_xn_rep_iq_credits:5;
-		u64 i_rsvd:3;
-		u64 i_xn_req_iq_credits:5;
-		u64 i_rsvd1:51;
-	} ii_iws_fld_s;
-} ii_iws_u_t;
-
-/************************************************************************
- *									*
- *  Masks errors in the IWEL register.					*
- *									*
- ************************************************************************/
-
-typedef union ii_iweim_u {
-	u64 ii_iweim_regval;
-	struct {
-		u64 i_intr_timed_out:1;
-		u64 i_rsvd:7;
-		u64 i_cam_overflow:1;
-		u64 i_cam_read_miss:1;
-		u64 i_rsvd1:2;
-		u64 i_ioq_rep_underflow:1;
-		u64 i_ioq_req_underflow:1;
-		u64 i_ioq_rep_overflow:1;
-		u64 i_ioq_req_overflow:1;
-		u64 i_iiq_rep_overflow:1;
-		u64 i_iiq_req_overflow:1;
-		u64 i_rsvd2:6;
-		u64 i_ii_xn_rep_cred_overflow:1;
-		u64 i_ii_xn_req_cred_overflow:1;
-		u64 i_rsvd3:6;
-		u64 i_ii_xn_invalid_cmd:1;
-		u64 i_xn_ii_invalid_cmd:1;
-		u64 i_rsvd4:30;
-	} ii_iweim_fld_s;
-} ii_iweim_u_t;
-
-/************************************************************************
- *									*
- *  A write to this register causes a particular field in the           *
- * corresponding widget's PRB entry to be adjusted up or down by 1.     *
- * This counter should be used when recovering from error and reset     *
- * conditions. Note that software would be capable of causing           *
- * inadvertent overflow or underflow of these counters.                 *
- *									*
- ************************************************************************/
-
-typedef union ii_ipca_u {
-	u64 ii_ipca_regval;
-	struct {
-		u64 i_wid:4;
-		u64 i_adjust:1;
-		u64 i_rsvd_1:3;
-		u64 i_field:2;
-		u64 i_rsvd:54;
-	} ii_ipca_fld_s;
-} ii_ipca_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte0a_u {
-	u64 ii_iprte0a_regval;
-	struct {
-		u64 i_rsvd_1:54;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} ii_iprte0a_fld_s;
-} ii_iprte0a_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte1a_u {
-	u64 ii_iprte1a_regval;
-	struct {
-		u64 i_rsvd_1:54;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} ii_iprte1a_fld_s;
-} ii_iprte1a_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte2a_u {
-	u64 ii_iprte2a_regval;
-	struct {
-		u64 i_rsvd_1:54;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} ii_iprte2a_fld_s;
-} ii_iprte2a_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte3a_u {
-	u64 ii_iprte3a_regval;
-	struct {
-		u64 i_rsvd_1:54;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} ii_iprte3a_fld_s;
-} ii_iprte3a_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte4a_u {
-	u64 ii_iprte4a_regval;
-	struct {
-		u64 i_rsvd_1:54;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} ii_iprte4a_fld_s;
-} ii_iprte4a_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte5a_u {
-	u64 ii_iprte5a_regval;
-	struct {
-		u64 i_rsvd_1:54;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} ii_iprte5a_fld_s;
-} ii_iprte5a_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte6a_u {
-	u64 ii_iprte6a_regval;
-	struct {
-		u64 i_rsvd_1:54;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} ii_iprte6a_fld_s;
-} ii_iprte6a_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte7a_u {
-	u64 ii_iprte7a_regval;
-	struct {
-		u64 i_rsvd_1:54;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} ii_iprtea7_fld_s;
-} ii_iprte7a_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte0b_u {
-	u64 ii_iprte0b_regval;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_address:47;
-		u64 i_init:3;
-		u64 i_source:11;
-	} ii_iprte0b_fld_s;
-} ii_iprte0b_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte1b_u {
-	u64 ii_iprte1b_regval;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_address:47;
-		u64 i_init:3;
-		u64 i_source:11;
-	} ii_iprte1b_fld_s;
-} ii_iprte1b_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte2b_u {
-	u64 ii_iprte2b_regval;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_address:47;
-		u64 i_init:3;
-		u64 i_source:11;
-	} ii_iprte2b_fld_s;
-} ii_iprte2b_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte3b_u {
-	u64 ii_iprte3b_regval;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_address:47;
-		u64 i_init:3;
-		u64 i_source:11;
-	} ii_iprte3b_fld_s;
-} ii_iprte3b_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte4b_u {
-	u64 ii_iprte4b_regval;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_address:47;
-		u64 i_init:3;
-		u64 i_source:11;
-	} ii_iprte4b_fld_s;
-} ii_iprte4b_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte5b_u {
-	u64 ii_iprte5b_regval;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_address:47;
-		u64 i_init:3;
-		u64 i_source:11;
-	} ii_iprte5b_fld_s;
-} ii_iprte5b_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte6b_u {
-	u64 ii_iprte6b_regval;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_address:47;
-		u64 i_init:3;
-		u64 i_source:11;
-
-	} ii_iprte6b_fld_s;
-} ii_iprte6b_u_t;
-
-/************************************************************************
- *									*
- *  There are 8 instances of this register. This register contains      *
- * the information that the II has to remember once it has launched a   *
- * PIO Read operation. The contents are used to form the correct        *
- * Router Network packet and direct the Crosstalk reply to the          *
- * appropriate processor.                                               *
- *									*
- ************************************************************************/
-
-typedef union ii_iprte7b_u {
-	u64 ii_iprte7b_regval;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_address:47;
-		u64 i_init:3;
-		u64 i_source:11;
-	} ii_iprte7b_fld_s;
-} ii_iprte7b_u_t;
-
-/************************************************************************
- *									*
- * Description:  SHub II contains a feature which did not exist in      *
- * the Hub which automatically cleans up after a Read Response          *
- * timeout, including deallocation of the IPRTE and recovery of IBuf    *
- * space. The inclusion of this register in SHub is for backward        *
- * compatibility                                                        *
- * A write to this register causes an entry from the table of           *
- * outstanding PIO Read Requests to be freed and returned to the        *
- * stack of free entries. This register is used in handling the         *
- * timeout errors that result in a PIO Reply never returning from       *
- * Crosstalk.                                                           *
- * Note that this register does not affect the contents of the IPRTE    *
- * registers. The Valid bits in those registers have to be              *
- * specifically turned off by software.                                 *
- *									*
- ************************************************************************/
-
-typedef union ii_ipdr_u {
-	u64 ii_ipdr_regval;
-	struct {
-		u64 i_te:3;
-		u64 i_rsvd_1:1;
-		u64 i_pnd:1;
-		u64 i_init_rpcnt:1;
-		u64 i_rsvd:58;
-	} ii_ipdr_fld_s;
-} ii_ipdr_u_t;
-
-/************************************************************************
- *									*
- *  A write to this register causes a CRB entry to be returned to the   *
- * queue of free CRBs. The entry should have previously been cleared    *
- * (mark bit) via backdoor access to the pertinent CRB entry. This      *
- * register is used in the last step of handling the errors that are    *
- * captured and marked in CRB entries.  Briefly: 1) first error for     *
- * DMA write from a particular device, and first error for a            *
- * particular BTE stream, lead to a marked CRB entry, and processor     *
- * interrupt, 2) software reads the error information captured in the   *
- * CRB entry, and presumably takes some corrective action, 3)           *
- * software clears the mark bit, and finally 4) software writes to      *
- * the ICDR register to return the CRB entry to the list of free CRB    *
- * entries.                                                             *
- *									*
- ************************************************************************/
-
-typedef union ii_icdr_u {
-	u64 ii_icdr_regval;
-	struct {
-		u64 i_crb_num:4;
-		u64 i_pnd:1;
-		u64 i_rsvd:59;
-	} ii_icdr_fld_s;
-} ii_icdr_u_t;
-
-/************************************************************************
- *									*
- *  This register provides debug access to two FIFOs inside of II.      *
- * Both IOQ_MAX* fields of this register contain the instantaneous      *
- * depth (in units of the number of available entries) of the           *
- * associated IOQ FIFO.  A read of this register will return the        *
- * number of free entries on each FIFO at the time of the read.  So     *
- * when a FIFO is idle, the associated field contains the maximum       *
- * depth of the FIFO.  This register is writable for debug reasons      *
- * and is intended to be written with the maximum desired FIFO depth    *
- * while the FIFO is idle. Software must assure that II is idle when    *
- * this register is written. If there are any active entries in any     *
- * of these FIFOs when this register is written, the results are        *
- * undefined.                                                           *
- *									*
- ************************************************************************/
-
-typedef union ii_ifdr_u {
-	u64 ii_ifdr_regval;
-	struct {
-		u64 i_ioq_max_rq:7;
-		u64 i_set_ioq_rq:1;
-		u64 i_ioq_max_rp:7;
-		u64 i_set_ioq_rp:1;
-		u64 i_rsvd:48;
-	} ii_ifdr_fld_s;
-} ii_ifdr_u_t;
-
-/************************************************************************
- *									*
- *  This register allows the II to become sluggish in removing          *
- * messages from its inbound queue (IIQ). This will cause messages to   *
- * back up in either virtual channel. Disabling the "molasses" mode     *
- * subsequently allows the II to be tested under stress. In the         *
- * sluggish ("Molasses") mode, the localized effects of congestion      *
- * can be observed.                                                     *
- *									*
- ************************************************************************/
-
-typedef union ii_iiap_u {
-	u64 ii_iiap_regval;
-	struct {
-		u64 i_rq_mls:6;
-		u64 i_rsvd_1:2;
-		u64 i_rp_mls:6;
-		u64 i_rsvd:50;
-	} ii_iiap_fld_s;
-} ii_iiap_u_t;
-
-/************************************************************************
- *									*
- *  This register allows several parameters of CRB operation to be      *
- * set. Note that writing to this register can have catastrophic side   *
- * effects, if the CRB is not quiescent, i.e. if the CRB is             *
- * processing protocol messages when the write occurs.                  *
- *									*
- ************************************************************************/
-
-typedef union ii_icmr_u {
-	u64 ii_icmr_regval;
-	struct {
-		u64 i_sp_msg:1;
-		u64 i_rd_hdr:1;
-		u64 i_rsvd_4:2;
-		u64 i_c_cnt:4;
-		u64 i_rsvd_3:4;
-		u64 i_clr_rqpd:1;
-		u64 i_clr_rppd:1;
-		u64 i_rsvd_2:2;
-		u64 i_fc_cnt:4;
-		u64 i_crb_vld:15;
-		u64 i_crb_mark:15;
-		u64 i_rsvd_1:2;
-		u64 i_precise:1;
-		u64 i_rsvd:11;
-	} ii_icmr_fld_s;
-} ii_icmr_u_t;
-
-/************************************************************************
- *									*
- *  This register allows control of the table portion of the CRB        *
- * logic via software. Control operations from this register have       *
- * priority over all incoming Crosstalk or BTE requests.                *
- *									*
- ************************************************************************/
-
-typedef union ii_iccr_u {
-	u64 ii_iccr_regval;
-	struct {
-		u64 i_crb_num:4;
-		u64 i_rsvd_1:4;
-		u64 i_cmd:8;
-		u64 i_pending:1;
-		u64 i_rsvd:47;
-	} ii_iccr_fld_s;
-} ii_iccr_u_t;
-
-/************************************************************************
- *									*
- *  This register allows the maximum timeout value to be programmed.    *
- *									*
- ************************************************************************/
-
-typedef union ii_icto_u {
-	u64 ii_icto_regval;
-	struct {
-		u64 i_timeout:8;
-		u64 i_rsvd:56;
-	} ii_icto_fld_s;
-} ii_icto_u_t;
-
-/************************************************************************
- *									*
- *  This register allows the timeout prescalar to be programmed. An     *
- * internal counter is associated with this register. When the          *
- * internal counter reaches the value of the PRESCALE field, the        *
- * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
- * field). The internal counter resets to zero, and then continues      *
- * counting.                                                            *
- *									*
- ************************************************************************/
-
-typedef union ii_ictp_u {
-	u64 ii_ictp_regval;
-	struct {
-		u64 i_prescale:24;
-		u64 i_rsvd:40;
-	} ii_ictp_fld_s;
-} ii_ictp_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- * The CRB Entry registers can be conceptualized as rows and columns    *
- * (illustrated in the table above). Each row contains the 4            *
- * registers required for a single CRB Entry. The first doubleword      *
- * (column) for each entry is labeled A, and the second doubleword      *
- * (higher address) is labeled B, the third doubleword is labeled C,    *
- * the fourth doubleword is labeled D and the fifth doubleword is       *
- * labeled E. All CRB entries have their addresses on a quarter         *
- * cacheline aligned boundary.                   *
- * Upon reset, only the following fields are initialized: valid         *
- * (VLD), priority count, timeout, timeout valid, and context valid.    *
- * All other bits should be cleared by software before use (after       *
- * recovering any potential error state from before the reset).         *
- * The following four tables summarize the format for the four          *
- * registers that are used for each ICRB# Entry.                        *
- *									*
- ************************************************************************/
-
-typedef union ii_icrb0_a_u {
-	u64 ii_icrb0_a_regval;
-	struct {
-		u64 ia_iow:1;
-		u64 ia_vld:1;
-		u64 ia_addr:47;
-		u64 ia_tnum:5;
-		u64 ia_sidn:4;
-		u64 ia_rsvd:6;
-	} ii_icrb0_a_fld_s;
-} ii_icrb0_a_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- *									*
- ************************************************************************/
-
-typedef union ii_icrb0_b_u {
-	u64 ii_icrb0_b_regval;
-	struct {
-		u64 ib_xt_err:1;
-		u64 ib_mark:1;
-		u64 ib_ln_uce:1;
-		u64 ib_errcode:3;
-		u64 ib_error:1;
-		u64 ib_stall__bte_1:1;
-		u64 ib_stall__bte_0:1;
-		u64 ib_stall__intr:1;
-		u64 ib_stall_ib:1;
-		u64 ib_intvn:1;
-		u64 ib_wb:1;
-		u64 ib_hold:1;
-		u64 ib_ack:1;
-		u64 ib_resp:1;
-		u64 ib_ack_cnt:11;
-		u64 ib_rsvd:7;
-		u64 ib_exc:5;
-		u64 ib_init:3;
-		u64 ib_imsg:8;
-		u64 ib_imsgtype:2;
-		u64 ib_use_old:1;
-		u64 ib_rsvd_1:11;
-	} ii_icrb0_b_fld_s;
-} ii_icrb0_b_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- *									*
- ************************************************************************/
-
-typedef union ii_icrb0_c_u {
-	u64 ii_icrb0_c_regval;
-	struct {
-		u64 ic_source:15;
-		u64 ic_size:2;
-		u64 ic_ct:1;
-		u64 ic_bte_num:1;
-		u64 ic_gbr:1;
-		u64 ic_resprqd:1;
-		u64 ic_bo:1;
-		u64 ic_suppl:15;
-		u64 ic_rsvd:27;
-	} ii_icrb0_c_fld_s;
-} ii_icrb0_c_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- *									*
- ************************************************************************/
-
-typedef union ii_icrb0_d_u {
-	u64 ii_icrb0_d_regval;
-	struct {
-		u64 id_pa_be:43;
-		u64 id_bte_op:1;
-		u64 id_pr_psc:4;
-		u64 id_pr_cnt:4;
-		u64 id_sleep:1;
-		u64 id_rsvd:11;
-	} ii_icrb0_d_fld_s;
-} ii_icrb0_d_u_t;
-
-/************************************************************************
- *									*
- * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
- * used for Crosstalk operations (both cacheline and partial            *
- * operations) or BTE/IO. Because the CRB entries are very wide, five   *
- * registers (_A to _E) are required to read and write each entry.      *
- *									*
- ************************************************************************/
-
-typedef union ii_icrb0_e_u {
-	u64 ii_icrb0_e_regval;
-	struct {
-		u64 ie_timeout:8;
-		u64 ie_context:15;
-		u64 ie_rsvd:1;
-		u64 ie_tvld:1;
-		u64 ie_cvld:1;
-		u64 ie_rsvd_0:38;
-	} ii_icrb0_e_fld_s;
-} ii_icrb0_e_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the lower 64 bits of the header of the       *
- * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
- * register is set.                                                     *
- *									*
- ************************************************************************/
-
-typedef union ii_icsml_u {
-	u64 ii_icsml_regval;
-	struct {
-		u64 i_tt_addr:47;
-		u64 i_newsuppl_ex:14;
-		u64 i_reserved:2;
-		u64 i_overflow:1;
-	} ii_icsml_fld_s;
-} ii_icsml_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the middle 64 bits of the header of the      *
- * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
- * register is set.                                                     *
- *									*
- ************************************************************************/
-
-typedef union ii_icsmm_u {
-	u64 ii_icsmm_regval;
-	struct {
-		u64 i_tt_ack_cnt:11;
-		u64 i_reserved:53;
-	} ii_icsmm_fld_s;
-} ii_icsmm_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the microscopic state, all the inputs to     *
- * the protocol table, captured with the spurious message. Valid when   *
- * the SP_MSG bit in the ICMR register is set.                          *
- *									*
- ************************************************************************/
-
-typedef union ii_icsmh_u {
-	u64 ii_icsmh_regval;
-	struct {
-		u64 i_tt_vld:1;
-		u64 i_xerr:1;
-		u64 i_ft_cwact_o:1;
-		u64 i_ft_wact_o:1;
-		u64 i_ft_active_o:1;
-		u64 i_sync:1;
-		u64 i_mnusg:1;
-		u64 i_mnusz:1;
-		u64 i_plusz:1;
-		u64 i_plusg:1;
-		u64 i_tt_exc:5;
-		u64 i_tt_wb:1;
-		u64 i_tt_hold:1;
-		u64 i_tt_ack:1;
-		u64 i_tt_resp:1;
-		u64 i_tt_intvn:1;
-		u64 i_g_stall_bte1:1;
-		u64 i_g_stall_bte0:1;
-		u64 i_g_stall_il:1;
-		u64 i_g_stall_ib:1;
-		u64 i_tt_imsg:8;
-		u64 i_tt_imsgtype:2;
-		u64 i_tt_use_old:1;
-		u64 i_tt_respreqd:1;
-		u64 i_tt_bte_num:1;
-		u64 i_cbn:1;
-		u64 i_match:1;
-		u64 i_rpcnt_lt_34:1;
-		u64 i_rpcnt_ge_34:1;
-		u64 i_rpcnt_lt_18:1;
-		u64 i_rpcnt_ge_18:1;
-		u64 i_rpcnt_lt_2:1;
-		u64 i_rpcnt_ge_2:1;
-		u64 i_rqcnt_lt_18:1;
-		u64 i_rqcnt_ge_18:1;
-		u64 i_rqcnt_lt_2:1;
-		u64 i_rqcnt_ge_2:1;
-		u64 i_tt_device:7;
-		u64 i_tt_init:3;
-		u64 i_reserved:5;
-	} ii_icsmh_fld_s;
-} ii_icsmh_u_t;
-
-/************************************************************************
- *									*
- *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
- * II core and a 3-bit selection signal to the fsbclk domain in the II  *
- * wrapper.                                                             *
- *									*
- ************************************************************************/
-
-typedef union ii_idbss_u {
-	u64 ii_idbss_regval;
-	struct {
-		u64 i_iioclk_core_submenu:3;
-		u64 i_rsvd:5;
-		u64 i_fsbclk_wrapper_submenu:3;
-		u64 i_rsvd_1:5;
-		u64 i_iioclk_menu:5;
-		u64 i_rsvd_2:43;
-	} ii_idbss_fld_s;
-} ii_idbss_u_t;
-
-/************************************************************************
- *									*
- * Description:  This register is used to set up the length for a       *
- * transfer and then to monitor the progress of that transfer. This     *
- * register needs to be initialized before a transfer is started. A     *
- * legitimate write to this register will set the Busy bit, clear the   *
- * Error bit, and initialize the length to the value desired.           *
- * While the transfer is in progress, hardware will decrement the       *
- * length field with each successful block that is copied. Once the     *
- * transfer completes, hardware will clear the Busy bit. The length     *
- * field will also contain the number of cache lines left to be         *
- * transferred.                                                         *
- *									*
- ************************************************************************/
-
-typedef union ii_ibls0_u {
-	u64 ii_ibls0_regval;
-	struct {
-		u64 i_length:16;
-		u64 i_error:1;
-		u64 i_rsvd_1:3;
-		u64 i_busy:1;
-		u64 i_rsvd:43;
-	} ii_ibls0_fld_s;
-} ii_ibls0_u_t;
-
-/************************************************************************
- *									*
- *  This register should be loaded before a transfer is started. The    *
- * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
- * address as described in Section 1.3, Figure2 and Figure3. Since      *
- * the bottom 7 bits of the address are always taken to be zero, BTE    *
- * transfers are always cacheline-aligned.                              *
- *									*
- ************************************************************************/
-
-typedef union ii_ibsa0_u {
-	u64 ii_ibsa0_regval;
-	struct {
-		u64 i_rsvd_1:7;
-		u64 i_addr:42;
-		u64 i_rsvd:15;
-	} ii_ibsa0_fld_s;
-} ii_ibsa0_u_t;
-
-/************************************************************************
- *									*
- *  This register should be loaded before a transfer is started. The    *
- * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
- * address as described in Section 1.3, Figure2 and Figure3. Since      *
- * the bottom 7 bits of the address are always taken to be zero, BTE    *
- * transfers are always cacheline-aligned.                              *
- *									*
- ************************************************************************/
-
-typedef union ii_ibda0_u {
-	u64 ii_ibda0_regval;
-	struct {
-		u64 i_rsvd_1:7;
-		u64 i_addr:42;
-		u64 i_rsvd:15;
-	} ii_ibda0_fld_s;
-} ii_ibda0_u_t;
-
-/************************************************************************
- *									*
- *  Writing to this register sets up the attributes of the transfer     *
- * and initiates the transfer operation. Reading this register has      *
- * the side effect of terminating any transfer in progress. Note:       *
- * stopping a transfer midstream could have an adverse impact on the    *
- * other BTE. If a BTE stream has to be stopped (due to error           *
- * handling for example), both BTE streams should be stopped and        *
- * their transfers discarded.                                           *
- *									*
- ************************************************************************/
-
-typedef union ii_ibct0_u {
-	u64 ii_ibct0_regval;
-	struct {
-		u64 i_zerofill:1;
-		u64 i_rsvd_2:3;
-		u64 i_notify:1;
-		u64 i_rsvd_1:3;
-		u64 i_poison:1;
-		u64 i_rsvd:55;
-	} ii_ibct0_fld_s;
-} ii_ibct0_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the address to which the WINV is sent.       *
- * This address has to be cache line aligned.                           *
- *									*
- ************************************************************************/
-
-typedef union ii_ibna0_u {
-	u64 ii_ibna0_regval;
-	struct {
-		u64 i_rsvd_1:7;
-		u64 i_addr:42;
-		u64 i_rsvd:15;
-	} ii_ibna0_fld_s;
-} ii_ibna0_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the programmable level as well as the node   *
- * ID and PI unit of the processor to which the interrupt will be       *
- * sent.								*
- *									*
- ************************************************************************/
-
-typedef union ii_ibia0_u {
-	u64 ii_ibia0_regval;
-	struct {
-		u64 i_rsvd_2:1;
-		u64 i_node_id:11;
-		u64 i_rsvd_1:4;
-		u64 i_level:7;
-		u64 i_rsvd:41;
-	} ii_ibia0_fld_s;
-} ii_ibia0_u_t;
-
-/************************************************************************
- *									*
- * Description:  This register is used to set up the length for a       *
- * transfer and then to monitor the progress of that transfer. This     *
- * register needs to be initialized before a transfer is started. A     *
- * legitimate write to this register will set the Busy bit, clear the   *
- * Error bit, and initialize the length to the value desired.           *
- * While the transfer is in progress, hardware will decrement the       *
- * length field with each successful block that is copied. Once the     *
- * transfer completes, hardware will clear the Busy bit. The length     *
- * field will also contain the number of cache lines left to be         *
- * transferred.                                                         *
- *									*
- ************************************************************************/
-
-typedef union ii_ibls1_u {
-	u64 ii_ibls1_regval;
-	struct {
-		u64 i_length:16;
-		u64 i_error:1;
-		u64 i_rsvd_1:3;
-		u64 i_busy:1;
-		u64 i_rsvd:43;
-	} ii_ibls1_fld_s;
-} ii_ibls1_u_t;
-
-/************************************************************************
- *									*
- *  This register should be loaded before a transfer is started. The    *
- * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
- * address as described in Section 1.3, Figure2 and Figure3. Since      *
- * the bottom 7 bits of the address are always taken to be zero, BTE    *
- * transfers are always cacheline-aligned.                              *
- *									*
- ************************************************************************/
-
-typedef union ii_ibsa1_u {
-	u64 ii_ibsa1_regval;
-	struct {
-		u64 i_rsvd_1:7;
-		u64 i_addr:33;
-		u64 i_rsvd:24;
-	} ii_ibsa1_fld_s;
-} ii_ibsa1_u_t;
-
-/************************************************************************
- *									*
- *  This register should be loaded before a transfer is started. The    *
- * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
- * address as described in Section 1.3, Figure2 and Figure3. Since      *
- * the bottom 7 bits of the address are always taken to be zero, BTE    *
- * transfers are always cacheline-aligned.                              *
- *									*
- ************************************************************************/
-
-typedef union ii_ibda1_u {
-	u64 ii_ibda1_regval;
-	struct {
-		u64 i_rsvd_1:7;
-		u64 i_addr:33;
-		u64 i_rsvd:24;
-	} ii_ibda1_fld_s;
-} ii_ibda1_u_t;
-
-/************************************************************************
- *									*
- *  Writing to this register sets up the attributes of the transfer     *
- * and initiates the transfer operation. Reading this register has      *
- * the side effect of terminating any transfer in progress. Note:       *
- * stopping a transfer midstream could have an adverse impact on the    *
- * other BTE. If a BTE stream has to be stopped (due to error           *
- * handling for example), both BTE streams should be stopped and        *
- * their transfers discarded.                                           *
- *									*
- ************************************************************************/
-
-typedef union ii_ibct1_u {
-	u64 ii_ibct1_regval;
-	struct {
-		u64 i_zerofill:1;
-		u64 i_rsvd_2:3;
-		u64 i_notify:1;
-		u64 i_rsvd_1:3;
-		u64 i_poison:1;
-		u64 i_rsvd:55;
-	} ii_ibct1_fld_s;
-} ii_ibct1_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the address to which the WINV is sent.       *
- * This address has to be cache line aligned.                           *
- *									*
- ************************************************************************/
-
-typedef union ii_ibna1_u {
-	u64 ii_ibna1_regval;
-	struct {
-		u64 i_rsvd_1:7;
-		u64 i_addr:33;
-		u64 i_rsvd:24;
-	} ii_ibna1_fld_s;
-} ii_ibna1_u_t;
-
-/************************************************************************
- *									*
- *  This register contains the programmable level as well as the node   *
- * ID and PI unit of the processor to which the interrupt will be       *
- * sent.								*
- *									*
- ************************************************************************/
-
-typedef union ii_ibia1_u {
-	u64 ii_ibia1_regval;
-	struct {
-		u64 i_pi_id:1;
-		u64 i_node_id:8;
-		u64 i_rsvd_1:7;
-		u64 i_level:7;
-		u64 i_rsvd:41;
-	} ii_ibia1_fld_s;
-} ii_ibia1_u_t;
-
-/************************************************************************
- *									*
- *  This register defines the resources that feed information into      *
- * the two performance counters located in the IO Performance           *
- * Profiling Register. There are 17 different quantities that can be    *
- * measured. Given these 17 different options, the two performance      *
- * counters have 15 of them in common; menu selections 0 through 0xE    *
- * are identical for each performance counter. As for the other two     *
- * options, one is available from one performance counter and the       *
- * other is available from the other performance counter. Hence, the    *
- * II supports all 17*16=272 possible combinations of quantities to     *
- * measure.                                                             *
- *									*
- ************************************************************************/
-
-typedef union ii_ipcr_u {
-	u64 ii_ipcr_regval;
-	struct {
-		u64 i_ippr0_c:4;
-		u64 i_ippr1_c:4;
-		u64 i_icct:8;
-		u64 i_rsvd:48;
-	} ii_ipcr_fld_s;
-} ii_ipcr_u_t;
-
-/************************************************************************
- *									*
- *									*
- *									*
- ************************************************************************/
-
-typedef union ii_ippr_u {
-	u64 ii_ippr_regval;
-	struct {
-		u64 i_ippr0:32;
-		u64 i_ippr1:32;
-	} ii_ippr_fld_s;
-} ii_ippr_u_t;
-
-/************************************************************************
- *									*
- * The following defines which were not formed into structures are	*
- * probably identical to another register, and the name of the		*
- * register is provided against each of these registers. This		*
- * information needs to be checked carefully				*
- *									*
- *		IIO_ICRB1_A		IIO_ICRB0_A			*
- *		IIO_ICRB1_B		IIO_ICRB0_B			*
- *		IIO_ICRB1_C		IIO_ICRB0_C			*
- *		IIO_ICRB1_D		IIO_ICRB0_D			*
- *		IIO_ICRB1_E		IIO_ICRB0_E			*
- *		IIO_ICRB2_A		IIO_ICRB0_A			*
- *		IIO_ICRB2_B		IIO_ICRB0_B			*
- *		IIO_ICRB2_C		IIO_ICRB0_C			*
- *		IIO_ICRB2_D		IIO_ICRB0_D			*
- *		IIO_ICRB2_E		IIO_ICRB0_E			*
- *		IIO_ICRB3_A		IIO_ICRB0_A			*
- *		IIO_ICRB3_B		IIO_ICRB0_B			*
- *		IIO_ICRB3_C		IIO_ICRB0_C			*
- *		IIO_ICRB3_D		IIO_ICRB0_D			*
- *		IIO_ICRB3_E		IIO_ICRB0_E			*
- *		IIO_ICRB4_A		IIO_ICRB0_A			*
- *		IIO_ICRB4_B		IIO_ICRB0_B			*
- *		IIO_ICRB4_C		IIO_ICRB0_C			*
- *		IIO_ICRB4_D		IIO_ICRB0_D			*
- *		IIO_ICRB4_E		IIO_ICRB0_E			*
- *		IIO_ICRB5_A		IIO_ICRB0_A			*
- *		IIO_ICRB5_B		IIO_ICRB0_B			*
- *		IIO_ICRB5_C		IIO_ICRB0_C			*
- *		IIO_ICRB5_D		IIO_ICRB0_D			*
- *		IIO_ICRB5_E		IIO_ICRB0_E			*
- *		IIO_ICRB6_A		IIO_ICRB0_A			*
- *		IIO_ICRB6_B		IIO_ICRB0_B			*
- *		IIO_ICRB6_C		IIO_ICRB0_C			*
- *		IIO_ICRB6_D		IIO_ICRB0_D			*
- *		IIO_ICRB6_E		IIO_ICRB0_E			*
- *		IIO_ICRB7_A		IIO_ICRB0_A			*
- *		IIO_ICRB7_B		IIO_ICRB0_B			*
- *		IIO_ICRB7_C		IIO_ICRB0_C			*
- *		IIO_ICRB7_D		IIO_ICRB0_D			*
- *		IIO_ICRB7_E		IIO_ICRB0_E			*
- *		IIO_ICRB8_A		IIO_ICRB0_A			*
- *		IIO_ICRB8_B		IIO_ICRB0_B			*
- *		IIO_ICRB8_C		IIO_ICRB0_C			*
- *		IIO_ICRB8_D		IIO_ICRB0_D			*
- *		IIO_ICRB8_E		IIO_ICRB0_E			*
- *		IIO_ICRB9_A		IIO_ICRB0_A			*
- *		IIO_ICRB9_B		IIO_ICRB0_B			*
- *		IIO_ICRB9_C		IIO_ICRB0_C			*
- *		IIO_ICRB9_D		IIO_ICRB0_D			*
- *		IIO_ICRB9_E		IIO_ICRB0_E			*
- *		IIO_ICRBA_A		IIO_ICRB0_A			*
- *		IIO_ICRBA_B		IIO_ICRB0_B			*
- *		IIO_ICRBA_C		IIO_ICRB0_C			*
- *		IIO_ICRBA_D		IIO_ICRB0_D			*
- *		IIO_ICRBA_E		IIO_ICRB0_E			*
- *		IIO_ICRBB_A		IIO_ICRB0_A			*
- *		IIO_ICRBB_B		IIO_ICRB0_B			*
- *		IIO_ICRBB_C		IIO_ICRB0_C			*
- *		IIO_ICRBB_D		IIO_ICRB0_D			*
- *		IIO_ICRBB_E		IIO_ICRB0_E			*
- *		IIO_ICRBC_A		IIO_ICRB0_A			*
- *		IIO_ICRBC_B		IIO_ICRB0_B			*
- *		IIO_ICRBC_C		IIO_ICRB0_C			*
- *		IIO_ICRBC_D		IIO_ICRB0_D			*
- *		IIO_ICRBC_E		IIO_ICRB0_E			*
- *		IIO_ICRBD_A		IIO_ICRB0_A			*
- *		IIO_ICRBD_B		IIO_ICRB0_B			*
- *		IIO_ICRBD_C		IIO_ICRB0_C			*
- *		IIO_ICRBD_D		IIO_ICRB0_D			*
- *		IIO_ICRBD_E		IIO_ICRB0_E			*
- *		IIO_ICRBE_A		IIO_ICRB0_A			*
- *		IIO_ICRBE_B		IIO_ICRB0_B			*
- *		IIO_ICRBE_C		IIO_ICRB0_C			*
- *		IIO_ICRBE_D		IIO_ICRB0_D			*
- *		IIO_ICRBE_E		IIO_ICRB0_E			*
- *									*
- ************************************************************************/
-
-/*
- * Slightly friendlier names for some common registers.
- */
-#define IIO_WIDGET              IIO_WID		/* Widget identification */
-#define IIO_WIDGET_STAT         IIO_WSTAT	/* Widget status register */
-#define IIO_WIDGET_CTRL         IIO_WCR		/* Widget control register */
-#define IIO_PROTECT             IIO_ILAPR	/* IO interface protection */
-#define IIO_PROTECT_OVRRD       IIO_ILAPO	/* IO protect override */
-#define IIO_OUTWIDGET_ACCESS    IIO_IOWA	/* Outbound widget access */
-#define IIO_INWIDGET_ACCESS     IIO_IIWA	/* Inbound widget access */
-#define IIO_INDEV_ERR_MASK      IIO_IIDEM	/* Inbound device error mask */
-#define IIO_LLP_CSR             IIO_ILCSR	/* LLP control and status */
-#define IIO_LLP_LOG             IIO_ILLR	/* LLP log */
-#define IIO_XTALKCC_TOUT        IIO_IXCC	/* Xtalk credit count timeout */
-#define IIO_XTALKTT_TOUT        IIO_IXTT	/* Xtalk tail timeout */
-#define IIO_IO_ERR_CLR          IIO_IECLR	/* IO error clear */
-#define IIO_IGFX_0 		IIO_IGFX0
-#define IIO_IGFX_1 		IIO_IGFX1
-#define IIO_IBCT_0		IIO_IBCT0
-#define IIO_IBCT_1		IIO_IBCT1
-#define IIO_IBLS_0		IIO_IBLS0
-#define IIO_IBLS_1		IIO_IBLS1
-#define IIO_IBSA_0		IIO_IBSA0
-#define IIO_IBSA_1		IIO_IBSA1
-#define IIO_IBDA_0		IIO_IBDA0
-#define IIO_IBDA_1		IIO_IBDA1
-#define IIO_IBNA_0		IIO_IBNA0
-#define IIO_IBNA_1		IIO_IBNA1
-#define IIO_IBIA_0		IIO_IBIA0
-#define IIO_IBIA_1		IIO_IBIA1
-#define IIO_IOPRB_0		IIO_IPRB0
-
-#define IIO_PRTE_A(_x)		(IIO_IPRTE0_A + (8 * (_x)))
-#define IIO_PRTE_B(_x)		(IIO_IPRTE0_B + (8 * (_x)))
-#define IIO_NUM_PRTES		8	/* Total number of PRB table entries */
-#define IIO_WIDPRTE_A(x)	IIO_PRTE_A(((x) - 8))	/* widget ID to its PRTE num */
-#define IIO_WIDPRTE_B(x)	IIO_PRTE_B(((x) - 8))	/* widget ID to its PRTE num */
-
-#define IIO_NUM_IPRBS 		9
-
-#define IIO_LLP_CSR_IS_UP		0x00002000
-#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
-#define IIO_LLP_CSR_LLP_STAT_SHFT       12
-
-#define IIO_LLP_CB_MAX  0xffff	/* in ILLR CB_CNT, Max Check Bit errors */
-#define IIO_LLP_SN_MAX  0xffff	/* in ILLR SN_CNT, Max Sequence Number errors */
-
-/* key to IIO_PROTECT_OVRRD */
-#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull	/* "SGIrules" */
-
-/* BTE register names */
-#define IIO_BTE_STAT_0          IIO_IBLS_0	/* Also BTE length/status 0 */
-#define IIO_BTE_SRC_0           IIO_IBSA_0	/* Also BTE source address  0 */
-#define IIO_BTE_DEST_0          IIO_IBDA_0	/* Also BTE dest. address 0 */
-#define IIO_BTE_CTRL_0          IIO_IBCT_0	/* Also BTE control/terminate 0 */
-#define IIO_BTE_NOTIFY_0        IIO_IBNA_0	/* Also BTE notification 0 */
-#define IIO_BTE_INT_0           IIO_IBIA_0	/* Also BTE interrupt 0 */
-#define IIO_BTE_OFF_0           0	/* Base offset from BTE 0 regs. */
-#define IIO_BTE_OFF_1   	(IIO_IBLS_1 - IIO_IBLS_0)	/* Offset from base to BTE 1 */
-
-/* BTE register offsets from base */
-#define BTEOFF_STAT             0
-#define BTEOFF_SRC      	(IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
-#define BTEOFF_DEST     	(IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
-#define BTEOFF_CTRL     	(IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
-#define BTEOFF_NOTIFY   	(IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
-#define BTEOFF_INT      	(IIO_BTE_INT_0 - IIO_BTE_STAT_0)
-
-/* names used in shub diags */
-#define IIO_BASE_BTE0   IIO_IBLS_0
-#define IIO_BASE_BTE1   IIO_IBLS_1
-
-/*
- * Macro which takes the widget number, and returns the
- * IO PRB address of that widget.
- * value _x is expected to be a widget number in the range
- * 0, 8 - 0xF
- */
-#define IIO_IOPRB(_x)	(IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
-                	(_x) : \
-                	(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
-
-/* GFX Flow Control Node/Widget Register */
-#define IIO_IGFX_W_NUM_BITS	4	/* size of widget num field */
-#define IIO_IGFX_W_NUM_MASK	((1<<IIO_IGFX_W_NUM_BITS)-1)
-#define IIO_IGFX_W_NUM_SHIFT	0
-#define IIO_IGFX_PI_NUM_BITS	1	/* size of PI num field */
-#define IIO_IGFX_PI_NUM_MASK	((1<<IIO_IGFX_PI_NUM_BITS)-1)
-#define IIO_IGFX_PI_NUM_SHIFT	4
-#define IIO_IGFX_N_NUM_BITS	8	/* size of node num field */
-#define IIO_IGFX_N_NUM_MASK	((1<<IIO_IGFX_N_NUM_BITS)-1)
-#define IIO_IGFX_N_NUM_SHIFT	5
-#define IIO_IGFX_P_NUM_BITS	1	/* size of processor num field */
-#define IIO_IGFX_P_NUM_MASK	((1<<IIO_IGFX_P_NUM_BITS)-1)
-#define IIO_IGFX_P_NUM_SHIFT	16
-#define IIO_IGFX_INIT(widget, pi, node, cpu)				(\
-	(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |	 \
-	(((pi)     & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|	 \
-	(((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |	 \
-	(((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
-
-/* Scratch registers (all bits available) */
-#define IIO_SCRATCH_REG0        IIO_ISCR0
-#define IIO_SCRATCH_REG1        IIO_ISCR1
-#define IIO_SCRATCH_MASK        0xffffffffffffffffUL
-
-#define IIO_SCRATCH_BIT0_0      0x0000000000000001UL
-#define IIO_SCRATCH_BIT0_1      0x0000000000000002UL
-#define IIO_SCRATCH_BIT0_2      0x0000000000000004UL
-#define IIO_SCRATCH_BIT0_3      0x0000000000000008UL
-#define IIO_SCRATCH_BIT0_4      0x0000000000000010UL
-#define IIO_SCRATCH_BIT0_5      0x0000000000000020UL
-#define IIO_SCRATCH_BIT0_6      0x0000000000000040UL
-#define IIO_SCRATCH_BIT0_7      0x0000000000000080UL
-#define IIO_SCRATCH_BIT0_8      0x0000000000000100UL
-#define IIO_SCRATCH_BIT0_9      0x0000000000000200UL
-#define IIO_SCRATCH_BIT0_A      0x0000000000000400UL
-
-#define IIO_SCRATCH_BIT1_0      0x0000000000000001UL
-#define IIO_SCRATCH_BIT1_1      0x0000000000000002UL
-/* IO Translation Table Entries */
-#define IIO_NUM_ITTES   7	/* ITTEs numbered 0..6 */
-					/* Hw manuals number them 1..7! */
-/*
- * IIO_IMEM Register fields.
- */
-#define IIO_IMEM_W0ESD  0x1UL	/* Widget 0 shut down due to error */
-#define IIO_IMEM_B0ESD	(1UL << 4)	/* BTE 0 shut down due to error */
-#define IIO_IMEM_B1ESD	(1UL << 8)	/* BTE 1 Shut down due to error */
-
-/*
- * As a permanent workaround for a bug in the PI side of the shub, we've
- * redefined big window 7 as small window 0.
- XXX does this still apply for SN1??
- */
-#define HUB_NUM_BIG_WINDOW	(IIO_NUM_ITTES - 1)
-
-/*
- * Use the top big window as a surrogate for the first small window
- */
-#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
-
-#define ILCSR_WARM_RESET        0x100
-
-/*
- * CRB manipulation macros
- *	The CRB macros are slightly complicated, since there are up to
- *	four registers associated with each CRB entry.
- */
-#define IIO_NUM_CRBS            15	/* Number of CRBs */
-#define IIO_NUM_PC_CRBS         4	/* Number of partial cache CRBs */
-#define IIO_ICRB_OFFSET         8
-#define IIO_ICRB_0              IIO_ICRB0_A
-#define IIO_ICRB_ADDR_SHFT	2	/* Shift to get proper address */
-/* XXX - This is now tuneable:
-        #define IIO_FIRST_PC_ENTRY 12
- */
-
-#define IIO_ICRB_A(_x)	((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
-#define IIO_ICRB_B(_x)	((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
-#define IIO_ICRB_C(_x)	((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
-#define IIO_ICRB_D(_x)	((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
-#define IIO_ICRB_E(_x)	((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
-
-#define TNUM_TO_WIDGET_DEV(_tnum)	(_tnum & 0x7)
-
-/*
- * values for "ecode" field
- */
-#define IIO_ICRB_ECODE_DERR     0	/* Directory error due to IIO access */
-#define IIO_ICRB_ECODE_PERR     1	/* Poison error on IO access */
-#define IIO_ICRB_ECODE_WERR     2	/* Write error by IIO access
-					 * e.g. WINV to a Read only line. */
-#define IIO_ICRB_ECODE_AERR     3	/* Access error caused by IIO access */
-#define IIO_ICRB_ECODE_PWERR    4	/* Error on partial write */
-#define IIO_ICRB_ECODE_PRERR    5	/* Error on partial read  */
-#define IIO_ICRB_ECODE_TOUT     6	/* CRB timeout before deallocating */
-#define IIO_ICRB_ECODE_XTERR    7	/* Incoming xtalk pkt had error bit */
-
-/*
- * Values for field imsgtype
- */
-#define IIO_ICRB_IMSGT_XTALK    0	/* Incoming message from Xtalk */
-#define IIO_ICRB_IMSGT_BTE      1	/* Incoming message from BTE    */
-#define IIO_ICRB_IMSGT_SN1NET   2	/* Incoming message from SN1 net */
-#define IIO_ICRB_IMSGT_CRB      3	/* Incoming message from CRB ???  */
-
-/*
- * values for field initiator.
- */
-#define IIO_ICRB_INIT_XTALK     0	/* Message originated in xtalk  */
-#define IIO_ICRB_INIT_BTE0      0x1	/* Message originated in BTE 0  */
-#define IIO_ICRB_INIT_SN1NET    0x2	/* Message originated in SN1net */
-#define IIO_ICRB_INIT_CRB       0x3	/* Message originated in CRB ?  */
-#define IIO_ICRB_INIT_BTE1      0x5	/* MEssage originated in BTE 1  */
-
-/*
- * Number of credits Hub widget has while sending req/response to
- * xbow.
- * Value of 3 is required by Xbow 1.1
- * We may be able to increase this to 4 with Xbow 1.2.
- */
-#define		   HUBII_XBOW_CREDIT       3
-#define		   HUBII_XBOW_REV2_CREDIT  4
-
-/*
- * Number of credits that xtalk devices should use when communicating
- * with a SHub (depth of SHub's queue).
- */
-#define HUB_CREDIT 4
-
-/*
- * Some IIO_PRB fields
- */
-#define IIO_PRB_MULTI_ERR	(1LL << 63)
-#define IIO_PRB_SPUR_RD		(1LL << 51)
-#define IIO_PRB_SPUR_WR		(1LL << 50)
-#define IIO_PRB_RD_TO		(1LL << 49)
-#define IIO_PRB_ERROR		(1LL << 48)
-
-/*************************************************************************
-
- Some of the IIO field masks and shifts are defined here.
- This is in order to maintain compatibility in SN0 and SN1 code
- 
-**************************************************************************/
-
-/*
- * ICMR register fields
- * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
- * present in SHub)
- */
-
-#define IIO_ICMR_CRB_VLD_SHFT   20
-#define IIO_ICMR_CRB_VLD_MASK	(0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
-
-#define IIO_ICMR_FC_CNT_SHFT    16
-#define IIO_ICMR_FC_CNT_MASK	(0xf << IIO_ICMR_FC_CNT_SHFT)
-
-#define IIO_ICMR_C_CNT_SHFT     4
-#define IIO_ICMR_C_CNT_MASK	(0xf << IIO_ICMR_C_CNT_SHFT)
-
-#define IIO_ICMR_PRECISE	(1UL << 52)
-#define IIO_ICMR_CLR_RPPD	(1UL << 13)
-#define IIO_ICMR_CLR_RQPD	(1UL << 12)
-
-/*
- * IIO PIO Deallocation register field masks : (IIO_IPDR)
- XXX present but not needed in bedrock?  See the manual.
- */
-#define IIO_IPDR_PND    	(1 << 4)
-
-/*
- * IIO CRB deallocation register field masks: (IIO_ICDR)
- */
-#define IIO_ICDR_PND    	(1 << 4)
-
-/* 
- * IO BTE Length/Status (IIO_IBLS) register bit field definitions
- */
-#define IBLS_BUSY		(0x1UL << 20)
-#define IBLS_ERROR_SHFT		16
-#define IBLS_ERROR		(0x1UL << IBLS_ERROR_SHFT)
-#define IBLS_LENGTH_MASK	0xffff
-
-/*
- * IO BTE Control/Terminate register (IBCT) register bit field definitions
- */
-#define IBCT_POISON		(0x1UL << 8)
-#define IBCT_NOTIFY		(0x1UL << 4)
-#define IBCT_ZFIL_MODE		(0x1UL << 0)
-
-/*
- * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
- */
-#define IIEPH1_VALID		(1UL << 44)
-#define IIEPH1_OVERRUN		(1UL << 40)
-#define IIEPH1_ERR_TYPE_SHFT	32
-#define IIEPH1_ERR_TYPE_MASK	0xf
-#define IIEPH1_SOURCE_SHFT	20
-#define IIEPH1_SOURCE_MASK	11
-#define IIEPH1_SUPPL_SHFT	8
-#define IIEPH1_SUPPL_MASK	11
-#define IIEPH1_CMD_SHFT		0
-#define IIEPH1_CMD_MASK		7
-
-#define IIEPH2_TAIL		(1UL << 40)
-#define IIEPH2_ADDRESS_SHFT	0
-#define IIEPH2_ADDRESS_MASK	38
-
-#define IIEPH1_ERR_SHORT_REQ	2
-#define IIEPH1_ERR_SHORT_REPLY	3
-#define IIEPH1_ERR_LONG_REQ	4
-#define IIEPH1_ERR_LONG_REPLY	5
-
-/*
- * IO Error Clear register bit field definitions
- */
-#define IECLR_PI1_FWD_INT	(1UL << 31)	/* clear PI1_FORWARD_INT in iidsr */
-#define IECLR_PI0_FWD_INT	(1UL << 30)	/* clear PI0_FORWARD_INT in iidsr */
-#define IECLR_SPUR_RD_HDR	(1UL << 29)	/* clear valid bit in ixss reg */
-#define IECLR_BTE1		(1UL << 18)	/* clear bte error 1 */
-#define IECLR_BTE0		(1UL << 17)	/* clear bte error 0 */
-#define IECLR_CRAZY		(1UL << 16)	/* clear crazy bit in wstat reg */
-#define IECLR_PRB_F		(1UL << 15)	/* clear err bit in PRB_F reg */
-#define IECLR_PRB_E		(1UL << 14)	/* clear err bit in PRB_E reg */
-#define IECLR_PRB_D		(1UL << 13)	/* clear err bit in PRB_D reg */
-#define IECLR_PRB_C		(1UL << 12)	/* clear err bit in PRB_C reg */
-#define IECLR_PRB_B		(1UL << 11)	/* clear err bit in PRB_B reg */
-#define IECLR_PRB_A		(1UL << 10)	/* clear err bit in PRB_A reg */
-#define IECLR_PRB_9		(1UL << 9)	/* clear err bit in PRB_9 reg */
-#define IECLR_PRB_8		(1UL << 8)	/* clear err bit in PRB_8 reg */
-#define IECLR_PRB_0		(1UL << 0)	/* clear err bit in PRB_0 reg */
-
-/*
- * IIO CRB control register Fields: IIO_ICCR 
- */
-#define	IIO_ICCR_PENDING	0x10000
-#define	IIO_ICCR_CMD_MASK	0xFF
-#define	IIO_ICCR_CMD_SHFT	7
-#define	IIO_ICCR_CMD_NOP	0x0	/* No Op */
-#define	IIO_ICCR_CMD_WAKE	0x100	/* Reactivate CRB entry and process */
-#define	IIO_ICCR_CMD_TIMEOUT	0x200	/* Make CRB timeout & mark invalid */
-#define	IIO_ICCR_CMD_EJECT	0x400	/* Contents of entry written to memory
-					 * via a WB
-					 */
-#define	IIO_ICCR_CMD_FLUSH	0x800
-
-/*
- *
- * CRB Register description.
- *
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- *
- * Many of the fields in CRB are status bits used by hardware
- * for implementation of the protocol. It's very dangerous to
- * mess around with the CRB registers.
- *
- * It's OK to read the CRB registers and try to make sense out of the
- * fields in CRB.
- *
- * Updating CRB requires all activities in Hub IIO to be quiesced.
- * otherwise, a write to CRB could corrupt other CRB entries.
- * CRBs are here only as a back door peek to shub IIO's status.
- * Quiescing implies  no dmas no PIOs
- * either directly from the cpu or from sn0net.
- * this is not something that can be done easily. So, AVOID updating
- * CRBs.
- */
-
-/*
- * Easy access macros for CRBs, all 5 registers (A-E)
- */
-typedef ii_icrb0_a_u_t icrba_t;
-#define a_sidn		ii_icrb0_a_fld_s.ia_sidn
-#define a_tnum		ii_icrb0_a_fld_s.ia_tnum
-#define a_addr          ii_icrb0_a_fld_s.ia_addr
-#define a_valid         ii_icrb0_a_fld_s.ia_vld
-#define a_iow           ii_icrb0_a_fld_s.ia_iow
-#define a_regvalue	ii_icrb0_a_regval
-
-typedef ii_icrb0_b_u_t icrbb_t;
-#define b_use_old       ii_icrb0_b_fld_s.ib_use_old
-#define b_imsgtype      ii_icrb0_b_fld_s.ib_imsgtype
-#define b_imsg          ii_icrb0_b_fld_s.ib_imsg
-#define b_initiator     ii_icrb0_b_fld_s.ib_init
-#define b_exc           ii_icrb0_b_fld_s.ib_exc
-#define b_ackcnt        ii_icrb0_b_fld_s.ib_ack_cnt
-#define b_resp          ii_icrb0_b_fld_s.ib_resp
-#define b_ack           ii_icrb0_b_fld_s.ib_ack
-#define b_hold          ii_icrb0_b_fld_s.ib_hold
-#define b_wb            ii_icrb0_b_fld_s.ib_wb
-#define b_intvn         ii_icrb0_b_fld_s.ib_intvn
-#define b_stall_ib      ii_icrb0_b_fld_s.ib_stall_ib
-#define b_stall_int     ii_icrb0_b_fld_s.ib_stall__intr
-#define b_stall_bte_0   ii_icrb0_b_fld_s.ib_stall__bte_0
-#define b_stall_bte_1   ii_icrb0_b_fld_s.ib_stall__bte_1
-#define b_error         ii_icrb0_b_fld_s.ib_error
-#define b_ecode         ii_icrb0_b_fld_s.ib_errcode
-#define b_lnetuce       ii_icrb0_b_fld_s.ib_ln_uce
-#define b_mark          ii_icrb0_b_fld_s.ib_mark
-#define b_xerr          ii_icrb0_b_fld_s.ib_xt_err
-#define b_regvalue	ii_icrb0_b_regval
-
-typedef ii_icrb0_c_u_t icrbc_t;
-#define c_suppl         ii_icrb0_c_fld_s.ic_suppl
-#define c_barrop        ii_icrb0_c_fld_s.ic_bo
-#define c_doresp        ii_icrb0_c_fld_s.ic_resprqd
-#define c_gbr           ii_icrb0_c_fld_s.ic_gbr
-#define c_btenum        ii_icrb0_c_fld_s.ic_bte_num
-#define c_cohtrans      ii_icrb0_c_fld_s.ic_ct
-#define c_xtsize        ii_icrb0_c_fld_s.ic_size
-#define c_source        ii_icrb0_c_fld_s.ic_source
-#define c_regvalue	ii_icrb0_c_regval
-
-typedef ii_icrb0_d_u_t icrbd_t;
-#define d_sleep         ii_icrb0_d_fld_s.id_sleep
-#define d_pricnt        ii_icrb0_d_fld_s.id_pr_cnt
-#define d_pripsc        ii_icrb0_d_fld_s.id_pr_psc
-#define d_bteop         ii_icrb0_d_fld_s.id_bte_op
-#define d_bteaddr       ii_icrb0_d_fld_s.id_pa_be	/* ic_pa_be fld has 2 names */
-#define d_benable       ii_icrb0_d_fld_s.id_pa_be	/* ic_pa_be fld has 2 names */
-#define d_regvalue	ii_icrb0_d_regval
-
-typedef ii_icrb0_e_u_t icrbe_t;
-#define icrbe_ctxtvld   ii_icrb0_e_fld_s.ie_cvld
-#define icrbe_toutvld   ii_icrb0_e_fld_s.ie_tvld
-#define icrbe_context   ii_icrb0_e_fld_s.ie_context
-#define icrbe_timeout   ii_icrb0_e_fld_s.ie_timeout
-#define e_regvalue	ii_icrb0_e_regval
-
-/* Number of widgets supported by shub */
-#define HUB_NUM_WIDGET          9
-#define HUB_WIDGET_ID_MIN       0x8
-#define HUB_WIDGET_ID_MAX       0xf
-
-#define HUB_WIDGET_PART_NUM     0xc120
-#define MAX_HUBS_PER_XBOW       2
-
-/* A few more #defines for backwards compatibility */
-#define iprb_t          ii_iprb0_u_t
-#define iprb_regval     ii_iprb0_regval
-#define iprb_mult_err	ii_iprb0_fld_s.i_mult_err
-#define iprb_spur_rd	ii_iprb0_fld_s.i_spur_rd
-#define iprb_spur_wr	ii_iprb0_fld_s.i_spur_wr
-#define iprb_rd_to	ii_iprb0_fld_s.i_rd_to
-#define iprb_ovflow     ii_iprb0_fld_s.i_of_cnt
-#define iprb_error      ii_iprb0_fld_s.i_error
-#define iprb_ff         ii_iprb0_fld_s.i_f
-#define iprb_mode       ii_iprb0_fld_s.i_m
-#define iprb_bnakctr    ii_iprb0_fld_s.i_nb
-#define iprb_anakctr    ii_iprb0_fld_s.i_na
-#define iprb_xtalkctr   ii_iprb0_fld_s.i_c
-
-#define LNK_STAT_WORKING        0x2		/* LLP is working */
-
-#define IIO_WSTAT_ECRAZY	(1ULL << 32)	/* Hub gone crazy */
-#define IIO_WSTAT_TXRETRY	(1ULL << 9)	/* Hub Tx Retry timeout */
-#define IIO_WSTAT_TXRETRY_MASK  0x7F		/* should be 0xFF?? */
-#define IIO_WSTAT_TXRETRY_SHFT  16
-#define IIO_WSTAT_TXRETRY_CNT(w)	(((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
-                          		IIO_WSTAT_TXRETRY_MASK)
-
-/* Number of II perf. counters we can multiplex at once */
-
-#define IO_PERF_SETS	32
-
-/* Bit for the widget in inbound access register */
-#define IIO_IIWA_WIDGET(_w)	((u64)(1ULL << _w))
-/* Bit for the widget in outbound access register */
-#define IIO_IOWA_WIDGET(_w)	((u64)(1ULL << _w))
-
-/* NOTE: The following define assumes that we are going to get
- * widget numbers from 8 thru F and the device numbers within
- * widget from 0 thru 7.
- */
-#define IIO_IIDEM_WIDGETDEV_MASK(w, d)	((u64)(1ULL << (8 * ((w) - 8) + (d))))
-
-/* IO Interrupt Destination Register */
-#define IIO_IIDSR_SENT_SHIFT    28
-#define IIO_IIDSR_SENT_MASK     0x30000000
-#define IIO_IIDSR_ENB_SHIFT     24
-#define IIO_IIDSR_ENB_MASK      0x01000000
-#define IIO_IIDSR_NODE_SHIFT    9
-#define IIO_IIDSR_NODE_MASK     0x000ff700
-#define IIO_IIDSR_PI_ID_SHIFT   8
-#define IIO_IIDSR_PI_ID_MASK    0x00000100
-#define IIO_IIDSR_LVL_SHIFT     0
-#define IIO_IIDSR_LVL_MASK      0x000000ff
-
-/* Xtalk timeout threshold register (IIO_IXTT) */
-#define IXTT_RRSP_TO_SHFT	55	/* read response timeout */
-#define IXTT_RRSP_TO_MASK	(0x1FULL << IXTT_RRSP_TO_SHFT)
-#define IXTT_RRSP_PS_SHFT	32	/* read responsed TO prescalar */
-#define IXTT_RRSP_PS_MASK	(0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
-#define IXTT_TAIL_TO_SHFT	0	/* tail timeout counter threshold */
-#define IXTT_TAIL_TO_MASK	(0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
-
-/*
- * The IO LLP control status register and widget control register
- */
-
-typedef union hubii_wcr_u {
-	u64 wcr_reg_value;
-	struct {
-		u64 wcr_widget_id:4,	/* LLP crossbar credit */
-		 wcr_tag_mode:1,	/* Tag mode */
-		 wcr_rsvd1:8,	/* Reserved */
-		 wcr_xbar_crd:3,	/* LLP crossbar credit */
-		 wcr_f_bad_pkt:1,	/* Force bad llp pkt enable */
-		 wcr_dir_con:1,	/* widget direct connect */
-		 wcr_e_thresh:5,	/* elasticity threshold */
-		 wcr_rsvd:41;	/* unused */
-	} wcr_fields_s;
-} hubii_wcr_t;
-
-#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
-
-/* The structures below are defined to extract and modify the ii
-performance registers */
-
-/* io_perf_sel allows the caller to specify what tests will be
-   performed */
-
-typedef union io_perf_sel {
-	u64 perf_sel_reg;
-	struct {
-		u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
-	} perf_sel_bits;
-} io_perf_sel_t;
-
-/* io_perf_cnt is to extract the count from the shub registers. Due to
-   hardware problems there is only one counter, not two. */
-
-typedef union io_perf_cnt {
-	u64 perf_cnt;
-	struct {
-		u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
-	} perf_cnt_bits;
-
-} io_perf_cnt_t;
-
-typedef union iprte_a {
-	u64 entry;
-	struct {
-		u64 i_rsvd_1:3;
-		u64 i_addr:38;
-		u64 i_init:3;
-		u64 i_source:8;
-		u64 i_rsvd:2;
-		u64 i_widget:4;
-		u64 i_to_cnt:5;
-		u64 i_vld:1;
-	} iprte_fields;
-} iprte_a_t;
-
-#endif				/* _ASM_IA64_SN_SHUBIO_H */
diff --git a/arch/ia64/include/asm/sn/simulator.h b/arch/ia64/include/asm/sn/simulator.h
deleted file mode 100644
index c2611f6cfe33..000000000000
--- a/arch/ia64/include/asm/sn/simulator.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_SIMULATOR_H
-#define _ASM_IA64_SN_SIMULATOR_H
-
-#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_SGI_UV)
-#define SNMAGIC 0xaeeeeeee8badbeefL
-#define IS_MEDUSA()			({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
-
-#define SIMULATOR_SLEEP()		asm("nop.i 0x8beef")
-#define IS_RUNNING_ON_SIMULATOR()	(sn_prom_type)
-#define IS_RUNNING_ON_FAKE_PROM()	(sn_prom_type == 2)
-extern int sn_prom_type;		/* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
-#else
-#define IS_MEDUSA()			0
-#define SIMULATOR_SLEEP()
-#define IS_RUNNING_ON_SIMULATOR()	0
-#endif
-
-#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/arch/ia64/include/asm/sn/sn2/sn_hwperf.h b/arch/ia64/include/asm/sn/sn2/sn_hwperf.h
deleted file mode 100644
index e61ebac38cdd..000000000000
--- a/arch/ia64/include/asm/sn/sn2/sn_hwperf.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
- *
- * Data types used by the SN_SAL_HWPERF_OP SAL call for monitoring
- * SGI Altix node and router hardware
- *
- * Mark Goodwin <markgw@sgi.com> Mon Aug 30 12:23:46 EST 2004
- */
-
-#ifndef SN_HWPERF_H
-#define SN_HWPERF_H
-
-/*
- * object structure. SN_HWPERF_ENUM_OBJECTS and SN_HWPERF_GET_CPU_INFO
- * return an array of these. Do not change this without also
- * changing the corresponding SAL code.
- */
-#define SN_HWPERF_MAXSTRING		128
-struct sn_hwperf_object_info {
-	u32 id;
-	union {
-		struct {
-			u64 this_part:1;
-			u64 is_shared:1;
-		} fields;
-		struct {
-			u64 flags;
-			u64 reserved;
-		} b;
-	} f;
-	char name[SN_HWPERF_MAXSTRING];
-	char location[SN_HWPERF_MAXSTRING];
-	u32 ports;
-};
-
-#define sn_hwp_this_part	f.fields.this_part
-#define sn_hwp_is_shared	f.fields.is_shared
-#define sn_hwp_flags		f.b.flags
-
-/* macros for object classification */
-#define SN_HWPERF_IS_NODE(x)		((x) && strstr((x)->name, "SHub"))
-#define SN_HWPERF_IS_NODE_SHUB2(x)	((x) && strstr((x)->name, "SHub 2."))
-#define SN_HWPERF_IS_IONODE(x)		((x) && strstr((x)->name, "TIO"))
-#define SN_HWPERF_IS_NL3ROUTER(x)	((x) && strstr((x)->name, "NL3Router"))
-#define SN_HWPERF_IS_NL4ROUTER(x)	((x) && strstr((x)->name, "NL4Router"))
-#define SN_HWPERF_IS_OLDROUTER(x)	((x) && strstr((x)->name, "Router"))
-#define SN_HWPERF_IS_ROUTER(x)		(SN_HWPERF_IS_NL3ROUTER(x) || 		\
-					 	SN_HWPERF_IS_NL4ROUTER(x) || 	\
-					 	SN_HWPERF_IS_OLDROUTER(x))
-#define SN_HWPERF_FOREIGN(x)		((x) && !(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
-#define SN_HWPERF_SAME_OBJTYPE(x,y)	((SN_HWPERF_IS_NODE(x) && SN_HWPERF_IS_NODE(y)) ||\
-					(SN_HWPERF_IS_IONODE(x) && SN_HWPERF_IS_IONODE(y)) ||\
-					(SN_HWPERF_IS_ROUTER(x) && SN_HWPERF_IS_ROUTER(y)))
-
-/* numa port structure, SN_HWPERF_ENUM_PORTS returns an array of these */
-struct sn_hwperf_port_info {
-	u32 port;
-	u32 conn_id;
-	u32 conn_port;
-};
-
-/* for HWPERF_{GET,SET}_MMRS */
-struct sn_hwperf_data {
-	u64 addr;
-	u64 data;
-};
-
-/* user ioctl() argument, see below */
-struct sn_hwperf_ioctl_args {
-        u64 arg;		/* argument, usually an object id */
-        u64 sz;                 /* size of transfer */
-        void *ptr;              /* pointer to source/target */
-        u32 v0;			/* second return value */
-};
-
-/*
- * For SN_HWPERF_{GET,SET}_MMRS and SN_HWPERF_OBJECT_DISTANCE,
- * sn_hwperf_ioctl_args.arg can be used to specify a CPU on which
- * to call SAL, and whether to use an interprocessor interrupt
- * or task migration in order to do so. If the CPU specified is
- * SN_HWPERF_ARG_ANY_CPU, then the current CPU will be used.
- */
-#define SN_HWPERF_ARG_ANY_CPU		0x7fffffffUL
-#define SN_HWPERF_ARG_CPU_MASK		0x7fffffff00000000ULL
-#define SN_HWPERF_ARG_USE_IPI_MASK	0x8000000000000000ULL
-#define SN_HWPERF_ARG_OBJID_MASK	0x00000000ffffffffULL
-
-/* 
- * ioctl requests on the "sn_hwperf" misc device that call SAL.
- */
-#define SN_HWPERF_OP_MEM_COPYIN		0x1000
-#define SN_HWPERF_OP_MEM_COPYOUT	0x2000
-#define SN_HWPERF_OP_MASK		0x0fff
-
-/*
- * Determine mem requirement.
- * arg	don't care
- * sz	8
- * p	pointer to u64 integer
- */
-#define	SN_HWPERF_GET_HEAPSIZE		1
-
-/*
- * Install mem for SAL drvr
- * arg	don't care
- * sz	sizeof buffer pointed to by p
- * p	pointer to buffer for scratch area
- */
-#define SN_HWPERF_INSTALL_HEAP		2
-
-/*
- * Determine number of objects
- * arg	don't care
- * sz	8
- * p	pointer to u64 integer
- */
-#define SN_HWPERF_OBJECT_COUNT		(10|SN_HWPERF_OP_MEM_COPYOUT)
-
-/*
- * Determine object "distance", relative to a cpu. This operation can
- * execute on a designated logical cpu number, using either an IPI or
- * via task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
- * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
- *
- * arg	bitmap of IPI flag, cpu number and object id
- * sz	8
- * p	pointer to u64 integer
- */
-#define SN_HWPERF_OBJECT_DISTANCE	(11|SN_HWPERF_OP_MEM_COPYOUT)
-
-/*
- * Enumerate objects. Special case if sz == 8, returns the required
- * buffer size.
- * arg	don't care
- * sz	sizeof buffer pointed to by p
- * p	pointer to array of struct sn_hwperf_object_info
- */
-#define SN_HWPERF_ENUM_OBJECTS		(12|SN_HWPERF_OP_MEM_COPYOUT)
-
-/*
- * Enumerate NumaLink ports for an object. Special case if sz == 8,
- * returns the required buffer size.
- * arg	object id
- * sz	sizeof buffer pointed to by p
- * p	pointer to array of struct sn_hwperf_port_info
- */
-#define SN_HWPERF_ENUM_PORTS		(13|SN_HWPERF_OP_MEM_COPYOUT)
-
-/*
- * SET/GET memory mapped registers. These operations can execute
- * on a designated logical cpu number, using either an IPI or via
- * task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
- * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
- *
- * arg	bitmap of ipi flag, cpu number and object id
- * sz	sizeof buffer pointed to by p
- * p	pointer to array of struct sn_hwperf_data
- */
-#define SN_HWPERF_SET_MMRS		(14|SN_HWPERF_OP_MEM_COPYIN)
-#define SN_HWPERF_GET_MMRS		(15|SN_HWPERF_OP_MEM_COPYOUT| \
-					    SN_HWPERF_OP_MEM_COPYIN)
-/*
- * Lock a shared object
- * arg	object id
- * sz	don't care
- * p	don't care
- */
-#define SN_HWPERF_ACQUIRE		16
-
-/*
- * Unlock a shared object
- * arg	object id
- * sz	don't care
- * p	don't care
- */
-#define SN_HWPERF_RELEASE		17
-
-/*
- * Break a lock on a shared object
- * arg	object id
- * sz	don't care
- * p	don't care
- */
-#define SN_HWPERF_FORCE_RELEASE		18
-
-/*
- * ioctl requests on "sn_hwperf" that do not call SAL
- */
-
-/*
- * get cpu info as an array of hwperf_object_info_t. 
- * id is logical CPU number, name is description, location
- * is geoid (e.g. 001c04#1c). Special case if sz == 8,
- * returns the required buffer size.
- *
- * arg	don't care
- * sz	sizeof buffer pointed to by p
- * p	pointer to array of struct sn_hwperf_object_info
- */
-#define SN_HWPERF_GET_CPU_INFO		(100|SN_HWPERF_OP_MEM_COPYOUT)
-
-/*
- * Given an object id, return it's node number (aka cnode).
- * arg	object id
- * sz	8
- * p	pointer to u64 integer
- */
-#define SN_HWPERF_GET_OBJ_NODE		(101|SN_HWPERF_OP_MEM_COPYOUT)
-
-/*
- * Given a node number (cnode), return it's nasid.
- * arg	ordinal node number (aka cnodeid)
- * sz	8
- * p	pointer to u64 integer
- */
-#define SN_HWPERF_GET_NODE_NASID	(102|SN_HWPERF_OP_MEM_COPYOUT)
-
-/*
- * Given a node id, determine the id of the nearest node with CPUs
- * and the id of the nearest node that has memory. The argument
- * node would normally be a "headless" node, e.g. an "IO node".
- * Return 0 on success.
- */
-extern int sn_hwperf_get_nearest_node(cnodeid_t node,
-	cnodeid_t *near_mem, cnodeid_t *near_cpu);
-
-/* return codes */
-#define SN_HWPERF_OP_OK			0
-#define SN_HWPERF_OP_NOMEM		1
-#define SN_HWPERF_OP_NO_PERM		2
-#define SN_HWPERF_OP_IO_ERROR		3
-#define SN_HWPERF_OP_BUSY		4
-#define SN_HWPERF_OP_RECONFIGURE	253
-#define SN_HWPERF_OP_INVAL		254
-
-int sn_topology_open(struct inode *inode, struct file *file);
-int sn_topology_release(struct inode *inode, struct file *file);
-#endif				/* SN_HWPERF_H */
diff --git a/arch/ia64/include/asm/sn/sn_cpuid.h b/arch/ia64/include/asm/sn/sn_cpuid.h
deleted file mode 100644
index a676dd9ace3e..000000000000
--- a/arch/ia64/include/asm/sn/sn_cpuid.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-
-#ifndef _ASM_IA64_SN_SN_CPUID_H
-#define _ASM_IA64_SN_SN_CPUID_H
-
-#include <linux/smp.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/pda.h>
-#include <asm/intrinsics.h>
-
-
-/*
- * Functions for converting between cpuids, nodeids and NASIDs.
- * 
- * These are for SGI platforms only.
- *
- */
-
-
-
-
-/*
- *  Definitions of terms (these definitions are for IA64 ONLY. Other architectures
- *  use cpuid/cpunum quite defferently):
- *
- *	   CPUID - a number in range of 0..NR_CPUS-1 that uniquely identifies
- *		the cpu. The value cpuid has no significance on IA64 other than
- *		the boot cpu is 0.
- *			smp_processor_id() returns the cpuid of the current cpu.
- *
- * 	   CPU_PHYSICAL_ID (also known as HARD_PROCESSOR_ID)
- *		This is the same as 31:24 of the processor LID register
- *			hard_smp_processor_id()- cpu_physical_id of current processor
- *			cpu_physical_id(cpuid) - convert a <cpuid> to a <physical_cpuid>
- *			cpu_logical_id(phy_id) - convert a <physical_cpuid> to a <cpuid> 
- *				* not real efficient - don't use in perf critical code
- *
- *         SLICE - a number in the range of 0 - 3 (typically) that represents the
- *		cpu number on a brick.
- *
- *	   SUBNODE - (almost obsolete) the number of the FSB that a cpu is
- *		connected to. This is also the same as the PI number. Usually 0 or 1.
- *
- *	NOTE!!!: the value of the bits in the cpu physical id (SAPICid or LID) of a cpu has no 
- *	significance. The SAPIC id (LID) is a 16-bit cookie that has meaning only to the PROM.
- *
- *
- * The macros convert between cpu physical ids & slice/nasid/cnodeid.
- * These terms are described below:
- *
- *
- * Brick
- *          -----   -----           -----   -----       CPU
- *          | 0 |   | 1 |           | 0 |   | 1 |       SLICE
- *          -----   -----           -----   -----
- *            |       |               |       |
- *            |       |               |       |
- *          0 |       | 2           0 |       | 2       FSB SLOT
- *             -------                 -------  
- *                |                       |
- *                |                       |
- *                |                       |
- *             ------------      -------------
- *             |          |      |           |
- *             |    SHUB  |      |   SHUB    |        NASID   (0..MAX_NASIDS)
- *             |          |----- |           |        CNODEID (0..num_compact_nodes-1)
- *             |          |      |           |
- *             |          |      |           |
- *             ------------      -------------
- *                   |                 |
- *                           
- *
- */
-
-#define get_node_number(addr)			NASID_GET(addr)
-
-/*
- * NOTE: on non-MP systems, only cpuid 0 exists
- */
-
-extern short physical_node_map[];	/* indexed by nasid to get cnode */
-
-/*
- * Macros for retrieving info about current cpu
- */
-#define get_nasid()	(sn_nodepda->phys_cpuid[smp_processor_id()].nasid)
-#define get_subnode()	(sn_nodepda->phys_cpuid[smp_processor_id()].subnode)
-#define get_slice()	(sn_nodepda->phys_cpuid[smp_processor_id()].slice)
-#define get_cnode()	(sn_nodepda->phys_cpuid[smp_processor_id()].cnode)
-#define get_sapicid()	((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
-
-/*
- * Macros for retrieving info about an arbitrary cpu
- *	cpuid - logical cpu id
- */
-#define cpuid_to_nasid(cpuid)		(sn_nodepda->phys_cpuid[cpuid].nasid)
-#define cpuid_to_subnode(cpuid)		(sn_nodepda->phys_cpuid[cpuid].subnode)
-#define cpuid_to_slice(cpuid)		(sn_nodepda->phys_cpuid[cpuid].slice)
-
-
-/*
- * Dont use the following in performance critical code. They require scans
- * of potentially large tables.
- */
-extern int nasid_slice_to_cpuid(int, int);
-
-/*
- * cnodeid_to_nasid - convert a cnodeid to a NASID
- */
-#define cnodeid_to_nasid(cnodeid)	(sn_cnodeid_to_nasid[cnodeid])
- 
-/*
- * nasid_to_cnodeid - convert a NASID to a cnodeid
- */
-#define nasid_to_cnodeid(nasid)		(physical_node_map[nasid])
-
-/*
- * partition_coherence_id - get the coherence ID of the current partition
- */
-extern u8 sn_coherency_id;
-#define partition_coherence_id()	(sn_coherency_id)
-
-#endif /* _ASM_IA64_SN_SN_CPUID_H */
-
diff --git a/arch/ia64/include/asm/sn/sn_feature_sets.h b/arch/ia64/include/asm/sn/sn_feature_sets.h
deleted file mode 100644
index 8e83ac117ace..000000000000
--- a/arch/ia64/include/asm/sn/sn_feature_sets.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _ASM_IA64_SN_FEATURE_SETS_H
-#define _ASM_IA64_SN_FEATURE_SETS_H
-
-/*
- * SN PROM Features
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2005-2006 Silicon Graphics, Inc.  All rights reserved.
- */
-
-
-/* --------------------- PROM Features -----------------------------*/
-extern int sn_prom_feature_available(int id);
-
-#define MAX_PROM_FEATURE_SETS			2
-
-/*
- * The following defines features that may or may not be supported by the
- * current PROM. The OS uses sn_prom_feature_available(feature) to test for
- * the presence of a PROM feature. Down rev (old) PROMs will always test
- * "false" for new features.
- *
- * Use:
- * 		if (sn_prom_feature_available(PRF_XXX))
- * 			...
- */
-
-#define PRF_PAL_CACHE_FLUSH_SAFE	0
-#define PRF_DEVICE_FLUSH_LIST		1
-#define PRF_HOTPLUG_SUPPORT		2
-#define PRF_CPU_DISABLE_SUPPORT		3
-
-/* --------------------- OS Features -------------------------------*/
-
-/*
- * The following defines OS features that are optionally present in
- * the operating system.
- * During boot, PROM is notified of these features via a series of calls:
- *
- * 		ia64_sn_set_os_feature(feature1);
- *
- * Once enabled, a feature cannot be disabled.
- *
- * By default, features are disabled unless explicitly enabled.
- *
- * These defines must be kept in sync with the corresponding
- * PROM definitions in feature_sets.h.
- */
-#define  OSF_MCA_SLV_TO_OS_INIT_SLV	0
-#define  OSF_FEAT_LOG_SBES		1
-#define  OSF_ACPI_ENABLE		2
-#define  OSF_PCISEGMENT_ENABLE		3
-
-
-#endif /* _ASM_IA64_SN_FEATURE_SETS_H */
diff --git a/arch/ia64/include/asm/sn/sn_sal.h b/arch/ia64/include/asm/sn/sn_sal.h
index 1f5ff470a5a1..d437aa43343b 100644
--- a/arch/ia64/include/asm/sn/sn_sal.h
+++ b/arch/ia64/include/asm/sn/sn_sal.h
@@ -11,140 +11,17 @@
  * Copyright (c) 2000-2006 Silicon Graphics, Inc.  All rights reserved.
  */
 
-
+#include <linux/types.h>
 #include <asm/sal.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/geo.h>
-#include <asm/sn/nodepda.h>
-#include <asm/sn/shub_mmr.h>
 
 // SGI Specific Calls
-#define  SN_SAL_POD_MODE                           0x02000001
-#define  SN_SAL_SYSTEM_RESET                       0x02000002
-#define  SN_SAL_PROBE                              0x02000003
-#define  SN_SAL_GET_MASTER_NASID                   0x02000004
-#define	 SN_SAL_GET_KLCONFIG_ADDR		   0x02000005
-#define  SN_SAL_LOG_CE				   0x02000006
-#define  SN_SAL_REGISTER_CE			   0x02000007
 #define  SN_SAL_GET_PARTITION_ADDR		   0x02000009
-#define  SN_SAL_XP_ADDR_REGION			   0x0200000f
-#define  SN_SAL_NO_FAULT_ZONE_VIRTUAL		   0x02000010
-#define  SN_SAL_NO_FAULT_ZONE_PHYSICAL		   0x02000011
-#define  SN_SAL_PRINT_ERROR			   0x02000012
-#define  SN_SAL_REGISTER_PMI_HANDLER		   0x02000014
-#define  SN_SAL_SET_ERROR_HANDLING_FEATURES	   0x0200001a	// reentrant
-#define  SN_SAL_GET_FIT_COMPT			   0x0200001b	// reentrant
-#define  SN_SAL_GET_SAPIC_INFO                     0x0200001d
-#define  SN_SAL_GET_SN_INFO                        0x0200001e
-#define  SN_SAL_CONSOLE_PUTC                       0x02000021
-#define  SN_SAL_CONSOLE_GETC                       0x02000022
-#define  SN_SAL_CONSOLE_PUTS                       0x02000023
-#define  SN_SAL_CONSOLE_GETS                       0x02000024
-#define  SN_SAL_CONSOLE_GETS_TIMEOUT               0x02000025
-#define  SN_SAL_CONSOLE_POLL                       0x02000026
-#define  SN_SAL_CONSOLE_INTR                       0x02000027
-#define  SN_SAL_CONSOLE_PUTB			   0x02000028
-#define  SN_SAL_CONSOLE_XMIT_CHARS		   0x0200002a
-#define  SN_SAL_CONSOLE_READC			   0x0200002b
-#define  SN_SAL_SYSCTL_OP			   0x02000030
-#define  SN_SAL_SYSCTL_MODID_GET	           0x02000031
-#define  SN_SAL_SYSCTL_GET                         0x02000032
-#define  SN_SAL_SYSCTL_IOBRICK_MODULE_GET          0x02000033
-#define  SN_SAL_SYSCTL_IO_PORTSPEED_GET            0x02000035
-#define  SN_SAL_SYSCTL_SLAB_GET                    0x02000036
-#define  SN_SAL_BUS_CONFIG		   	   0x02000037
-#define  SN_SAL_SYS_SERIAL_GET			   0x02000038
-#define  SN_SAL_PARTITION_SERIAL_GET		   0x02000039
-#define  SN_SAL_SYSCTL_PARTITION_GET               0x0200003a
-#define  SN_SAL_SYSTEM_POWER_DOWN		   0x0200003b
-#define  SN_SAL_GET_MASTER_BASEIO_NASID		   0x0200003c
-#define  SN_SAL_COHERENCE                          0x0200003d
 #define  SN_SAL_MEMPROTECT                         0x0200003e
-#define  SN_SAL_SYSCTL_FRU_CAPTURE		   0x0200003f
-
-#define  SN_SAL_SYSCTL_IOBRICK_PCI_OP		   0x02000042	// reentrant
-#define	 SN_SAL_IROUTER_OP			   0x02000043
-#define  SN_SAL_SYSCTL_EVENT                       0x02000044
-#define  SN_SAL_IOIF_INTERRUPT			   0x0200004a
-#define  SN_SAL_HWPERF_OP			   0x02000050   // lock
-#define  SN_SAL_IOIF_ERROR_INTERRUPT		   0x02000051
-#define  SN_SAL_IOIF_PCI_SAFE			   0x02000052
-#define  SN_SAL_IOIF_SLOT_ENABLE		   0x02000053
-#define  SN_SAL_IOIF_SLOT_DISABLE		   0x02000054
-#define  SN_SAL_IOIF_GET_HUBDEV_INFO		   0x02000055
-#define  SN_SAL_IOIF_GET_PCIBUS_INFO		   0x02000056
-#define  SN_SAL_IOIF_GET_PCIDEV_INFO		   0x02000057
-#define  SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST	   0x02000058	// deprecated
-#define  SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST	   0x0200005a
-
-#define SN_SAL_IOIF_INIT			   0x0200005f
-#define SN_SAL_HUB_ERROR_INTERRUPT		   0x02000060
-#define SN_SAL_BTE_RECOVER			   0x02000061
-#define SN_SAL_RESERVED_DO_NOT_USE		   0x02000062
-#define SN_SAL_IOIF_GET_PCI_TOPOLOGY		   0x02000064
-
-#define  SN_SAL_GET_PROM_FEATURE_SET		   0x02000065
-#define  SN_SAL_SET_OS_FEATURE_SET		   0x02000066
-#define  SN_SAL_INJECT_ERROR			   0x02000067
-#define  SN_SAL_SET_CPU_NUMBER			   0x02000068
 
-#define  SN_SAL_KERNEL_LAUNCH_EVENT		   0x02000069
 #define  SN_SAL_WATCHLIST_ALLOC			   0x02000070
 #define  SN_SAL_WATCHLIST_FREE			   0x02000071
 
 /*
- * Service-specific constants
- */
-
-/* Console interrupt manipulation */
-	/* action codes */
-#define SAL_CONSOLE_INTR_OFF    0       /* turn the interrupt off */
-#define SAL_CONSOLE_INTR_ON     1       /* turn the interrupt on */
-#define SAL_CONSOLE_INTR_STATUS 2	/* retrieve the interrupt status */
-	/* interrupt specification & status return codes */
-#define SAL_CONSOLE_INTR_XMIT	1	/* output interrupt */
-#define SAL_CONSOLE_INTR_RECV	2	/* input interrupt */
-
-/* interrupt handling */
-#define SAL_INTR_ALLOC		1
-#define SAL_INTR_FREE		2
-#define SAL_INTR_REDIRECT	3
-
-/*
- * operations available on the generic SN_SAL_SYSCTL_OP
- * runtime service
- */
-#define SAL_SYSCTL_OP_IOBOARD		0x0001  /*  retrieve board type */
-#define SAL_SYSCTL_OP_TIO_JLCK_RST      0x0002  /* issue TIO clock reset */
-
-/*
- * IRouter (i.e. generalized system controller) operations
- */
-#define SAL_IROUTER_OPEN	0	/* open a subchannel */
-#define SAL_IROUTER_CLOSE	1	/* close a subchannel */
-#define SAL_IROUTER_SEND	2	/* send part of an IRouter packet */
-#define SAL_IROUTER_RECV	3	/* receive part of an IRouter packet */
-#define SAL_IROUTER_INTR_STATUS	4	/* check the interrupt status for
-					 * an open subchannel
-					 */
-#define SAL_IROUTER_INTR_ON	5	/* enable an interrupt */
-#define SAL_IROUTER_INTR_OFF	6	/* disable an interrupt */
-#define SAL_IROUTER_INIT	7	/* initialize IRouter driver */
-
-/* IRouter interrupt mask bits */
-#define SAL_IROUTER_INTR_XMIT	SAL_CONSOLE_INTR_XMIT
-#define SAL_IROUTER_INTR_RECV	SAL_CONSOLE_INTR_RECV
-
-/*
- * Error Handling Features
- */
-#define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV	0x1	// obsolete
-#define SAL_ERR_FEAT_LOG_SBES			0x2	// obsolete
-#define SAL_ERR_FEAT_MFR_OVERRIDE		0x4
-#define SAL_ERR_FEAT_SBE_THRESHOLD		0xffff0000
-
-/*
  * SAL Error Codes
  */
 #define SALRET_MORE_PASSES	1
@@ -153,458 +30,6 @@
 #define SALRET_INVALID_ARG	(-2)
 #define SALRET_ERROR		(-3)
 
-#define SN_SAL_FAKE_PROM			   0x02009999
-
-/**
-  * sn_sal_revision - get the SGI SAL revision number
-  *
-  * The SGI PROM stores its version in the sal_[ab]_rev_(major|minor).
-  * This routine simply extracts the major and minor values and
-  * presents them in a u32 format.
-  *
-  * For example, version 4.05 would be represented at 0x0405.
-  */
-static inline u32
-sn_sal_rev(void)
-{
-	struct ia64_sal_systab *systab = __va(efi.sal_systab);
-
-	return (u32)(systab->sal_b_rev_major << 8 | systab->sal_b_rev_minor);
-}
-
-/*
- * Returns the master console nasid, if the call fails, return an illegal
- * value.
- */
-static inline u64
-ia64_sn_get_console_nasid(void)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0);
-
-	if (ret_stuff.status < 0)
-		return ret_stuff.status;
-
-	/* Master console nasid is in 'v0' */
-	return ret_stuff.v0;
-}
-
-/*
- * Returns the master baseio nasid, if the call fails, return an illegal
- * value.
- */
-static inline u64
-ia64_sn_get_master_baseio_nasid(void)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0);
-
-	if (ret_stuff.status < 0)
-		return ret_stuff.status;
-
-	/* Master baseio nasid is in 'v0' */
-	return ret_stuff.v0;
-}
-
-static inline void *
-ia64_sn_get_klconfig_addr(nasid_t nasid)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
-	return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
-}
-
-/*
- * Returns the next console character.
- */
-static inline u64
-ia64_sn_console_getc(int *ch)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0);
-
-	/* character is in 'v0' */
-	*ch = (int)ret_stuff.v0;
-
-	return ret_stuff.status;
-}
-
-/*
- * Read a character from the SAL console device, after a previous interrupt
- * or poll operation has given us to know that a character is available
- * to be read.
- */
-static inline u64
-ia64_sn_console_readc(void)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_READC, 0, 0, 0, 0, 0, 0, 0);
-
-	/* character is in 'v0' */
-	return ret_stuff.v0;
-}
-
-/*
- * Sends the given character to the console.
- */
-static inline u64
-ia64_sn_console_putc(char ch)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
-
-	return ret_stuff.status;
-}
-
-/*
- * Sends the given buffer to the console.
- */
-static inline u64
-ia64_sn_console_putb(const char *buf, int len)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0; 
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
-
-	if ( ret_stuff.status == 0 ) {
-		return ret_stuff.v0;
-	}
-	return (u64)0;
-}
-
-/*
- * Print a platform error record
- */
-static inline u64
-ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
-
-	return ret_stuff.status;
-}
-
-/*
- * Check for Platform errors
- */
-static inline u64
-ia64_sn_plat_cpei_handler(void)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0);
-
-	return ret_stuff.status;
-}
-
-/*
- * Set Error Handling Features	(Obsolete)
- */
-static inline u64
-ia64_sn_plat_set_error_handling_features(void)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES,
-		SAL_ERR_FEAT_LOG_SBES,
-		0, 0, 0, 0, 0, 0);
-
-	return ret_stuff.status;
-}
-
-/*
- * Checks for console input.
- */
-static inline u64
-ia64_sn_console_check(int *result)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0);
-
-	/* result is in 'v0' */
-	*result = (int)ret_stuff.v0;
-
-	return ret_stuff.status;
-}
-
-/*
- * Checks console interrupt status
- */
-static inline u64
-ia64_sn_console_intr_status(void)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
-		 0, SAL_CONSOLE_INTR_STATUS,
-		 0, 0, 0, 0, 0);
-
-	if (ret_stuff.status == 0) {
-	    return ret_stuff.v0;
-	}
-	
-	return 0;
-}
-
-/*
- * Enable an interrupt on the SAL console device.
- */
-static inline void
-ia64_sn_console_intr_enable(u64 intr)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
-		 intr, SAL_CONSOLE_INTR_ON,
-		 0, 0, 0, 0, 0);
-}
-
-/*
- * Disable an interrupt on the SAL console device.
- */
-static inline void
-ia64_sn_console_intr_disable(u64 intr)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
-		 intr, SAL_CONSOLE_INTR_OFF,
-		 0, 0, 0, 0, 0);
-}
-
-/*
- * Sends a character buffer to the console asynchronously.
- */
-static inline u64
-ia64_sn_console_xmit_chars(char *buf, int len)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
-		 (u64)buf, (u64)len,
-		 0, 0, 0, 0, 0);
-
-	if (ret_stuff.status == 0) {
-	    return ret_stuff.v0;
-	}
-
-	return 0;
-}
-
-/*
- * Returns the iobrick module Id
- */
-static inline u64
-ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0);
-
-	/* result is in 'v0' */
-	*result = (int)ret_stuff.v0;
-
-	return ret_stuff.status;
-}
-
-/**
- * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function
- *
- * SN_SAL_POD_MODE actually takes an argument, but it's always
- * 0 when we call it from the kernel, so we don't have to expose
- * it to the caller.
- */
-static inline u64
-ia64_sn_pod_mode(void)
-{
-	struct ia64_sal_retval isrv;
-	SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
-	if (isrv.status)
-		return 0;
-	return isrv.v0;
-}
-
-/**
- * ia64_sn_probe_mem - read from memory safely
- * @addr: address to probe
- * @size: number bytes to read (1,2,4,8)
- * @data_ptr: address to store value read by probe (-1 returned if probe fails)
- *
- * Call into the SAL to do a memory read.  If the read generates a machine
- * check, this routine will recover gracefully and return -1 to the caller.
- * @addr is usually a kernel virtual address in uncached space (i.e. the
- * address starts with 0xc), but if called in physical mode, @addr should
- * be a physical address.
- *
- * Return values:
- *  0 - probe successful
- *  1 - probe failed (generated MCA)
- *  2 - Bad arg
- * <0 - PAL error
- */
-static inline u64
-ia64_sn_probe_mem(long addr, long size, void *data_ptr)
-{
-	struct ia64_sal_retval isrv;
-
-	SAL_CALL(isrv, SN_SAL_PROBE, addr, size, 0, 0, 0, 0, 0);
-
-	if (data_ptr) {
-		switch (size) {
-		case 1:
-			*((u8*)data_ptr) = (u8)isrv.v0;
-			break;
-		case 2:
-			*((u16*)data_ptr) = (u16)isrv.v0;
-			break;
-		case 4:
-			*((u32*)data_ptr) = (u32)isrv.v0;
-			break;
-		case 8:
-			*((u64*)data_ptr) = (u64)isrv.v0;
-			break;
-		default:
-			isrv.status = 2;
-		}
-	}
-	return isrv.status;
-}
-
-/*
- * Retrieve the system serial number as an ASCII string.
- */
-static inline u64
-ia64_sn_sys_serial_get(char *buf)
-{
-	struct ia64_sal_retval ret_stuff;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0);
-	return ret_stuff.status;
-}
-
-extern char sn_system_serial_number_string[];
-extern u64 sn_partition_serial_number;
-
-static inline char *
-sn_system_serial_number(void) {
-	if (sn_system_serial_number_string[0]) {
-		return(sn_system_serial_number_string);
-	} else {
-		ia64_sn_sys_serial_get(sn_system_serial_number_string);
-		return(sn_system_serial_number_string);
-	}
-}
-	
-
-/*
- * Returns a unique id number for this system and partition (suitable for
- * use with license managers), based in part on the system serial number.
- */
-static inline u64
-ia64_sn_partition_serial_get(void)
-{
-	struct ia64_sal_retval ret_stuff;
-	ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0,
-				   0, 0, 0, 0, 0, 0);
-	if (ret_stuff.status != 0)
-	    return 0;
-	return ret_stuff.v0;
-}
-
-static inline u64
-sn_partition_serial_number_val(void) {
-	if (unlikely(sn_partition_serial_number == 0)) {
-		sn_partition_serial_number = ia64_sn_partition_serial_get();
-	}
-	return sn_partition_serial_number;
-}
-
-/*
- * Returns the partition id of the nasid passed in as an argument,
- * or INVALID_PARTID if the partition id cannot be retrieved.
- */
-static inline partid_t
-ia64_sn_sysctl_partition_get(nasid_t nasid)
-{
-	struct ia64_sal_retval ret_stuff;
-	SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
-		0, 0, 0, 0, 0, 0);
-	if (ret_stuff.status != 0)
-	    return -1;
-	return ((partid_t)ret_stuff.v0);
-}
-
 /*
  * Returns the physical address of the partition's reserved page through
  * an iterative number of calls.
@@ -634,96 +59,6 @@ sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len)
 }
 
 /*
- * Register or unregister a physical address range being referenced across
- * a partition boundary for which certain SAL errors should be scanned for,
- * cleaned up and ignored.  This is of value for kernel partitioning code only.
- * Values for the operation argument:
- *	1 = register this address range with SAL
- *	0 = unregister this address range with SAL
- * 
- * SAL maintains a reference count on an address range in case it is registered
- * multiple times.
- * 
- * On success, returns the reference count of the address range after the SAL
- * call has performed the current registration/unregistration.  Returns a
- * negative value if an error occurred.
- */
-static inline int
-sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
-{
-	struct ia64_sal_retval ret_stuff;
-	ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len,
-			 (u64)operation, 0, 0, 0, 0);
-	return ret_stuff.status;
-}
-
-/*
- * Register or unregister an instruction range for which SAL errors should
- * be ignored.  If an error occurs while in the registered range, SAL jumps
- * to return_addr after ignoring the error.  Values for the operation argument:
- *	1 = register this instruction range with SAL
- *	0 = unregister this instruction range with SAL
- *
- * Returns 0 on success, or a negative value if an error occurred.
- */
-static inline int
-sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
-			 int virtual, int operation)
-{
-	struct ia64_sal_retval ret_stuff;
-	u64 call;
-	if (virtual) {
-		call = SN_SAL_NO_FAULT_ZONE_VIRTUAL;
-	} else {
-		call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
-	}
-	ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr,
-			 (u64)1, 0, 0, 0);
-	return ret_stuff.status;
-}
-
-/*
- * Register or unregister a function to handle a PMI received by a CPU.
- * Before calling the registered handler, SAL sets r1 to the value that
- * was passed in as the global_pointer.
- *
- * If the handler pointer is NULL, then the currently registered handler
- * will be unregistered.
- *
- * Returns 0 on success, or a negative value if an error occurred.
- */
-static inline int
-sn_register_pmi_handler(u64 handler, u64 global_pointer)
-{
-	struct ia64_sal_retval ret_stuff;
-	ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler,
-			 global_pointer, 0, 0, 0, 0, 0);
-	return ret_stuff.status;
-}
-
-/*
- * Change or query the coherence domain for this partition. Each cpu-based
- * nasid is represented by a bit in an array of 64-bit words:
- *      0 = not in this partition's coherency domain
- *      1 = in this partition's coherency domain
- *
- * It is not possible for the local system's nasids to be removed from
- * the coherency domain.  Purpose of the domain arguments:
- *      new_domain = set the coherence domain to the given nasids
- *      old_domain = return the current coherence domain
- *
- * Returns 0 on success, or a negative value if an error occurred.
- */
-static inline int
-sn_change_coherence(u64 *new_domain, u64 *old_domain)
-{
-	struct ia64_sal_retval ret_stuff;
-	ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
-				(u64)old_domain, 0, 0, 0, 0, 0);
-	return ret_stuff.status;
-}
-
-/*
  * Change memory access protections for a physical address range.
  * nasid_array is not used on Altix, but may be in future architectures.
  * Available memory protection access classes are defined after the function.
@@ -744,450 +79,6 @@ sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
 #define SN_MEMPROT_ACCESS_CLASS_6		0x084080
 #define SN_MEMPROT_ACCESS_CLASS_7		0x021080
 
-/*
- * Turns off system power.
- */
-static inline void
-ia64_sn_power_down(void)
-{
-	struct ia64_sal_retval ret_stuff;
-	SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
-	while(1)
-		cpu_relax();
-	/* never returns */
-}
-
-/**
- * ia64_sn_fru_capture - tell the system controller to capture hw state
- *
- * This routine will call the SAL which will tell the system controller(s)
- * to capture hw mmr information from each SHub in the system.
- */
-static inline u64
-ia64_sn_fru_capture(void)
-{
-        struct ia64_sal_retval isrv;
-        SAL_CALL(isrv, SN_SAL_SYSCTL_FRU_CAPTURE, 0, 0, 0, 0, 0, 0, 0);
-        if (isrv.status)
-                return 0;
-        return isrv.v0;
-}
-
-/*
- * Performs an operation on a PCI bus or slot -- power up, power down
- * or reset.
- */
-static inline u64
-ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type, 
-			      u64 bus, char slot, 
-			      u64 action)
-{
-	struct ia64_sal_retval rv = {0, 0, 0, 0};
-
-	SAL_CALL_NOLOCK(rv, SN_SAL_SYSCTL_IOBRICK_PCI_OP, connection_type, n, action,
-		 bus, (u64) slot, 0, 0);
-	if (rv.status)
-	    	return rv.v0;
-	return 0;
-}
-
-
-/*
- * Open a subchannel for sending arbitrary data to the system
- * controller network via the system controller device associated with
- * 'nasid'.  Return the subchannel number or a negative error code.
- */
-static inline int
-ia64_sn_irtr_open(nasid_t nasid)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_OPEN, nasid,
-			   0, 0, 0, 0, 0);
-	return (int) rv.v0;
-}
-
-/*
- * Close system controller subchannel 'subch' previously opened on 'nasid'.
- */
-static inline int
-ia64_sn_irtr_close(nasid_t nasid, int subch)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_CLOSE,
-			   (u64) nasid, (u64) subch, 0, 0, 0, 0);
-	return (int) rv.status;
-}
-
-/*
- * Read data from system controller associated with 'nasid' on
- * subchannel 'subch'.  The buffer to be filled is pointed to by
- * 'buf', and its capacity is in the integer pointed to by 'len'.  The
- * referent of 'len' is set to the number of bytes read by the SAL
- * call.  The return value is either SALRET_OK (for bytes read) or
- * SALRET_ERROR (for error or "no data available").
- */
-static inline int
-ia64_sn_irtr_recv(nasid_t nasid, int subch, char *buf, int *len)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_RECV,
-			   (u64) nasid, (u64) subch, (u64) buf, (u64) len,
-			   0, 0);
-	return (int) rv.status;
-}
-
-/*
- * Write data to the system controller network via the system
- * controller associated with 'nasid' on suchannel 'subch'.  The
- * buffer to be written out is pointed to by 'buf', and 'len' is the
- * number of bytes to be written.  The return value is either the
- * number of bytes written (which could be zero) or a negative error
- * code.
- */
-static inline int
-ia64_sn_irtr_send(nasid_t nasid, int subch, char *buf, int len)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_SEND,
-			   (u64) nasid, (u64) subch, (u64) buf, (u64) len,
-			   0, 0);
-	return (int) rv.v0;
-}
-
-/*
- * Check whether any interrupts are pending for the system controller
- * associated with 'nasid' and its subchannel 'subch'.  The return
- * value is a mask of pending interrupts (SAL_IROUTER_INTR_XMIT and/or
- * SAL_IROUTER_INTR_RECV).
- */
-static inline int
-ia64_sn_irtr_intr(nasid_t nasid, int subch)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_STATUS,
-			   (u64) nasid, (u64) subch, 0, 0, 0, 0);
-	return (int) rv.v0;
-}
-
-/*
- * Enable the interrupt indicated by the intr parameter (either
- * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
- */
-static inline int
-ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_ON,
-			   (u64) nasid, (u64) subch, intr, 0, 0, 0);
-	return (int) rv.v0;
-}
-
-/*
- * Disable the interrupt indicated by the intr parameter (either
- * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
- */
-static inline int
-ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_OFF,
-			   (u64) nasid, (u64) subch, intr, 0, 0, 0);
-	return (int) rv.v0;
-}
-
-/*
- * Set up a node as the point of contact for system controller
- * environmental event delivery.
- */
-static inline int
-ia64_sn_sysctl_event_init(nasid_t nasid)
-{
-        struct ia64_sal_retval rv;
-        SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
-			   0, 0, 0, 0, 0, 0);
-        return (int) rv.v0;
-}
-
-/*
- * Ask the system controller on the specified nasid to reset
- * the CX corelet clock.  Only valid on TIO nodes.
- */
-static inline int
-ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
-			nasid, 0, 0, 0, 0, 0);
-	if (rv.status != 0)
-		return (int)rv.status;
-	if (rv.v0 != 0)
-		return (int)rv.v0;
-
-	return 0;
-}
-
-/*
- * Get the associated ioboard type for a given nasid.
- */
-static inline long
-ia64_sn_sysctl_ioboard_get(nasid_t nasid, u16 *ioboard)
-{
-	struct ia64_sal_retval isrv;
-	SAL_CALL_REENTRANT(isrv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
-			   nasid, 0, 0, 0, 0, 0);
-	if (isrv.v0 != 0) {
-		*ioboard = isrv.v0;
-		return isrv.status;
-	}
-	if (isrv.v1 != 0) {
-		*ioboard = isrv.v1;
-		return isrv.status;
-	}
-
-	return isrv.status;
-}
-
-/**
- * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
- * @nasid: NASID of node to read
- * @index: FIT entry index to be retrieved (0..n)
- * @fitentry: 16 byte buffer where FIT entry will be stored.
- * @banbuf: optional buffer for retrieving banner
- * @banlen: length of banner buffer
- *
- * Access to the physical PROM chips needs to be serialized since reads and
- * writes can't occur at the same time, so we need to call into the SAL when
- * we want to look at the FIT entries on the chips.
- *
- * Returns:
- *	%SALRET_OK if ok
- *	%SALRET_INVALID_ARG if index too big
- *	%SALRET_NOT_IMPLEMENTED if running on older PROM
- *	??? if nasid invalid OR banner buffer not large enough
- */
-static inline int
-ia64_sn_get_fit_compt(u64 nasid, u64 index, void *fitentry, void *banbuf,
-		      u64 banlen)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_NOLOCK(rv, SN_SAL_GET_FIT_COMPT, nasid, index, fitentry,
-			banbuf, banlen, 0, 0);
-	return (int) rv.status;
-}
-
-/*
- * Initialize the SAL components of the system controller
- * communication driver; specifically pass in a sizable buffer that
- * can be used for allocation of subchannel queues as new subchannels
- * are opened.  "buf" points to the buffer, and "len" specifies its
- * length.
- */
-static inline int
-ia64_sn_irtr_init(nasid_t nasid, void *buf, int len)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INIT,
-			   (u64) nasid, (u64) buf, (u64) len, 0, 0, 0);
-	return (int) rv.status;
-}
-
-/*
- * Returns the nasid, subnode & slice corresponding to a SAPIC ID
- *
- *  In:
- *	arg0 - SN_SAL_GET_SAPIC_INFO
- *	arg1 - sapicid (lid >> 16) 
- *  Out:
- *	v0 - nasid
- *	v1 - subnode
- *	v2 - slice
- */
-static inline u64
-ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SAPIC_INFO, sapicid, 0, 0, 0, 0, 0, 0);
-
-/***** BEGIN HACK - temp til old proms no longer supported ********/
-	if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
-		if (nasid) *nasid = sapicid & 0xfff;
-		if (subnode) *subnode = (sapicid >> 13) & 1;
-		if (slice) *slice = (sapicid >> 12) & 3;
-		return 0;
-	}
-/***** END HACK *******/
-
-	if (ret_stuff.status < 0)
-		return ret_stuff.status;
-
-	if (nasid) *nasid = (int) ret_stuff.v0;
-	if (subnode) *subnode = (int) ret_stuff.v1;
-	if (slice) *slice = (int) ret_stuff.v2;
-	return 0;
-}
- 
-/*
- * Returns information about the HUB/SHUB.
- *  In:
- *	arg0 - SN_SAL_GET_SN_INFO
- * 	arg1 - 0 (other values reserved for future use)
- *  Out:
- *	v0 
- *		[7:0]   - shub type (0=shub1, 1=shub2)
- *		[15:8]  - Log2 max number of nodes in entire system (includes
- *			  C-bricks, I-bricks, etc)
- *		[23:16] - Log2 of nodes per sharing domain			 
- * 		[31:24] - partition ID
- * 		[39:32] - coherency_id
- * 		[47:40] - regionsize
- *	v1 
- *		[15:0]  - nasid mask (ex., 0x7ff for 11 bit nasid)
- *	 	[23:15] - bit position of low nasid bit
- */
-static inline u64
-ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift, 
-		u8 *systemsize, u8 *sharing_domain_size, u8 *partid, u8 *coher, u8 *reg)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	ret_stuff.v1 = 0;
-	ret_stuff.v2 = 0;
-	SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
-
-/***** BEGIN HACK - temp til old proms no longer supported ********/
-	if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
-		int nasid = get_sapicid() & 0xfff;
-#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL
-#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
-		if (shubtype) *shubtype = 0;
-		if (nasid_bitmask) *nasid_bitmask = 0x7ff;
-		if (nasid_shift) *nasid_shift = 38;
-		if (systemsize) *systemsize = 10;
-		if (sharing_domain_size) *sharing_domain_size = 8;
-		if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
-		if (coher) *coher = nasid >> 9;
-		if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
-			SH_SHUB_ID_NODES_PER_BIT_SHFT;
-		return 0;
-	}
-/***** END HACK *******/
-
-	if (ret_stuff.status < 0)
-		return ret_stuff.status;
-
-	if (shubtype) *shubtype = ret_stuff.v0 & 0xff;
-	if (systemsize) *systemsize = (ret_stuff.v0 >> 8) & 0xff;
-	if (sharing_domain_size) *sharing_domain_size = (ret_stuff.v0 >> 16) & 0xff;
-	if (partid) *partid = (ret_stuff.v0 >> 24) & 0xff;
-	if (coher) *coher = (ret_stuff.v0 >> 32) & 0xff;
-	if (reg) *reg = (ret_stuff.v0 >> 40) & 0xff;
-	if (nasid_bitmask) *nasid_bitmask = (ret_stuff.v1 & 0xffff);
-	if (nasid_shift) *nasid_shift = (ret_stuff.v1 >> 16) & 0xff;
-	return 0;
-}
- 
-/*
- * This is the access point to the Altix PROM hardware performance
- * and status monitoring interface. For info on using this, see
- * arch/ia64/include/asm/sn/sn2/sn_hwperf.h
- */
-static inline int
-ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
-                  u64 a3, u64 a4, int *v0)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_NOLOCK(rv, SN_SAL_HWPERF_OP, (u64)nasid,
-		opcode, a0, a1, a2, a3, a4);
-	if (v0)
-		*v0 = (int) rv.v0;
-	return (int) rv.status;
-}
-
-static inline int
-ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
-	return (int) rv.status;
-}
-
-/*
- * BTE error recovery is implemented in SAL
- */
-static inline int
-ia64_sn_bte_recovery(nasid_t nasid)
-{
-	struct ia64_sal_retval rv;
-
-	rv.status = 0;
-	SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, (u64)nasid, 0, 0, 0, 0, 0, 0);
-	if (rv.status == SALRET_NOT_IMPLEMENTED)
-		return 0;
-	return (int) rv.status;
-}
-
-static inline int
-ia64_sn_is_fake_prom(void)
-{
-	struct ia64_sal_retval rv;
-	SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
-	return (rv.status == 0);
-}
-
-static inline int
-ia64_sn_get_prom_feature_set(int set, unsigned long *feature_set)
-{
-	struct ia64_sal_retval rv;
-
-	SAL_CALL_NOLOCK(rv, SN_SAL_GET_PROM_FEATURE_SET, set, 0, 0, 0, 0, 0, 0);
-	if (rv.status != 0)
-		return rv.status;
-	*feature_set = rv.v0;
-	return 0;
-}
-
-static inline int
-ia64_sn_set_os_feature(int feature)
-{
-	struct ia64_sal_retval rv;
-
-	SAL_CALL_NOLOCK(rv, SN_SAL_SET_OS_FEATURE_SET, feature, 0, 0, 0, 0, 0, 0);
-	return rv.status;
-}
-
-static inline int
-sn_inject_error(u64 paddr, u64 *data, u64 *ecc)
-{
-	struct ia64_sal_retval ret_stuff;
-
-	ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_INJECT_ERROR, paddr, (u64)data,
-				(u64)ecc, 0, 0, 0, 0);
-	return ret_stuff.status;
-}
-
-static inline int
-ia64_sn_set_cpu_number(int cpu)
-{
-	struct ia64_sal_retval rv;
-
-	SAL_CALL_NOLOCK(rv, SN_SAL_SET_CPU_NUMBER, cpu, 0, 0, 0, 0, 0, 0);
-	return rv.status;
-}
-static inline int
-ia64_sn_kernel_launch_event(void)
-{
- 	struct ia64_sal_retval rv;
-	SAL_CALL_NOLOCK(rv, SN_SAL_KERNEL_LAUNCH_EVENT, 0, 0, 0, 0, 0, 0, 0);
-	return rv.status;
-}
-
 union sn_watchlist_u {
 	u64     val;
 	struct {
diff --git a/arch/ia64/include/asm/sn/tioca.h b/arch/ia64/include/asm/sn/tioca.h
deleted file mode 100644
index 666222d7f0f6..000000000000
--- a/arch/ia64/include/asm/sn/tioca.h
+++ /dev/null
@@ -1,596 +0,0 @@
-#ifndef _ASM_IA64_SN_TIO_TIOCA_H
-#define _ASM_IA64_SN_TIO_TIOCA_H
-
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-
-#define TIOCA_PART_NUM	0xE020
-#define TIOCA_MFGR_NUM	0x24
-#define TIOCA_REV_A	0x1
-
-/*
- * Register layout for TIO:CA.  See below for bitmasks for each register.
- */
-
-struct tioca {
-	u64	ca_id;				/* 0x000000 */
-	u64	ca_control1;			/* 0x000008 */
-	u64	ca_control2;			/* 0x000010 */
-	u64	ca_status1;			/* 0x000018 */
-	u64	ca_status2;			/* 0x000020 */
-	u64	ca_gart_aperature;		/* 0x000028 */
-	u64	ca_gfx_detach;			/* 0x000030 */
-	u64	ca_inta_dest_addr;		/* 0x000038 */
-	u64	ca_intb_dest_addr;		/* 0x000040 */
-	u64	ca_err_int_dest_addr;		/* 0x000048 */
-	u64	ca_int_status;			/* 0x000050 */
-	u64	ca_int_status_alias;		/* 0x000058 */
-	u64	ca_mult_error;			/* 0x000060 */
-	u64	ca_mult_error_alias;		/* 0x000068 */
-	u64	ca_first_error;			/* 0x000070 */
-	u64	ca_int_mask;			/* 0x000078 */
-	u64	ca_crm_pkterr_type;		/* 0x000080 */
-	u64	ca_crm_pkterr_type_alias;	/* 0x000088 */
-	u64	ca_crm_ct_error_detail_1;	/* 0x000090 */
-	u64	ca_crm_ct_error_detail_2;	/* 0x000098 */
-	u64	ca_crm_tnumto;			/* 0x0000A0 */
-	u64	ca_gart_err;			/* 0x0000A8 */
-	u64	ca_pcierr_type;			/* 0x0000B0 */
-	u64	ca_pcierr_addr;			/* 0x0000B8 */
-
-	u64	ca_pad_0000C0[3];		/* 0x0000{C0..D0} */
-
-	u64	ca_pci_rd_buf_flush;		/* 0x0000D8 */
-	u64	ca_pci_dma_addr_extn;		/* 0x0000E0 */
-	u64	ca_agp_dma_addr_extn;		/* 0x0000E8 */
-	u64	ca_force_inta;			/* 0x0000F0 */
-	u64	ca_force_intb;			/* 0x0000F8 */
-	u64	ca_debug_vector_sel;		/* 0x000100 */
-	u64	ca_debug_mux_core_sel;		/* 0x000108 */
-	u64	ca_debug_mux_pci_sel;		/* 0x000110 */
-	u64	ca_debug_domain_sel;		/* 0x000118 */
-
-	u64	ca_pad_000120[28];		/* 0x0001{20..F8} */
-
-	u64	ca_gart_ptr_table;		/* 0x200 */
-	u64	ca_gart_tlb_addr[8];		/* 0x2{08..40} */
-};
-
-/*
- * Mask/shift definitions for TIO:CA registers.  The convention here is
- * to mainly use the names as they appear in the "TIO AEGIS Programmers'
- * Reference" with a CA_ prefix added.  Some exceptions were made to fix
- * duplicate field names or to generalize fields that are common to
- * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for
- * example).
- *
- * Fields consisting of a single bit have a single #define have a single
- * macro declaration to mask the bit.  Fields consisting of multiple bits
- * have two declarations: one to mask the proper bits in a register, and 
- * a second with the suffix "_SHFT" to identify how far the mask needs to
- * be shifted right to get its base value.
- */
-
-/* ==== ca_control1 */
-#define CA_SYS_BIG_END			(1ull << 0)
-#define CA_DMA_AGP_SWAP			(1ull << 1)
-#define CA_DMA_PCI_SWAP			(1ull << 2)
-#define CA_PIO_IO_SWAP			(1ull << 3)
-#define CA_PIO_MEM_SWAP			(1ull << 4)
-#define CA_GFX_WR_SWAP			(1ull << 5)
-#define CA_AGP_FW_ENABLE		(1ull << 6)
-#define CA_AGP_CAL_CYCLE		(0x7ull << 7)
-#define CA_AGP_CAL_CYCLE_SHFT		7
-#define CA_AGP_CAL_PRSCL_BYP		(1ull << 10)
-#define CA_AGP_INIT_CAL_ENB		(1ull << 11)
-#define CA_INJ_ADDR_PERR		(1ull << 12)
-#define CA_INJ_DATA_PERR		(1ull << 13)
-	/* bits 15:14 unused */
-#define CA_PCIM_IO_NBE_AD		(0x7ull << 16)
-#define CA_PCIM_IO_NBE_AD_SHFT		16
-#define CA_PCIM_FAST_BTB_ENB		(1ull << 19)
-	/* bits 23:20 unused */
-#define CA_PIO_ADDR_OFFSET		(0xffull << 24)
-#define CA_PIO_ADDR_OFFSET_SHFT		24
-	/* bits 35:32 unused */
-#define CA_AGPDMA_OP_COMBDELAY		(0x1full << 36)
-#define CA_AGPDMA_OP_COMBDELAY_SHFT	36
-	/* bit 41 unused */
-#define CA_AGPDMA_OP_ENB_COMBDELAY	(1ull << 42)
-#define	CA_PCI_INT_LPCNT		(0xffull << 44)
-#define CA_PCI_INT_LPCNT_SHFT		44
-	/* bits 63:52 unused */
-
-/* ==== ca_control2 */
-#define CA_AGP_LATENCY_TO		(0xffull << 0)
-#define CA_AGP_LATENCY_TO_SHFT		0
-#define CA_PCI_LATENCY_TO		(0xffull << 8)
-#define CA_PCI_LATENCY_TO_SHFT		8
-#define CA_PCI_MAX_RETRY		(0x3ffull << 16)
-#define CA_PCI_MAX_RETRY_SHFT		16
-	/* bits 27:26 unused */
-#define CA_RT_INT_EN			(0x3ull << 28)
-#define CA_RT_INT_EN_SHFT			28
-#define CA_MSI_INT_ENB			(1ull << 30)
-#define CA_PCI_ARB_ERR_ENB		(1ull << 31)
-#define CA_GART_MEM_PARAM		(0x3ull << 32)
-#define CA_GART_MEM_PARAM_SHFT		32
-#define CA_GART_RD_PREFETCH_ENB		(1ull << 34)
-#define CA_GART_WR_PREFETCH_ENB		(1ull << 35)
-#define CA_GART_FLUSH_TLB		(1ull << 36)
-	/* bits 39:37 unused */
-#define CA_CRM_TNUMTO_PERIOD		(0x1fffull << 40)
-#define CA_CRM_TNUMTO_PERIOD_SHFT	40
-	/* bits 55:53 unused */
-#define CA_CRM_TNUMTO_ENB		(1ull << 56)
-#define CA_CRM_PRESCALER_BYP		(1ull << 57)
-	/* bits 59:58 unused */
-#define CA_CRM_MAX_CREDIT		(0x7ull << 60)
-#define CA_CRM_MAX_CREDIT_SHFT		60
-	/* bit 63 unused */
-
-/* ==== ca_status1 */
-#define CA_CORELET_ID			(0x3ull << 0)
-#define CA_CORELET_ID_SHFT		0
-#define CA_INTA_N			(1ull << 2)
-#define CA_INTB_N			(1ull << 3)
-#define CA_CRM_CREDIT_AVAIL		(0x7ull << 4)
-#define CA_CRM_CREDIT_AVAIL_SHFT	4
-	/* bit 7 unused */
-#define CA_CRM_SPACE_AVAIL		(0x7full << 8)
-#define CA_CRM_SPACE_AVAIL_SHFT		8
-	/* bit 15 unused */
-#define CA_GART_TLB_VAL			(0xffull << 16)
-#define CA_GART_TLB_VAL_SHFT		16
-	/* bits 63:24 unused */
-
-/* ==== ca_status2 */
-#define CA_GFX_CREDIT_AVAIL		(0xffull << 0)
-#define CA_GFX_CREDIT_AVAIL_SHFT	0
-#define CA_GFX_OPQ_AVAIL		(0xffull << 8)
-#define CA_GFX_OPQ_AVAIL_SHFT		8
-#define CA_GFX_WRBUFF_AVAIL		(0xffull << 16)
-#define CA_GFX_WRBUFF_AVAIL_SHFT	16
-#define CA_ADMA_OPQ_AVAIL		(0xffull << 24)
-#define CA_ADMA_OPQ_AVAIL_SHFT		24
-#define CA_ADMA_WRBUFF_AVAIL		(0xffull << 32)
-#define CA_ADMA_WRBUFF_AVAIL_SHFT	32
-#define CA_ADMA_RDBUFF_AVAIL		(0x7full << 40)
-#define CA_ADMA_RDBUFF_AVAIL_SHFT	40
-#define CA_PCI_PIO_OP_STAT		(1ull << 47)
-#define CA_PDMA_OPQ_AVAIL		(0xfull << 48)
-#define CA_PDMA_OPQ_AVAIL_SHFT		48
-#define CA_PDMA_WRBUFF_AVAIL		(0xfull << 52)
-#define CA_PDMA_WRBUFF_AVAIL_SHFT	52
-#define CA_PDMA_RDBUFF_AVAIL		(0x3ull << 56)
-#define CA_PDMA_RDBUFF_AVAIL_SHFT	56
-	/* bits 63:58 unused */
-
-/* ==== ca_gart_aperature */
-#define CA_GART_AP_ENB_AGP		(1ull << 0)
-#define CA_GART_PAGE_SIZE		(1ull << 1)
-#define CA_GART_AP_ENB_PCI		(1ull << 2)
-	/* bits 11:3 unused */
-#define CA_GART_AP_SIZE			(0x3ffull << 12)
-#define CA_GART_AP_SIZE_SHFT		12
-#define CA_GART_AP_BASE			(0x3ffffffffffull << 22)
-#define CA_GART_AP_BASE_SHFT		22
-
-/* ==== ca_inta_dest_addr
-   ==== ca_intb_dest_addr 
-   ==== ca_err_int_dest_addr */
-	/* bits 2:0 unused */
-#define CA_INT_DEST_ADDR		(0x7ffffffffffffull << 3)
-#define CA_INT_DEST_ADDR_SHFT		3
-	/* bits 55:54 unused */
-#define CA_INT_DEST_VECT		(0xffull << 56)
-#define CA_INT_DEST_VECT_SHFT		56
-
-/* ==== ca_int_status */
-/* ==== ca_int_status_alias */
-/* ==== ca_mult_error */
-/* ==== ca_mult_error_alias */
-/* ==== ca_first_error */
-/* ==== ca_int_mask */
-#define CA_PCI_ERR			(1ull << 0)
-	/* bits 3:1 unused */
-#define CA_GART_FETCH_ERR		(1ull << 4)
-#define CA_GFX_WR_OVFLW			(1ull << 5)
-#define CA_PIO_REQ_OVFLW		(1ull << 6)
-#define CA_CRM_PKTERR			(1ull << 7)
-#define CA_CRM_DVERR			(1ull << 8)
-#define CA_TNUMTO			(1ull << 9)
-#define CA_CXM_RSP_CRED_OVFLW		(1ull << 10)
-#define CA_CXM_REQ_CRED_OVFLW		(1ull << 11)
-#define CA_PIO_INVALID_ADDR		(1ull << 12)
-#define CA_PCI_ARB_TO			(1ull << 13)
-#define CA_AGP_REQ_OFLOW		(1ull << 14)
-#define CA_SBA_TYPE1_ERR		(1ull << 15)
-	/* bit 16 unused */
-#define CA_INTA				(1ull << 17)
-#define CA_INTB				(1ull << 18)
-#define CA_MULT_INTA			(1ull << 19)
-#define CA_MULT_INTB			(1ull << 20)
-#define CA_GFX_CREDIT_OVFLW		(1ull << 21)
-	/* bits 63:22 unused */
-
-/* ==== ca_crm_pkterr_type */
-/* ==== ca_crm_pkterr_type_alias */
-#define CA_CRM_PKTERR_SBERR_HDR		(1ull << 0)
-#define CA_CRM_PKTERR_DIDN		(1ull << 1)
-#define CA_CRM_PKTERR_PACTYPE		(1ull << 2)
-#define CA_CRM_PKTERR_INV_TNUM		(1ull << 3)
-#define CA_CRM_PKTERR_ADDR_RNG		(1ull << 4)
-#define CA_CRM_PKTERR_ADDR_ALGN		(1ull << 5)
-#define CA_CRM_PKTERR_HDR_PARAM		(1ull << 6)
-#define CA_CRM_PKTERR_CW_ERR		(1ull << 7)
-#define CA_CRM_PKTERR_SBERR_NH		(1ull << 8)
-#define CA_CRM_PKTERR_EARLY_TERM	(1ull << 9)
-#define CA_CRM_PKTERR_EARLY_TAIL	(1ull << 10)
-#define CA_CRM_PKTERR_MSSNG_TAIL	(1ull << 11)
-#define CA_CRM_PKTERR_MSSNG_HDR		(1ull << 12)
-	/* bits 15:13 unused */
-#define CA_FIRST_CRM_PKTERR_SBERR_HDR	(1ull << 16)
-#define CA_FIRST_CRM_PKTERR_DIDN	(1ull << 17)
-#define CA_FIRST_CRM_PKTERR_PACTYPE	(1ull << 18)
-#define CA_FIRST_CRM_PKTERR_INV_TNUM	(1ull << 19)
-#define CA_FIRST_CRM_PKTERR_ADDR_RNG	(1ull << 20)
-#define CA_FIRST_CRM_PKTERR_ADDR_ALGN	(1ull << 21)
-#define CA_FIRST_CRM_PKTERR_HDR_PARAM	(1ull << 22)
-#define CA_FIRST_CRM_PKTERR_CW_ERR	(1ull << 23)
-#define CA_FIRST_CRM_PKTERR_SBERR_NH	(1ull << 24)
-#define CA_FIRST_CRM_PKTERR_EARLY_TERM	(1ull << 25)
-#define CA_FIRST_CRM_PKTERR_EARLY_TAIL	(1ull << 26)
-#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL	(1ull << 27)
-#define CA_FIRST_CRM_PKTERR_MSSNG_HDR	(1ull << 28)
-	/* bits 63:29 unused */
-
-/* ==== ca_crm_ct_error_detail_1 */
-#define CA_PKT_TYPE			(0xfull << 0)
-#define CA_PKT_TYPE_SHFT		0
-#define CA_SRC_ID			(0x3ull << 4)
-#define CA_SRC_ID_SHFT			4
-#define CA_DATA_SZ			(0x3ull << 6)
-#define CA_DATA_SZ_SHFT			6
-#define CA_TNUM				(0xffull << 8)
-#define CA_TNUM_SHFT			8
-#define CA_DW_DATA_EN			(0xffull << 16)
-#define CA_DW_DATA_EN_SHFT		16
-#define CA_GFX_CRED			(0xffull << 24)
-#define CA_GFX_CRED_SHFT		24
-#define CA_MEM_RD_PARAM			(0x3ull << 32)
-#define CA_MEM_RD_PARAM_SHFT		32
-#define CA_PIO_OP			(1ull << 34)
-#define CA_CW_ERR			(1ull << 35)
-	/* bits 62:36 unused */
-#define CA_VALID			(1ull << 63)
-
-/* ==== ca_crm_ct_error_detail_2 */
-	/* bits 2:0 unused */
-#define CA_PKT_ADDR			(0x1fffffffffffffull << 3)
-#define CA_PKT_ADDR_SHFT		3
-	/* bits 63:56 unused */
-
-/* ==== ca_crm_tnumto */
-#define CA_CRM_TNUMTO_VAL		(0xffull << 0)
-#define CA_CRM_TNUMTO_VAL_SHFT		0
-#define CA_CRM_TNUMTO_WR		(1ull << 8)
-	/* bits 63:9 unused */
-
-/* ==== ca_gart_err */
-#define CA_GART_ERR_SOURCE		(0x3ull << 0)
-#define CA_GART_ERR_SOURCE_SHFT		0
-	/* bits 3:2 unused */
-#define CA_GART_ERR_ADDR		(0xfffffffffull << 4)
-#define CA_GART_ERR_ADDR_SHFT		4
-	/* bits 63:40 unused */
-
-/* ==== ca_pcierr_type */
-#define CA_PCIERR_DATA			(0xffffffffull << 0)
-#define CA_PCIERR_DATA_SHFT		0
-#define CA_PCIERR_ENB			(0xfull << 32)
-#define CA_PCIERR_ENB_SHFT		32
-#define CA_PCIERR_CMD			(0xfull << 36)
-#define CA_PCIERR_CMD_SHFT		36
-#define CA_PCIERR_A64			(1ull << 40)
-#define CA_PCIERR_SLV_SERR		(1ull << 41)
-#define CA_PCIERR_SLV_WR_PERR		(1ull << 42)
-#define CA_PCIERR_SLV_RD_PERR		(1ull << 43)
-#define CA_PCIERR_MST_SERR		(1ull << 44)
-#define CA_PCIERR_MST_WR_PERR		(1ull << 45)
-#define CA_PCIERR_MST_RD_PERR		(1ull << 46)
-#define CA_PCIERR_MST_MABT		(1ull << 47)
-#define CA_PCIERR_MST_TABT		(1ull << 48)
-#define CA_PCIERR_MST_RETRY_TOUT	(1ull << 49)
-
-#define CA_PCIERR_TYPES \
-	(CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \
-	 CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \
-	 CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \
-	 CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT)
-
-	/* bits 63:50 unused */
-
-/* ==== ca_pci_dma_addr_extn */
-#define CA_UPPER_NODE_OFFSET		(0x3full << 0)
-#define CA_UPPER_NODE_OFFSET_SHFT	0
-	/* bits 7:6 unused */
-#define CA_CHIPLET_ID			(0x3ull << 8)
-#define CA_CHIPLET_ID_SHFT		8
-	/* bits 11:10 unused */
-#define CA_PCI_DMA_NODE_ID		(0xffffull << 12)
-#define CA_PCI_DMA_NODE_ID_SHFT		12
-	/* bits 27:26 unused */
-#define CA_PCI_DMA_PIO_MEM_TYPE		(1ull << 28)
-	/* bits 63:29 unused */
-
-
-/* ==== ca_agp_dma_addr_extn */
-	/* bits 19:0 unused */
-#define CA_AGP_DMA_NODE_ID		(0xffffull << 20)
-#define CA_AGP_DMA_NODE_ID_SHFT		20
-	/* bits 27:26 unused */
-#define CA_AGP_DMA_PIO_MEM_TYPE		(1ull << 28)
-	/* bits 63:29 unused */
-
-/* ==== ca_debug_vector_sel */
-#define CA_DEBUG_MN_VSEL		(0xfull << 0)
-#define CA_DEBUG_MN_VSEL_SHFT		0
-#define CA_DEBUG_PP_VSEL		(0xfull << 4)
-#define CA_DEBUG_PP_VSEL_SHFT		4
-#define CA_DEBUG_GW_VSEL		(0xfull << 8)
-#define CA_DEBUG_GW_VSEL_SHFT		8
-#define CA_DEBUG_GT_VSEL		(0xfull << 12)
-#define CA_DEBUG_GT_VSEL_SHFT		12
-#define CA_DEBUG_PD_VSEL		(0xfull << 16)
-#define CA_DEBUG_PD_VSEL_SHFT		16
-#define CA_DEBUG_AD_VSEL		(0xfull << 20)
-#define CA_DEBUG_AD_VSEL_SHFT		20
-#define CA_DEBUG_CX_VSEL		(0xfull << 24)
-#define CA_DEBUG_CX_VSEL_SHFT		24
-#define CA_DEBUG_CR_VSEL		(0xfull << 28)
-#define CA_DEBUG_CR_VSEL_SHFT		28
-#define CA_DEBUG_BA_VSEL		(0xfull << 32)
-#define CA_DEBUG_BA_VSEL_SHFT		32
-#define CA_DEBUG_PE_VSEL		(0xfull << 36)
-#define CA_DEBUG_PE_VSEL_SHFT		36
-#define CA_DEBUG_BO_VSEL		(0xfull << 40)
-#define CA_DEBUG_BO_VSEL_SHFT		40
-#define CA_DEBUG_BI_VSEL		(0xfull << 44)
-#define CA_DEBUG_BI_VSEL_SHFT		44
-#define CA_DEBUG_AS_VSEL		(0xfull << 48)
-#define CA_DEBUG_AS_VSEL_SHFT		48
-#define CA_DEBUG_PS_VSEL		(0xfull << 52)
-#define CA_DEBUG_PS_VSEL_SHFT		52
-#define CA_DEBUG_PM_VSEL		(0xfull << 56)
-#define CA_DEBUG_PM_VSEL_SHFT		56
-	/* bits 63:60 unused */
-
-/* ==== ca_debug_mux_core_sel */
-/* ==== ca_debug_mux_pci_sel */
-#define CA_DEBUG_MSEL0			(0x7ull << 0)
-#define CA_DEBUG_MSEL0_SHFT		0
-	/* bit 3 unused */
-#define CA_DEBUG_NSEL0			(0x7ull << 4)
-#define CA_DEBUG_NSEL0_SHFT		4
-	/* bit 7 unused */
-#define CA_DEBUG_MSEL1			(0x7ull << 8)
-#define CA_DEBUG_MSEL1_SHFT		8
-	/* bit 11 unused */
-#define CA_DEBUG_NSEL1			(0x7ull << 12)
-#define CA_DEBUG_NSEL1_SHFT		12
-	/* bit 15 unused */
-#define CA_DEBUG_MSEL2			(0x7ull << 16)
-#define CA_DEBUG_MSEL2_SHFT		16
-	/* bit 19 unused */
-#define CA_DEBUG_NSEL2			(0x7ull << 20)
-#define CA_DEBUG_NSEL2_SHFT		20
-	/* bit 23 unused */
-#define CA_DEBUG_MSEL3			(0x7ull << 24)
-#define CA_DEBUG_MSEL3_SHFT		24
-	/* bit 27 unused */
-#define CA_DEBUG_NSEL3			(0x7ull << 28)
-#define CA_DEBUG_NSEL3_SHFT		28
-	/* bit 31 unused */
-#define CA_DEBUG_MSEL4			(0x7ull << 32)
-#define CA_DEBUG_MSEL4_SHFT		32
-	/* bit 35 unused */
-#define CA_DEBUG_NSEL4			(0x7ull << 36)
-#define CA_DEBUG_NSEL4_SHFT		36
-	/* bit 39 unused */
-#define CA_DEBUG_MSEL5			(0x7ull << 40)
-#define CA_DEBUG_MSEL5_SHFT		40
-	/* bit 43 unused */
-#define CA_DEBUG_NSEL5			(0x7ull << 44)
-#define CA_DEBUG_NSEL5_SHFT		44
-	/* bit 47 unused */
-#define CA_DEBUG_MSEL6			(0x7ull << 48)
-#define CA_DEBUG_MSEL6_SHFT		48
-	/* bit 51 unused */
-#define CA_DEBUG_NSEL6			(0x7ull << 52)
-#define CA_DEBUG_NSEL6_SHFT		52
-	/* bit 55 unused */
-#define CA_DEBUG_MSEL7			(0x7ull << 56)
-#define CA_DEBUG_MSEL7_SHFT		56
-	/* bit 59 unused */
-#define CA_DEBUG_NSEL7			(0x7ull << 60)
-#define CA_DEBUG_NSEL7_SHFT		60
-	/* bit 63 unused */
-
-
-/* ==== ca_debug_domain_sel */
-#define CA_DEBUG_DOMAIN_L		(1ull << 0)
-#define CA_DEBUG_DOMAIN_H		(1ull << 1)
-	/* bits 63:2 unused */
-
-/* ==== ca_gart_ptr_table */
-#define CA_GART_PTR_VAL			(1ull << 0)
-	/* bits 11:1 unused */
-#define CA_GART_PTR_ADDR		(0xfffffffffffull << 12)
-#define CA_GART_PTR_ADDR_SHFT		12
-	/* bits 63:56 unused */
-
-/* ==== ca_gart_tlb_addr[0-7] */
-#define CA_GART_TLB_ADDR		(0xffffffffffffffull << 0)
-#define CA_GART_TLB_ADDR_SHFT		0
-	/* bits 62:56 unused */
-#define CA_GART_TLB_ENTRY_VAL		(1ull << 63)
-
-/*
- * PIO address space ranges for TIO:CA
- */
-
-/* CA internal registers */
-#define CA_PIO_ADMIN			0x00000000
-#define CA_PIO_ADMIN_LEN		0x00010000
-
-/* GFX Write Buffer - Diagnostics */
-#define CA_PIO_GFX			0x00010000
-#define CA_PIO_GFX_LEN			0x00010000
-
-/* AGP DMA Write Buffer - Diagnostics */
-#define CA_PIO_AGP_DMAWRITE		0x00020000
-#define CA_PIO_AGP_DMAWRITE_LEN		0x00010000
-
-/* AGP DMA READ Buffer - Diagnostics */
-#define CA_PIO_AGP_DMAREAD		0x00030000
-#define CA_PIO_AGP_DMAREAD_LEN		0x00010000
-
-/* PCI Config Type 0 */
-#define CA_PIO_PCI_TYPE0_CONFIG		0x01000000
-#define CA_PIO_PCI_TYPE0_CONFIG_LEN	0x01000000
-
-/* PCI Config Type 1 */
-#define CA_PIO_PCI_TYPE1_CONFIG		0x02000000
-#define CA_PIO_PCI_TYPE1_CONFIG_LEN	0x01000000
-
-/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */
-#define CA_PIO_PCI_IO			0x03000000
-#define CA_PIO_PCI_IO_LEN		0x05000000
-
-/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */
-/*	use Fast Write if enabled and coretalk packet type is a GFX request */
-#define CA_PIO_PCI_MEM_OFFSET		0x08000000
-#define CA_PIO_PCI_MEM_OFFSET_LEN	0x08000000
-
-/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */
-/*	use Fast Write if enabled and coretalk packet type is a GFX request */
-#define CA_PIO_PCI_MEM			0x40000000
-#define CA_PIO_PCI_MEM_LEN		0xc0000000
-
-/*
- * DMA space
- *
- * The CA aperature (ie. bus address range) mapped by the GART is segmented into
- * two parts.  The lower portion of the aperature is used for mapping 32 bit
- * PCI addresses which are managed by the dma interfaces in this file.  The
- * upper poprtion of the aperature is used for mapping 48 bit AGP addresses.
- * The AGP portion of the aperature is managed by the agpgart_be.c driver
- * in drivers/linux/agp.  There are ca-specific hooks in that driver to
- * manipulate the gart, but management of the AGP portion of the aperature
- * is the responsibility of that driver.
- *
- * CA allows three main types of DMA mapping:
- *
- * PCI 64-bit	Managed by this driver
- * PCI 32-bit 	Managed by this driver
- * AGP 48-bit	Managed by hooks in the /dev/agpgart driver
- *
- * All of the above can optionally be remapped through the GART.  The following
- * table lists the combinations of addressing types and GART remapping that
- * is currently supported by the driver (h/w supports all, s/w limits this):
- *
- *		PCI64		PCI32		AGP48
- * GART		no		yes		yes
- * Direct	yes		yes		no
- *
- * GART remapping of PCI64 is not done because there is no need to.  The
- * 64 bit PCI address holds all of the information necessary to target any
- * memory in the system.
- *
- * AGP48 is always mapped through the GART.  Management of the AGP48 portion
- * of the aperature is the responsibility of code in the agpgart_be driver.
- *
- * The non-64 bit bus address space will currently be partitioned like this:
- *
- *	0xffff_ffff_ffff	+--------
- *				| AGP48 direct
- *				| Space managed by this driver
- *	CA_AGP_DIRECT_BASE	+--------
- *				| AGP GART mapped (gfx aperature)
- *				| Space managed by /dev/agpgart driver
- *				| This range is exposed to the agpgart
- * 				| driver as the "graphics aperature"
- *	CA_AGP_MAPPED_BASE	+-----
- *				| PCI GART mapped
- *				| Space managed by this driver		
- *	CA_PCI32_MAPPED_BASE	+----
- *				| PCI32 direct
- *				| Space managed by this driver
- *	0xC000_0000		+--------
- *	(CA_PCI32_DIRECT_BASE)
- *
- * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE
- * is what we call the CA aperature.  Addresses falling in this range will
- * be remapped using the GART.
- *
- * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE
- * is what we call the graphics aperature.  This is a subset of the CA
- * aperature and is under the control of the agpgart_be driver.
- *
- * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are
- * somewhat arbitrary values.  The known constraints on choosing these is:
- *
- * 1)  CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size)
- *     must be one of the values supported by the ca_gart_aperature register.
- *     Currently valid values are: 4MB through 4096MB in powers of 2 increments
- *
- * 2)  CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
- *     must be in MB units since that's what the agpgart driver assumes.
- */
-
-/*
- * Define Bus DMA ranges.  These are configurable (see constraints above)
- * and will probably need tuning based on experience.
- */
-
-
-/*
- * 11/24/03
- * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it
- * generally unusable.  The problem is that for PCI direct 32 
- * DMA's, all 32 bits of the bus address are used to form the lower 32 bits
- * of the coretalk address, and coretalk bits 38:32 come from a register.
- * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available
- * for DMA (the rest is allocated to PIO), host node addresses need to be
- * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
- * as well.  So there can be no PCI32 direct DMA below 3GB!!  For this
- * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes
- * tioca_dma_direct32() a noop but preserves the code flow should this issue
- * be fixed in a respin.
- *
- * For now, all PCI32 DMA's must be mapped through the GART.
- */
-
-#define CA_PCI32_DIRECT_BASE	0xC0000000UL	/* BASE not configurable */
-#define CA_PCI32_DIRECT_SIZE	0x00000000UL	/* 0 MB */
-
-#define CA_PCI32_MAPPED_BASE	0xC0000000UL
-#define CA_PCI32_MAPPED_SIZE	0x40000000UL	/* 2GB */
-
-#define CA_AGP_MAPPED_BASE	0x80000000UL
-#define CA_AGP_MAPPED_SIZE	0x40000000UL	/* 2GB */
-
-#define CA_AGP_DIRECT_BASE	0x40000000UL	/* 2GB */
-#define CA_AGP_DIRECT_SIZE	0x40000000UL
-
-#define CA_APERATURE_BASE	(CA_AGP_MAPPED_BASE)
-#define CA_APERATURE_SIZE	(CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE)
-
-#endif  /* _ASM_IA64_SN_TIO_TIOCA_H */
diff --git a/arch/ia64/include/asm/sn/tioca_provider.h b/arch/ia64/include/asm/sn/tioca_provider.h
deleted file mode 100644
index 9a820ac61be3..000000000000
--- a/arch/ia64/include/asm/sn/tioca_provider.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
-#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
-
-#include <asm/sn/tioca.h>
-
-/*
- * WAR enables
- * Defines for individual WARs. Each is a bitmask of applicable
- * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
- * (3 << 1) == (rev A or rev B), etc
- */
-
-#define TIOCA_WAR_ENABLED(pv, tioca_common) \
-	((1 << tioca_common->ca_rev) & pv)
-
-  /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
-#define PV907908 (1 << 1)
-  /* ATI config space problems after BIOS execution starts */
-#define PV908234 (1 << 1)
-  /* CA:AGPDMA write request data mismatch with ABC1CL merge */
-#define PV895469 (1 << 1)
-  /* TIO:CA TLB invalidate of written GART entries possibly not occurring in CA*/
-#define PV910244 (1 << 1)
-
-struct tioca_dmamap{
-	struct list_head	cad_list;	/* headed by ca_list */
-
-	dma_addr_t		cad_dma_addr;	/* Linux dma handle */
-	uint			cad_gart_entry; /* start entry in ca_gart_pagemap */
-	uint			cad_gart_size;	/* #entries for this map */
-};
-
-/*
- * Kernel only fields.  Prom may look at this stuff for debugging only.
- * Access this structure through the ca_kernel_private ptr.
- */
-
-struct tioca_common ;
-
-struct tioca_kernel {
-	struct tioca_common	*ca_common;	/* tioca this belongs to */
-	struct list_head	ca_list;	/* list of all ca's */
-	struct list_head	ca_dmamaps;
-	spinlock_t		ca_lock;	/* Kernel lock */
-	cnodeid_t		ca_closest_node;
-	struct list_head	*ca_devices;	/* bus->devices */
-
-	/*
-	 * General GART stuff
-	 */
-	u64	ca_ap_size;		/* size of aperature in bytes */
-	u32	ca_gart_entries;	/* # u64 entries in gart */
-	u32	ca_ap_pagesize; 	/* aperature page size in bytes */
-	u64	ca_ap_bus_base; 	/* bus address of CA aperature */
-	u64	ca_gart_size;		/* gart size in bytes */
-	u64	*ca_gart;		/* gart table vaddr */
-	u64	ca_gart_coretalk_addr;	/* gart coretalk addr */
-	u8		ca_gart_iscoherent;	/* used in tioca_tlbflush */
-
-	/* PCI GART convenience values */
-	u64	ca_pciap_base;		/* pci aperature bus base address */
-	u64	ca_pciap_size;		/* pci aperature size (bytes) */
-	u64	ca_pcigart_base;	/* gfx GART bus base address */
-	u64	*ca_pcigart;		/* gfx GART vm address */
-	u32	ca_pcigart_entries;
-	u32	ca_pcigart_start;	/* PCI start index in ca_gart */
-	void		*ca_pcigart_pagemap;
-
-	/* AGP GART convenience values */
-	u64	ca_gfxap_base;		/* gfx aperature bus base address */
-	u64	ca_gfxap_size;		/* gfx aperature size (bytes) */
-	u64	ca_gfxgart_base;	/* gfx GART bus base address */
-	u64	*ca_gfxgart;		/* gfx GART vm address */
-	u32	ca_gfxgart_entries;
-	u32	ca_gfxgart_start;	/* agpgart start index in ca_gart */
-};
-
-/*
- * Common tioca info shared between kernel and prom
- *
- * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
- * TO THE PROM VERSION.
- */
-
-struct tioca_common {
-	struct pcibus_bussoft	ca_common;	/* common pciio header */
-
-	u32		ca_rev;
-	u32		ca_closest_nasid;
-
-	u64		ca_prom_private;
-	u64		ca_kernel_private;
-};
-
-/**
- * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
- * @paddr: page address to convert
- *
- * Convert a system [coretalk] address to a GART entry.  GART entries are
- * formed using the following:
- *
- *     data = ( (1<<63) |  ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) | 
- * (REMAP_SYS_ADDR) ) >> 12 )
- *
- * DATA written to 1 GART TABLE Entry in system memory is remapped system
- * addr for 1 page 
- *
- * The data is for coretalk address format right shifted 12 bits with a
- * valid bit.
- *
- *	GART_TABLE_ENTRY [ 25:0 ]  -- REMAP_SYS_ADDRESS[37:12].
- *	GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
- *	GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
- *	GART_TABLE_ENTRY [ 63 ]    -- Valid Bit 
- */
-static inline u64
-tioca_paddr_to_gart(unsigned long paddr)
-{
-	/*
-	 * We are assuming right now that paddr already has the correct
-	 * format since the address from xtalk_dmaXXX should already have
-	 * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
-	 */
-
-	return ((paddr) >> 12) | (1UL << 63);
-}
-
-/**
- * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
- * @page_addr: system page address to map
- */
-
-static inline unsigned long
-tioca_physpage_to_gart(u64 page_addr)
-{
-	u64 coretalk_addr;
-
-	coretalk_addr = PHYS_TO_TIODMA(page_addr);
-	if (!coretalk_addr) {
-		return 0;
-	}
-
-	return tioca_paddr_to_gart(coretalk_addr);
-}
-
-/**
- * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
- * @tioca_kernel: CA context 
- *
- * Invalidate tlb entries for a given CA GART.  Main complexity is to account
- * for revA bug.
- */
-static inline void
-tioca_tlbflush(struct tioca_kernel *tioca_kernel)
-{
-	volatile u64 tmp;
-	volatile struct tioca __iomem *ca_base;
-	struct tioca_common *tioca_common;
-
-	tioca_common = tioca_kernel->ca_common;
-	ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
-
-	/*
-	 * Explicit flushes not needed if GART is in cached mode
-	 */
-	if (tioca_kernel->ca_gart_iscoherent) {
-		if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
-			/*
-			 * PV910244:  RevA CA needs explicit flushes.
-			 * Need to put GART into uncached mode before
-			 * flushing otherwise the explicit flush is ignored.
-			 *
-			 * Alternate WAR would be to leave GART cached and
-			 * touch every CL aligned GART entry.
-			 */
-
-			__sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
-			__sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
-			__sn_setq_relaxed(&ca_base->ca_control2,
-			    (0x2ull << CA_GART_MEM_PARAM_SHFT));
-			tmp = __sn_readq_relaxed(&ca_base->ca_control2);
-		}
-
-		return;
-	}
-
-	/*
-	 * Gart in uncached mode ... need an explicit flush.
-	 */
-
-	__sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
-	tmp = __sn_readq_relaxed(&ca_base->ca_control2);
-}
-
-extern u32	tioca_gart_found;
-extern struct list_head tioca_list;
-extern int tioca_init_provider(void);
-extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
-#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/tioce.h b/arch/ia64/include/asm/sn/tioce.h
deleted file mode 100644
index 6eae8ada90f0..000000000000
--- a/arch/ia64/include/asm/sn/tioce.h
+++ /dev/null
@@ -1,760 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef __ASM_IA64_SN_TIOCE_H__
-#define __ASM_IA64_SN_TIOCE_H__
-
-/* CE ASIC part & mfgr information  */
-#define TIOCE_PART_NUM			0xCE00
-#define TIOCE_SRC_ID			0x01
-#define TIOCE_REV_A			0x1
-
-/* CE Virtual PPB Vendor/Device IDs */
-#define CE_VIRT_PPB_VENDOR_ID		0x10a9
-#define CE_VIRT_PPB_DEVICE_ID		0x4002
-
-/* CE Host Bridge Vendor/Device IDs */
-#define CE_HOST_BRIDGE_VENDOR_ID	0x10a9
-#define CE_HOST_BRIDGE_DEVICE_ID	0x4001
-
-
-#define TIOCE_NUM_M40_ATES		4096
-#define TIOCE_NUM_M3240_ATES		2048
-#define TIOCE_NUM_PORTS			2
-
-/*
- * Register layout for TIOCE.  MMR offsets are shown at the far right of the
- * structure definition.
- */
-typedef volatile struct tioce {
-	/*
-	 * ADMIN : Administration Registers
-	 */
-	u64	ce_adm_id;				/* 0x000000 */
-	u64	ce_pad_000008;				/* 0x000008 */
-	u64	ce_adm_dyn_credit_status;		/* 0x000010 */
-	u64	ce_adm_last_credit_status;		/* 0x000018 */
-	u64	ce_adm_credit_limit;			/* 0x000020 */
-	u64	ce_adm_force_credit;			/* 0x000028 */
-	u64	ce_adm_control;				/* 0x000030 */
-	u64	ce_adm_mmr_chn_timeout;			/* 0x000038 */
-	u64	ce_adm_ssp_ure_timeout;			/* 0x000040 */
-	u64	ce_adm_ssp_dre_timeout;			/* 0x000048 */
-	u64	ce_adm_ssp_debug_sel;			/* 0x000050 */
-	u64	ce_adm_int_status;			/* 0x000058 */
-	u64	ce_adm_int_status_alias;		/* 0x000060 */
-	u64	ce_adm_int_mask;			/* 0x000068 */
-	u64	ce_adm_int_pending;			/* 0x000070 */
-	u64	ce_adm_force_int;			/* 0x000078 */
-	u64	ce_adm_ure_ups_buf_barrier_flush;	/* 0x000080 */
-	u64	ce_adm_int_dest[15];	    /* 0x000088 -- 0x0000F8 */
-	u64	ce_adm_error_summary;			/* 0x000100 */
-	u64	ce_adm_error_summary_alias;		/* 0x000108 */
-	u64	ce_adm_error_mask;			/* 0x000110 */
-	u64	ce_adm_first_error;			/* 0x000118 */
-	u64	ce_adm_error_overflow;			/* 0x000120 */
-	u64	ce_adm_error_overflow_alias;		/* 0x000128 */
-	u64	ce_pad_000130[2];	    /* 0x000130 -- 0x000138 */
-	u64	ce_adm_tnum_error;			/* 0x000140 */
-	u64	ce_adm_mmr_err_detail;			/* 0x000148 */
-	u64	ce_adm_msg_sram_perr_detail;		/* 0x000150 */
-	u64	ce_adm_bap_sram_perr_detail;		/* 0x000158 */
-	u64	ce_adm_ce_sram_perr_detail;		/* 0x000160 */
-	u64	ce_adm_ce_credit_oflow_detail;		/* 0x000168 */
-	u64	ce_adm_tx_link_idle_max_timer;		/* 0x000170 */
-	u64	ce_adm_pcie_debug_sel;			/* 0x000178 */
-	u64	ce_pad_000180[16];	    /* 0x000180 -- 0x0001F8 */
-
-	u64	ce_adm_pcie_debug_sel_top;		/* 0x000200 */
-	u64	ce_adm_pcie_debug_lat_sel_lo_top;	/* 0x000208 */
-	u64	ce_adm_pcie_debug_lat_sel_hi_top;	/* 0x000210 */
-	u64	ce_adm_pcie_debug_trig_sel_top;		/* 0x000218 */
-	u64	ce_adm_pcie_debug_trig_lat_sel_lo_top;	/* 0x000220 */
-	u64	ce_adm_pcie_debug_trig_lat_sel_hi_top;	/* 0x000228 */
-	u64	ce_adm_pcie_trig_compare_top;		/* 0x000230 */
-	u64	ce_adm_pcie_trig_compare_en_top;	/* 0x000238 */
-	u64	ce_adm_ssp_debug_sel_top;		/* 0x000240 */
-	u64	ce_adm_ssp_debug_lat_sel_lo_top;	/* 0x000248 */
-	u64	ce_adm_ssp_debug_lat_sel_hi_top;	/* 0x000250 */
-	u64	ce_adm_ssp_debug_trig_sel_top;		/* 0x000258 */
-	u64	ce_adm_ssp_debug_trig_lat_sel_lo_top;	/* 0x000260 */
-	u64	ce_adm_ssp_debug_trig_lat_sel_hi_top;	/* 0x000268 */
-	u64	ce_adm_ssp_trig_compare_top;		/* 0x000270 */
-	u64	ce_adm_ssp_trig_compare_en_top;		/* 0x000278 */
-	u64	ce_pad_000280[48];	    /* 0x000280 -- 0x0003F8 */
-
-	u64	ce_adm_bap_ctrl;			/* 0x000400 */
-	u64	ce_pad_000408[127];	    /* 0x000408 -- 0x0007F8 */
-
-	u64	ce_msg_buf_data63_0[35];    /* 0x000800 -- 0x000918 */
-	u64	ce_pad_000920[29];	    /* 0x000920 -- 0x0009F8 */
-
-	u64	ce_msg_buf_data127_64[35];  /* 0x000A00 -- 0x000B18 */
-	u64	ce_pad_000B20[29];	    /* 0x000B20 -- 0x000BF8 */
-
-	u64	ce_msg_buf_parity[35];	    /* 0x000C00 -- 0x000D18 */
-	u64	ce_pad_000D20[29];	    /* 0x000D20 -- 0x000DF8 */
-
-	u64	ce_pad_000E00[576];	    /* 0x000E00 -- 0x001FF8 */
-
-	/*
-	 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
-	 * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
-	 * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
-	 */
-	#define ce_lsi(link_num)	ce_lsi[link_num-1]
-	struct ce_lsi_reg {
-		u64	ce_lsi_lpu_id;			/* 0x00z000 */
-		u64	ce_lsi_rst;			/* 0x00z008 */
-		u64	ce_lsi_dbg_stat;		/* 0x00z010 */
-		u64	ce_lsi_dbg_cfg;			/* 0x00z018 */
-		u64	ce_lsi_ltssm_ctrl;		/* 0x00z020 */
-		u64	ce_lsi_lk_stat;			/* 0x00z028 */
-		u64	ce_pad_00z030[2];   /* 0x00z030 -- 0x00z038 */
-		u64	ce_lsi_int_and_stat;		/* 0x00z040 */
-		u64	ce_lsi_int_mask;		/* 0x00z048 */
-		u64	ce_pad_00z050[22];  /* 0x00z050 -- 0x00z0F8 */
-		u64	ce_lsi_lk_perf_cnt_sel;		/* 0x00z100 */
-		u64	ce_pad_00z108;			/* 0x00z108 */
-		u64	ce_lsi_lk_perf_cnt_ctrl;	/* 0x00z110 */
-		u64	ce_pad_00z118;			/* 0x00z118 */
-		u64	ce_lsi_lk_perf_cnt1;		/* 0x00z120 */
-		u64	ce_lsi_lk_perf_cnt1_test;	/* 0x00z128 */
-		u64	ce_lsi_lk_perf_cnt2;		/* 0x00z130 */
-		u64	ce_lsi_lk_perf_cnt2_test;	/* 0x00z138 */
-		u64	ce_pad_00z140[24];  /* 0x00z140 -- 0x00z1F8 */
-		u64	ce_lsi_lk_lyr_cfg;		/* 0x00z200 */
-		u64	ce_lsi_lk_lyr_status;		/* 0x00z208 */
-		u64	ce_lsi_lk_lyr_int_stat;		/* 0x00z210 */
-		u64	ce_lsi_lk_ly_int_stat_test;	/* 0x00z218 */
-		u64	ce_lsi_lk_ly_int_stat_mask;	/* 0x00z220 */
-		u64	ce_pad_00z228[3];   /* 0x00z228 -- 0x00z238 */
-		u64	ce_lsi_fc_upd_ctl;		/* 0x00z240 */
-		u64	ce_pad_00z248[3];   /* 0x00z248 -- 0x00z258 */
-		u64	ce_lsi_flw_ctl_upd_to_timer;	/* 0x00z260 */
-		u64	ce_lsi_flw_ctl_upd_timer0;	/* 0x00z268 */
-		u64	ce_lsi_flw_ctl_upd_timer1;	/* 0x00z270 */
-		u64	ce_pad_00z278[49];  /* 0x00z278 -- 0x00z3F8 */
-		u64	ce_lsi_freq_nak_lat_thrsh;	/* 0x00z400 */
-		u64	ce_lsi_ack_nak_lat_tmr;		/* 0x00z408 */
-		u64	ce_lsi_rply_tmr_thr;		/* 0x00z410 */
-		u64	ce_lsi_rply_tmr;		/* 0x00z418 */
-		u64	ce_lsi_rply_num_stat;		/* 0x00z420 */
-		u64	ce_lsi_rty_buf_max_addr;	/* 0x00z428 */
-		u64	ce_lsi_rty_fifo_ptr;		/* 0x00z430 */
-		u64	ce_lsi_rty_fifo_rd_wr_ptr;	/* 0x00z438 */
-		u64	ce_lsi_rty_fifo_cred;		/* 0x00z440 */
-		u64	ce_lsi_seq_cnt;			/* 0x00z448 */
-		u64	ce_lsi_ack_sent_seq_num;	/* 0x00z450 */
-		u64	ce_lsi_seq_cnt_fifo_max_addr;	/* 0x00z458 */
-		u64	ce_lsi_seq_cnt_fifo_ptr;	/* 0x00z460 */
-		u64	ce_lsi_seq_cnt_rd_wr_ptr;	/* 0x00z468 */
-		u64	ce_lsi_tx_lk_ts_ctl;		/* 0x00z470 */
-		u64	ce_pad_00z478;			/* 0x00z478 */
-		u64	ce_lsi_mem_addr_ctl;		/* 0x00z480 */
-		u64	ce_lsi_mem_d_ld0;		/* 0x00z488 */
-		u64	ce_lsi_mem_d_ld1;		/* 0x00z490 */
-		u64	ce_lsi_mem_d_ld2;		/* 0x00z498 */
-		u64	ce_lsi_mem_d_ld3;		/* 0x00z4A0 */
-		u64	ce_lsi_mem_d_ld4;		/* 0x00z4A8 */
-		u64	ce_pad_00z4B0[2];   /* 0x00z4B0 -- 0x00z4B8 */
-		u64	ce_lsi_rty_d_cnt;		/* 0x00z4C0 */
-		u64	ce_lsi_seq_buf_cnt;		/* 0x00z4C8 */
-		u64	ce_lsi_seq_buf_bt_d;		/* 0x00z4D0 */
-		u64	ce_pad_00z4D8;			/* 0x00z4D8 */
-		u64	ce_lsi_ack_lat_thr;		/* 0x00z4E0 */
-		u64	ce_pad_00z4E8[3];   /* 0x00z4E8 -- 0x00z4F8 */
-		u64	ce_lsi_nxt_rcv_seq_1_cntr;	/* 0x00z500 */
-		u64	ce_lsi_unsp_dllp_rcvd;		/* 0x00z508 */
-		u64	ce_lsi_rcv_lk_ts_ctl;		/* 0x00z510 */
-		u64	ce_pad_00z518[29];  /* 0x00z518 -- 0x00z5F8 */
-		u64	ce_lsi_phy_lyr_cfg;		/* 0x00z600 */
-		u64	ce_pad_00z608;			/* 0x00z608 */
-		u64	ce_lsi_phy_lyr_int_stat;	/* 0x00z610 */
-		u64	ce_lsi_phy_lyr_int_stat_test;	/* 0x00z618 */
-		u64	ce_lsi_phy_lyr_int_mask;	/* 0x00z620 */
-		u64	ce_pad_00z628[11];  /* 0x00z628 -- 0x00z678 */
-		u64	ce_lsi_rcv_phy_cfg;		/* 0x00z680 */
-		u64	ce_lsi_rcv_phy_stat1;		/* 0x00z688 */
-		u64	ce_lsi_rcv_phy_stat2;		/* 0x00z690 */
-		u64	ce_lsi_rcv_phy_stat3;		/* 0x00z698 */
-		u64	ce_lsi_rcv_phy_int_stat;	/* 0x00z6A0 */
-		u64	ce_lsi_rcv_phy_int_stat_test;	/* 0x00z6A8 */
-		u64	ce_lsi_rcv_phy_int_mask;	/* 0x00z6B0 */
-		u64	ce_pad_00z6B8[9];   /* 0x00z6B8 -- 0x00z6F8 */
-		u64	ce_lsi_tx_phy_cfg;		/* 0x00z700 */
-		u64	ce_lsi_tx_phy_stat;		/* 0x00z708 */
-		u64	ce_lsi_tx_phy_int_stat;		/* 0x00z710 */
-		u64	ce_lsi_tx_phy_int_stat_test;	/* 0x00z718 */
-		u64	ce_lsi_tx_phy_int_mask;		/* 0x00z720 */
-		u64	ce_lsi_tx_phy_stat2;		/* 0x00z728 */
-		u64	ce_pad_00z730[10];  /* 0x00z730 -- 0x00z77F */
-		u64	ce_lsi_ltssm_cfg1;		/* 0x00z780 */
-		u64	ce_lsi_ltssm_cfg2;		/* 0x00z788 */
-		u64	ce_lsi_ltssm_cfg3;		/* 0x00z790 */
-		u64	ce_lsi_ltssm_cfg4;		/* 0x00z798 */
-		u64	ce_lsi_ltssm_cfg5;		/* 0x00z7A0 */
-		u64	ce_lsi_ltssm_stat1;		/* 0x00z7A8 */
-		u64	ce_lsi_ltssm_stat2;		/* 0x00z7B0 */
-		u64	ce_lsi_ltssm_int_stat;		/* 0x00z7B8 */
-		u64	ce_lsi_ltssm_int_stat_test;	/* 0x00z7C0 */
-		u64	ce_lsi_ltssm_int_mask;		/* 0x00z7C8 */
-		u64	ce_lsi_ltssm_stat_wr_en;	/* 0x00z7D0 */
-		u64	ce_pad_00z7D8[5];   /* 0x00z7D8 -- 0x00z7F8 */
-		u64	ce_lsi_gb_cfg1;			/* 0x00z800 */
-		u64	ce_lsi_gb_cfg2;			/* 0x00z808 */
-		u64	ce_lsi_gb_cfg3;			/* 0x00z810 */
-		u64	ce_lsi_gb_cfg4;			/* 0x00z818 */
-		u64	ce_lsi_gb_stat;			/* 0x00z820 */
-		u64	ce_lsi_gb_int_stat;		/* 0x00z828 */
-		u64	ce_lsi_gb_int_stat_test;	/* 0x00z830 */
-		u64	ce_lsi_gb_int_mask;		/* 0x00z838 */
-		u64	ce_lsi_gb_pwr_dn1;		/* 0x00z840 */
-		u64	ce_lsi_gb_pwr_dn2;		/* 0x00z848 */
-		u64	ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
-	} ce_lsi[2];
-
-	u64	ce_pad_004000[10];	    /* 0x004000 -- 0x004048 */
-
-	/*
-	 * CRM: Coretalk Receive Module Registers
-	 */
-	u64	ce_crm_debug_mux;			/* 0x004050 */
-	u64	ce_pad_004058;				/* 0x004058 */
-	u64	ce_crm_ssp_err_cmd_wrd;			/* 0x004060 */
-	u64	ce_crm_ssp_err_addr;			/* 0x004068 */
-	u64	ce_crm_ssp_err_syn;			/* 0x004070 */
-
-	u64	ce_pad_004078[499];	    /* 0x004078 -- 0x005008 */
-
-	/*
-         * CXM: Coretalk Xmit Module Registers
-         */
-	u64	ce_cxm_dyn_credit_status;		/* 0x005010 */
-	u64	ce_cxm_last_credit_status;		/* 0x005018 */
-	u64	ce_cxm_credit_limit;			/* 0x005020 */
-	u64	ce_cxm_force_credit;			/* 0x005028 */
-	u64	ce_cxm_disable_bypass;			/* 0x005030 */
-	u64	ce_pad_005038[3];	    /* 0x005038 -- 0x005048 */
-	u64	ce_cxm_debug_mux;			/* 0x005050 */
-
-        u64        ce_pad_005058[501];         /* 0x005058 -- 0x005FF8 */
-
-	/*
-	 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
-	 * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
-	 * DTL: the comment offsets at far right: let 'y' = {6 or 8}
-	 *
-	 * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
-	 * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
-	 * UTL: the comment offsets at far right: let 'z' = {7 or 9}
-	 */
-	#define ce_dtl(link_num)	ce_dtl_utl[link_num-1]
-	#define ce_utl(link_num)	ce_dtl_utl[link_num-1]
-	struct ce_dtl_utl_reg {
-		/* DTL */
-		u64	ce_dtl_dtdr_credit_limit;	/* 0x00y000 */
-		u64	ce_dtl_dtdr_credit_force;	/* 0x00y008 */
-		u64	ce_dtl_dyn_credit_status;	/* 0x00y010 */
-		u64	ce_dtl_dtl_last_credit_stat;	/* 0x00y018 */
-		u64	ce_dtl_dtl_ctrl;		/* 0x00y020 */
-		u64	ce_pad_00y028[5];   /* 0x00y028 -- 0x00y048 */
-		u64	ce_dtl_debug_sel;		/* 0x00y050 */
-		u64	ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
-
-		/* UTL */
-		u64	ce_utl_utl_ctrl;		/* 0x00z000 */
-		u64	ce_utl_debug_sel;		/* 0x00z008 */
-		u64	ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
-	} ce_dtl_utl[2];
-
-	u64	ce_pad_00A000[514];	    /* 0x00A000 -- 0x00B008 */
-
-	/*
-	 * URE: Upstream Request Engine
-         */
-	u64	ce_ure_dyn_credit_status;		/* 0x00B010 */
-	u64	ce_ure_last_credit_status;		/* 0x00B018 */
-	u64	ce_ure_credit_limit;			/* 0x00B020 */
-	u64	ce_pad_00B028;				/* 0x00B028 */
-	u64	ce_ure_control;				/* 0x00B030 */
-	u64	ce_ure_status;				/* 0x00B038 */
-	u64	ce_pad_00B040[2];	    /* 0x00B040 -- 0x00B048 */
-	u64	ce_ure_debug_sel;			/* 0x00B050 */
-	u64	ce_ure_pcie_debug_sel;			/* 0x00B058 */
-	u64	ce_ure_ssp_err_cmd_wrd;			/* 0x00B060 */
-	u64	ce_ure_ssp_err_addr;			/* 0x00B068 */
-	u64	ce_ure_page_map;			/* 0x00B070 */
-	u64	ce_ure_dir_map[TIOCE_NUM_PORTS];	/* 0x00B078 */
-	u64	ce_ure_pipe_sel1;			/* 0x00B088 */
-	u64	ce_ure_pipe_mask1;			/* 0x00B090 */
-	u64	ce_ure_pipe_sel2;			/* 0x00B098 */
-	u64	ce_ure_pipe_mask2;			/* 0x00B0A0 */
-	u64	ce_ure_pcie1_credits_sent;		/* 0x00B0A8 */
-	u64	ce_ure_pcie1_credits_used;		/* 0x00B0B0 */
-	u64	ce_ure_pcie1_credit_limit;		/* 0x00B0B8 */
-	u64	ce_ure_pcie2_credits_sent;		/* 0x00B0C0 */
-	u64	ce_ure_pcie2_credits_used;		/* 0x00B0C8 */
-	u64	ce_ure_pcie2_credit_limit;		/* 0x00B0D0 */
-	u64	ce_ure_pcie_force_credit;		/* 0x00B0D8 */
-	u64	ce_ure_rd_tnum_val;			/* 0x00B0E0 */
-	u64	ce_ure_rd_tnum_rsp_rcvd;		/* 0x00B0E8 */
-	u64	ce_ure_rd_tnum_esent_timer;		/* 0x00B0F0 */
-	u64	ce_ure_rd_tnum_error;			/* 0x00B0F8 */
-	u64	ce_ure_rd_tnum_first_cl;		/* 0x00B100 */
-	u64	ce_ure_rd_tnum_link_buf;		/* 0x00B108 */
-	u64	ce_ure_wr_tnum_val;			/* 0x00B110 */
-	u64	ce_ure_sram_err_addr0;			/* 0x00B118 */
-	u64	ce_ure_sram_err_addr1;			/* 0x00B120 */
-	u64	ce_ure_sram_err_addr2;			/* 0x00B128 */
-	u64	ce_ure_sram_rd_addr0;			/* 0x00B130 */
-	u64	ce_ure_sram_rd_addr1;			/* 0x00B138 */
-	u64	ce_ure_sram_rd_addr2;			/* 0x00B140 */
-	u64	ce_ure_sram_wr_addr0;			/* 0x00B148 */
-	u64	ce_ure_sram_wr_addr1;			/* 0x00B150 */
-	u64	ce_ure_sram_wr_addr2;			/* 0x00B158 */
-	u64	ce_ure_buf_flush10;			/* 0x00B160 */
-	u64	ce_ure_buf_flush11;			/* 0x00B168 */
-	u64	ce_ure_buf_flush12;			/* 0x00B170 */
-	u64	ce_ure_buf_flush13;			/* 0x00B178 */
-	u64	ce_ure_buf_flush20;			/* 0x00B180 */
-	u64	ce_ure_buf_flush21;			/* 0x00B188 */
-	u64	ce_ure_buf_flush22;			/* 0x00B190 */
-	u64	ce_ure_buf_flush23;			/* 0x00B198 */
-	u64	ce_ure_pcie_control1;			/* 0x00B1A0 */
-	u64	ce_ure_pcie_control2;			/* 0x00B1A8 */
-
-	u64	ce_pad_00B1B0[458];	    /* 0x00B1B0 -- 0x00BFF8 */
-
-	/* Upstream Data Buffer, Port1 */
-	struct ce_ure_maint_ups_dat1_data {
-		u64	data63_0[512];	    /* 0x00C000 -- 0x00CFF8 */
-		u64	data127_64[512];    /* 0x00D000 -- 0x00DFF8 */
-		u64	parity[512];	    /* 0x00E000 -- 0x00EFF8 */
-	} ce_ure_maint_ups_dat1;
-
-	/* Upstream Header Buffer, Port1 */
-	struct ce_ure_maint_ups_hdr1_data {
-		u64	data63_0[512];	    /* 0x00F000 -- 0x00FFF8 */
-		u64	data127_64[512];    /* 0x010000 -- 0x010FF8 */
-		u64	parity[512];	    /* 0x011000 -- 0x011FF8 */
-	} ce_ure_maint_ups_hdr1;
-
-	/* Upstream Data Buffer, Port2 */
-	struct ce_ure_maint_ups_dat2_data {
-		u64	data63_0[512];	    /* 0x012000 -- 0x012FF8 */
-		u64	data127_64[512];    /* 0x013000 -- 0x013FF8 */
-		u64	parity[512];	    /* 0x014000 -- 0x014FF8 */
-	} ce_ure_maint_ups_dat2;
-
-	/* Upstream Header Buffer, Port2 */
-	struct ce_ure_maint_ups_hdr2_data {
-		u64	data63_0[512];	    /* 0x015000 -- 0x015FF8 */
-		u64	data127_64[512];    /* 0x016000 -- 0x016FF8 */
-		u64	parity[512];	    /* 0x017000 -- 0x017FF8 */
-	} ce_ure_maint_ups_hdr2;
-
-	/* Downstream Data Buffer */
-	struct ce_ure_maint_dns_dat_data {
-		u64	data63_0[512];	    /* 0x018000 -- 0x018FF8 */
-		u64	data127_64[512];    /* 0x019000 -- 0x019FF8 */
-		u64	parity[512];	    /* 0x01A000 -- 0x01AFF8 */
-	} ce_ure_maint_dns_dat;
-
-	/* Downstream Header Buffer */
-	struct	ce_ure_maint_dns_hdr_data {
-		u64	data31_0[64];	    /* 0x01B000 -- 0x01B1F8 */
-		u64	data95_32[64];	    /* 0x01B200 -- 0x01B3F8 */
-		u64	parity[64];	    /* 0x01B400 -- 0x01B5F8 */
-	} ce_ure_maint_dns_hdr;
-
-	/* RCI Buffer Data */
-	struct	ce_ure_maint_rci_data {
-		u64	data41_0[64];	    /* 0x01B600 -- 0x01B7F8 */
-		u64	data69_42[64];	    /* 0x01B800 -- 0x01B9F8 */
-	} ce_ure_maint_rci;
-
-	/* Response Queue */
-	u64	ce_ure_maint_rspq[64];	    /* 0x01BA00 -- 0x01BBF8 */
-
-	u64	ce_pad_01C000[4224];	    /* 0x01BC00 -- 0x023FF8 */
-
-	/* Admin Build-a-Packet Buffer */
-	struct	ce_adm_maint_bap_buf_data {
-		u64	data63_0[258];	    /* 0x024000 -- 0x024808 */
-		u64	data127_64[258];    /* 0x024810 -- 0x025018 */
-		u64	parity[258];	    /* 0x025020 -- 0x025828 */
-	} ce_adm_maint_bap_buf;
-
-	u64	ce_pad_025830[5370];	    /* 0x025830 -- 0x02FFF8 */
-
-	/* URE: 40bit PMU ATE Buffer */		    /* 0x030000 -- 0x037FF8 */
-	u64	ce_ure_ate40[TIOCE_NUM_M40_ATES];
-
-	/* URE: 32/40bit PMU ATE Buffer */	    /* 0x038000 -- 0x03BFF8 */
-	u64	ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
-
-	u64	ce_pad_03C000[2050];	    /* 0x03C000 -- 0x040008 */
-
-	/*
-	 * DRE: Down Stream Request Engine
-         */
-	u64	ce_dre_dyn_credit_status1;		/* 0x040010 */
-	u64	ce_dre_dyn_credit_status2;		/* 0x040018 */
-	u64	ce_dre_last_credit_status1;		/* 0x040020 */
-	u64	ce_dre_last_credit_status2;		/* 0x040028 */
-	u64	ce_dre_credit_limit1;			/* 0x040030 */
-	u64	ce_dre_credit_limit2;			/* 0x040038 */
-	u64	ce_dre_force_credit1;			/* 0x040040 */
-	u64	ce_dre_force_credit2;			/* 0x040048 */
-	u64	ce_dre_debug_mux1;			/* 0x040050 */
-	u64	ce_dre_debug_mux2;			/* 0x040058 */
-	u64	ce_dre_ssp_err_cmd_wrd;			/* 0x040060 */
-	u64	ce_dre_ssp_err_addr;			/* 0x040068 */
-	u64	ce_dre_comp_err_cmd_wrd;		/* 0x040070 */
-	u64	ce_dre_comp_err_addr;			/* 0x040078 */
-	u64	ce_dre_req_status;			/* 0x040080 */
-	u64	ce_dre_config1;				/* 0x040088 */
-	u64	ce_dre_config2;				/* 0x040090 */
-	u64	ce_dre_config_req_status;		/* 0x040098 */
-	u64	ce_pad_0400A0[12];	    /* 0x0400A0 -- 0x0400F8 */
-	u64	ce_dre_dyn_fifo;			/* 0x040100 */
-	u64	ce_pad_040108[3];	    /* 0x040108 -- 0x040118 */
-	u64	ce_dre_last_fifo;			/* 0x040120 */
-
-	u64	ce_pad_040128[27];	    /* 0x040128 -- 0x0401F8 */
-
-	/* DRE Downstream Head Queue */
-	struct	ce_dre_maint_ds_head_queue {
-		u64	data63_0[32];	    /* 0x040200 -- 0x0402F8 */
-		u64	data127_64[32];	    /* 0x040300 -- 0x0403F8 */
-		u64	parity[32];	    /* 0x040400 -- 0x0404F8 */
-	} ce_dre_maint_ds_head_q;
-
-	u64	ce_pad_040500[352];	    /* 0x040500 -- 0x040FF8 */
-
-	/* DRE Downstream Data Queue */
-	struct	ce_dre_maint_ds_data_queue {
-		u64	data63_0[256];	    /* 0x041000 -- 0x0417F8 */
-		u64	ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
-		u64	data127_64[256];    /* 0x042000 -- 0x0427F8 */
-		u64	ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
-		u64	parity[256];	    /* 0x043000 -- 0x0437F8 */
-		u64	ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
-	} ce_dre_maint_ds_data_q;
-
-	/* DRE URE Upstream Response Queue */
-	struct	ce_dre_maint_ure_us_rsp_queue {
-		u64	data63_0[8];	    /* 0x044000 -- 0x044038 */
-		u64	ce_pad_044040[24];  /* 0x044040 -- 0x0440F8 */
-		u64	data127_64[8];      /* 0x044100 -- 0x044138 */
-		u64	ce_pad_044140[24];  /* 0x044140 -- 0x0441F8 */
-		u64	parity[8];	    /* 0x044200 -- 0x044238 */
-		u64	ce_pad_044240[24];  /* 0x044240 -- 0x0442F8 */
-	} ce_dre_maint_ure_us_rsp_q;
-
-	u64 	ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
-
-	u64	ce_end_of_struct;			/* 0x044400 */
-} tioce_t;
-
-/* ce_lsiX_gb_cfg1 register bit masks & shifts */
-#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT	0
-#define CE_LSI_GB_CFG1_RXL0S_THS_MASK	(0xffULL << 0)
-#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT	8
-#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK	(0xfULL << 8)
-#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT	12
-#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK	(0x7ULL << 12)
-#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT	15
-#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK	(0x1ULL << 15)
-#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT	16
-#define CE_LSI_GB_CFG1_LPBK_SEL_MASK	(0x3ULL << 16)
-#define CE_LSI_GB_CFG1_LPBK_EN_SHFT	18
-#define CE_LSI_GB_CFG1_LPBK_EN_MASK	(0x1ULL << 18)
-#define CE_LSI_GB_CFG1_RVRS_LB_SHFT	19
-#define CE_LSI_GB_CFG1_RVRS_LB_MASK	(0x1ULL << 19)
-#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT	20
-#define CE_LSI_GB_CFG1_RVRS_CLK_MASK	(0x3ULL << 20)
-#define CE_LSI_GB_CFG1_SLF_TS_SHFT	24
-#define CE_LSI_GB_CFG1_SLF_TS_MASK	(0xfULL << 24)
-
-/* ce_adm_int_mask/ce_adm_int_status register bit defines */
-#define CE_ADM_INT_CE_ERROR_SHFT		0
-#define CE_ADM_INT_LSI1_IP_ERROR_SHFT		1
-#define CE_ADM_INT_LSI2_IP_ERROR_SHFT		2
-#define CE_ADM_INT_PCIE_ERROR_SHFT		3
-#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT	4
-#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT	5
-#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT	6
-#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT	7
-#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT	8
-#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT	9
-#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT	10
-#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT	11
-#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT	12
-#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT	13
-#define CE_ADM_INT_PCIE_MSG_SHFT		14 /*see int_dest_14*/
-#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT		14
-#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT		15
-#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT		16
-#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT		17
-#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT	22
-#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT	23
-
-/* ce_adm_force_int register bit defines */
-#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT	0
-#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT	1
-#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT	2
-#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT	3
-#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT	4
-#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT	5
-#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT	6
-#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT	7
-#define CE_ADM_FORCE_INT_ALWAYS_SHFT		8
-
-/* ce_adm_int_dest register bit masks & shifts */
-#define INTR_VECTOR_SHFT			56
-
-/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
-#define CE_ADM_ERR_CRM_SSP_REQ_INVALID			(0x1ULL <<  0)
-#define CE_ADM_ERR_SSP_REQ_HEADER			(0x1ULL <<  1)
-#define CE_ADM_ERR_SSP_RSP_HEADER			(0x1ULL <<  2)
-#define CE_ADM_ERR_SSP_PROTOCOL_ERROR			(0x1ULL <<  3)
-#define CE_ADM_ERR_SSP_SBE				(0x1ULL <<  4)
-#define CE_ADM_ERR_SSP_MBE				(0x1ULL <<  5)
-#define CE_ADM_ERR_CXM_CREDIT_OFLOW			(0x1ULL <<  6)
-#define CE_ADM_ERR_DRE_SSP_REQ_INVAL			(0x1ULL <<  7)
-#define CE_ADM_ERR_SSP_REQ_LONG				(0x1ULL <<  8)
-#define CE_ADM_ERR_SSP_REQ_OFLOW			(0x1ULL <<  9)
-#define CE_ADM_ERR_SSP_REQ_SHORT			(0x1ULL << 10)
-#define CE_ADM_ERR_SSP_REQ_SIDEBAND			(0x1ULL << 11)
-#define CE_ADM_ERR_SSP_REQ_ADDR_ERR			(0x1ULL << 12)
-#define CE_ADM_ERR_SSP_REQ_BAD_BE			(0x1ULL << 13)
-#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT			(0x1ULL << 14)
-#define CE_ADM_ERR_PCIE_UNEXP_COMPL			(0x1ULL << 15)
-#define CE_ADM_ERR_PCIE_ERR_COMPL			(0x1ULL << 16)
-#define CE_ADM_ERR_DRE_CREDIT_OFLOW			(0x1ULL << 17)
-#define CE_ADM_ERR_DRE_SRAM_PE				(0x1ULL << 18)
-#define CE_ADM_ERR_SSP_RSP_INVALID			(0x1ULL << 19)
-#define CE_ADM_ERR_SSP_RSP_LONG				(0x1ULL << 20)
-#define CE_ADM_ERR_SSP_RSP_SHORT			(0x1ULL << 21)
-#define CE_ADM_ERR_SSP_RSP_SIDEBAND			(0x1ULL << 22)
-#define CE_ADM_ERR_URE_SSP_RSP_UNEXP			(0x1ULL << 23)
-#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT		(0x1ULL << 24)
-#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT		(0x1ULL << 25)
-#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT		(0x1ULL << 26)
-#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT			(0x1ULL << 27)
-#define CE_ADM_ERR_URE_CREDIT_OFLOW			(0x1ULL << 28)
-#define CE_ADM_ERR_URE_SRAM_PE				(0x1ULL << 29)
-#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP			(0x1ULL << 30)
-#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT			(0x1ULL << 31)
-#define CE_ADM_ERR_MMR_ACCESS_ERROR			(0x1ULL << 32)
-#define CE_ADM_ERR_MMR_ADDR_ERROR			(0x1ULL << 33)
-#define CE_ADM_ERR_ADM_CREDIT_OFLOW			(0x1ULL << 34)
-#define CE_ADM_ERR_ADM_SRAM_PE				(0x1ULL << 35)
-#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR		(0x1ULL << 36)
-#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR		(0x1ULL << 37)
-#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR	(0x1ULL << 38)
-#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR	(0x1ULL << 39)
-#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR		(0x1ULL << 40)
-#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR		(0x1ULL << 41)
-#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR		(0x1ULL << 42)
-#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR		(0x1ULL << 43)
-#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR		(0x1ULL << 44)
-#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR		(0x1ULL << 45)
-#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR		(0x1ULL << 46)
-#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR		(0x1ULL << 47)
-#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR	(0x1ULL << 48)
-#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR	(0x1ULL << 49)
-#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR		(0x1ULL << 50)
-#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR		(0x1ULL << 51)
-#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR		(0x1ULL << 52)
-#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR		(0x1ULL << 53)
-#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR		(0x1ULL << 54)
-#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR		(0x1ULL << 55)
-#define CE_ADM_ERR_PORT1_PCIE_COR_ERR			(0x1ULL << 56)
-#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR			(0x1ULL << 57)
-#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR			(0x1ULL << 58)
-#define CE_ADM_ERR_PORT2_PCIE_COR_ERR			(0x1ULL << 59)
-#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR			(0x1ULL << 60)
-#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR			(0x1ULL << 61)
-
-/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
-#define FLUSH_SEL_PORT1_PIPE0_SHFT	0
-#define FLUSH_SEL_PORT1_PIPE1_SHFT	4
-#define FLUSH_SEL_PORT1_PIPE2_SHFT	8
-#define FLUSH_SEL_PORT1_PIPE3_SHFT	12
-#define FLUSH_SEL_PORT2_PIPE0_SHFT	16
-#define FLUSH_SEL_PORT2_PIPE1_SHFT	20
-#define FLUSH_SEL_PORT2_PIPE2_SHFT	24
-#define FLUSH_SEL_PORT2_PIPE3_SHFT	28
-
-/* ce_dre_config1 register bit masks and shifts */
-#define CE_DRE_RO_ENABLE		(0x1ULL << 0)
-#define CE_DRE_DYN_RO_ENABLE		(0x1ULL << 1)
-#define CE_DRE_SUP_CONFIG_COMP_ERROR	(0x1ULL << 2)
-#define CE_DRE_SUP_IO_COMP_ERROR	(0x1ULL << 3)
-#define CE_DRE_ADDR_MODE_SHFT		4
-
-/* ce_dre_config_req_status register bit masks */
-#define CE_DRE_LAST_CONFIG_COMPLETION	(0x7ULL << 0)
-#define CE_DRE_DOWNSTREAM_CONFIG_ERROR	(0x1ULL << 3)
-#define CE_DRE_CONFIG_COMPLETION_VALID	(0x1ULL << 4)
-#define CE_DRE_CONFIG_REQUEST_ACTIVE	(0x1ULL << 5)
-
-/* ce_ure_control register bit masks & shifts */
-#define CE_URE_RD_MRG_ENABLE		(0x1ULL << 0)
-#define CE_URE_WRT_MRG_ENABLE1		(0x1ULL << 4)
-#define CE_URE_WRT_MRG_ENABLE2		(0x1ULL << 5)
-#define CE_URE_WRT_MRG_TIMER_SHFT	12
-#define CE_URE_WRT_MRG_TIMER_MASK	(0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
-#define CE_URE_WRT_MRG_TIMER(x)		(((u64)(x) << \
-					  CE_URE_WRT_MRG_TIMER_SHFT) & \
-					 CE_URE_WRT_MRG_TIMER_MASK)
-#define CE_URE_RSPQ_BYPASS_DISABLE	(0x1ULL << 24)
-#define CE_URE_UPS_DAT1_PAR_DISABLE	(0x1ULL << 32)
-#define CE_URE_UPS_HDR1_PAR_DISABLE	(0x1ULL << 33)
-#define CE_URE_UPS_DAT2_PAR_DISABLE	(0x1ULL << 34)
-#define CE_URE_UPS_HDR2_PAR_DISABLE	(0x1ULL << 35)
-#define CE_URE_ATE_PAR_DISABLE		(0x1ULL << 36)
-#define CE_URE_RCI_PAR_DISABLE		(0x1ULL << 37)
-#define CE_URE_RSPQ_PAR_DISABLE		(0x1ULL << 38)
-#define CE_URE_DNS_DAT_PAR_DISABLE	(0x1ULL << 39)
-#define CE_URE_DNS_HDR_PAR_DISABLE	(0x1ULL << 40)
-#define CE_URE_MALFORM_DISABLE		(0x1ULL << 44)
-#define CE_URE_UNSUP_DISABLE		(0x1ULL << 45)
-
-/* ce_ure_page_map register bit masks & shifts */
-#define CE_URE_ATE3240_ENABLE		(0x1ULL << 0)
-#define CE_URE_ATE40_ENABLE 		(0x1ULL << 1)
-#define CE_URE_PAGESIZE_SHFT		4
-#define CE_URE_PAGESIZE_MASK		(0x7ULL << CE_URE_PAGESIZE_SHFT)
-#define CE_URE_4K_PAGESIZE		(0x0ULL << CE_URE_PAGESIZE_SHFT)
-#define CE_URE_16K_PAGESIZE		(0x1ULL << CE_URE_PAGESIZE_SHFT)
-#define CE_URE_64K_PAGESIZE		(0x2ULL << CE_URE_PAGESIZE_SHFT)
-#define CE_URE_128K_PAGESIZE		(0x3ULL << CE_URE_PAGESIZE_SHFT)
-#define CE_URE_256K_PAGESIZE		(0x4ULL << CE_URE_PAGESIZE_SHFT)
-
-/* ce_ure_pipe_sel register bit masks & shifts */
-#define PKT_TRAFIC_SHRT			16
-#define BUS_SRC_ID_SHFT			8
-#define DEV_SRC_ID_SHFT			3
-#define FNC_SRC_ID_SHFT			0
-#define CE_URE_TC_MASK			(0x07ULL << PKT_TRAFIC_SHRT)
-#define CE_URE_BUS_MASK			(0xFFULL << BUS_SRC_ID_SHFT)
-#define CE_URE_DEV_MASK			(0x1FULL << DEV_SRC_ID_SHFT)
-#define CE_URE_FNC_MASK			(0x07ULL << FNC_SRC_ID_SHFT)
-#define CE_URE_PIPE_BUS(b)		(((u64)(b) << BUS_SRC_ID_SHFT) & \
-					 CE_URE_BUS_MASK)
-#define CE_URE_PIPE_DEV(d)		(((u64)(d) << DEV_SRC_ID_SHFT) & \
-					 CE_URE_DEV_MASK)
-#define CE_URE_PIPE_FNC(f)		(((u64)(f) << FNC_SRC_ID_SHFT) & \
-					 CE_URE_FNC_MASK)
-
-#define CE_URE_SEL1_SHFT		0
-#define CE_URE_SEL2_SHFT		20
-#define CE_URE_SEL3_SHFT		40
-#define CE_URE_SEL1_MASK		(0x7FFFFULL << CE_URE_SEL1_SHFT)
-#define CE_URE_SEL2_MASK		(0x7FFFFULL << CE_URE_SEL2_SHFT)
-#define CE_URE_SEL3_MASK		(0x7FFFFULL << CE_URE_SEL3_SHFT)
-
-
-/* ce_ure_pipe_mask register bit masks & shifts */
-#define CE_URE_MASK1_SHFT		0
-#define CE_URE_MASK2_SHFT		20
-#define CE_URE_MASK3_SHFT		40
-#define CE_URE_MASK1_MASK		(0x7FFFFULL << CE_URE_MASK1_SHFT)
-#define CE_URE_MASK2_MASK		(0x7FFFFULL << CE_URE_MASK2_SHFT)
-#define CE_URE_MASK3_MASK		(0x7FFFFULL << CE_URE_MASK3_SHFT)
-
-
-/* ce_ure_pcie_control1 register bit masks & shifts */
-#define CE_URE_SI			(0x1ULL << 0)
-#define CE_URE_ELAL_SHFT		4
-#define CE_URE_ELAL_MASK		(0x7ULL << CE_URE_ELAL_SHFT)
-#define CE_URE_ELAL_SET(n)		(((u64)(n) << CE_URE_ELAL_SHFT) & \
-					 CE_URE_ELAL_MASK)
-#define CE_URE_ELAL1_SHFT		8
-#define CE_URE_ELAL1_MASK		(0x7ULL << CE_URE_ELAL1_SHFT)
-#define CE_URE_ELAL1_SET(n)		(((u64)(n) << CE_URE_ELAL1_SHFT) & \
-					 CE_URE_ELAL1_MASK)
-#define CE_URE_SCC			(0x1ULL << 12)
-#define CE_URE_PN1_SHFT			16
-#define CE_URE_PN1_MASK			(0xFFULL << CE_URE_PN1_SHFT)
-#define CE_URE_PN2_SHFT			24
-#define CE_URE_PN2_MASK			(0xFFULL << CE_URE_PN2_SHFT)
-#define CE_URE_PN1_SET(n)		(((u64)(n) << CE_URE_PN1_SHFT) & \
-					 CE_URE_PN1_MASK)
-#define CE_URE_PN2_SET(n)		(((u64)(n) << CE_URE_PN2_SHFT) & \
-					 CE_URE_PN2_MASK)
-
-/* ce_ure_pcie_control2 register bit masks & shifts */
-#define CE_URE_ABP			(0x1ULL << 0)
-#define CE_URE_PCP			(0x1ULL << 1)
-#define CE_URE_MSP			(0x1ULL << 2)
-#define CE_URE_AIP			(0x1ULL << 3)
-#define CE_URE_PIP			(0x1ULL << 4)
-#define CE_URE_HPS			(0x1ULL << 5)
-#define CE_URE_HPC			(0x1ULL << 6)
-#define CE_URE_SPLV_SHFT		7
-#define CE_URE_SPLV_MASK		(0xFFULL << CE_URE_SPLV_SHFT)
-#define CE_URE_SPLV_SET(n)		(((u64)(n) << CE_URE_SPLV_SHFT) & \
-					 CE_URE_SPLV_MASK)
-#define CE_URE_SPLS_SHFT		15
-#define CE_URE_SPLS_MASK		(0x3ULL << CE_URE_SPLS_SHFT)
-#define CE_URE_SPLS_SET(n)		(((u64)(n) << CE_URE_SPLS_SHFT) & \
-					 CE_URE_SPLS_MASK)
-#define CE_URE_PSN1_SHFT		19
-#define CE_URE_PSN1_MASK		(0x1FFFULL << CE_URE_PSN1_SHFT)
-#define CE_URE_PSN2_SHFT		32
-#define CE_URE_PSN2_MASK		(0x1FFFULL << CE_URE_PSN2_SHFT)
-#define CE_URE_PSN1_SET(n)		(((u64)(n) << CE_URE_PSN1_SHFT) & \
-					 CE_URE_PSN1_MASK)
-#define CE_URE_PSN2_SET(n)		(((u64)(n) << CE_URE_PSN2_SHFT) & \
-					 CE_URE_PSN2_MASK)
-
-/*
- * PIO address space ranges for CE
- */
-
-/* Local CE Registers Space */
-#define CE_PIO_MMR			0x00000000
-#define CE_PIO_MMR_LEN			0x04000000
-
-/* PCI Compatible Config Space */
-#define CE_PIO_CONFIG_SPACE		0x04000000
-#define CE_PIO_CONFIG_SPACE_LEN		0x04000000
-
-/* PCI I/O Space Alias */
-#define CE_PIO_IO_SPACE_ALIAS		0x08000000
-#define CE_PIO_IO_SPACE_ALIAS_LEN	0x08000000
-
-/* PCI Enhanced Config Space */
-#define CE_PIO_E_CONFIG_SPACE		0x10000000
-#define CE_PIO_E_CONFIG_SPACE_LEN	0x10000000
-
-/* PCI I/O Space */
-#define CE_PIO_IO_SPACE			0x100000000
-#define CE_PIO_IO_SPACE_LEN		0x100000000
-
-/* PCI MEM Space */
-#define CE_PIO_MEM_SPACE		0x200000000
-#define CE_PIO_MEM_SPACE_LEN		TIO_HWIN_SIZE
-
-
-/*
- * CE PCI Enhanced Config Space shifts & masks
- */
-#define CE_E_CONFIG_BUS_SHFT		20
-#define CE_E_CONFIG_BUS_MASK		(0xFF << CE_E_CONFIG_BUS_SHFT)
-#define CE_E_CONFIG_DEVICE_SHFT		15
-#define CE_E_CONFIG_DEVICE_MASK		(0x1F << CE_E_CONFIG_DEVICE_SHFT)
-#define CE_E_CONFIG_FUNC_SHFT		12
-#define CE_E_CONFIG_FUNC_MASK		(0x7  << CE_E_CONFIG_FUNC_SHFT)
-
-#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/arch/ia64/include/asm/sn/tioce_provider.h b/arch/ia64/include/asm/sn/tioce_provider.h
deleted file mode 100644
index 32c32f30b099..000000000000
--- a/arch/ia64/include/asm/sn/tioce_provider.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_CE_PROVIDER_H
-#define _ASM_IA64_SN_CE_PROVIDER_H
-
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/tioce.h>
-
-/*
- * Common TIOCE structure shared between the prom and kernel
- *
- * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
- * PROM VERSION.
- */
-struct tioce_common {
-	struct pcibus_bussoft	ce_pcibus;	/* common pciio header */
-
-	u32		ce_rev;
-	u64		ce_kernel_private;
-	u64		ce_prom_private;
-};
-
-struct tioce_kernel {
-	struct tioce_common	*ce_common;
-	spinlock_t		ce_lock;
-	struct list_head	ce_dmamap_list;
-
-	u64		ce_ate40_shadow[TIOCE_NUM_M40_ATES];
-	u64		ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
-	u32		ce_ate3240_pagesize;
-
-	u8			ce_port1_secondary;
-
-	/* per-port resources */
-	struct {
-		int 		dirmap_refcnt;
-		u64	dirmap_shadow;
-	} ce_port[TIOCE_NUM_PORTS];
-};
-
-struct tioce_dmamap {
-	struct list_head	ce_dmamap_list;	/* headed by tioce_kernel */
-	u32		refcnt;
-
-	u64		nbytes;		/* # bytes mapped */
-
-	u64		ct_start;	/* coretalk start address */
-	u64		pci_start;	/* bus start address */
-
-	u64		__iomem *ate_hw;/* hw ptr of first ate in map */
-	u64		*ate_shadow;	/* shadow ptr of firat ate */
-	u16		ate_count;	/* # ate's in the map */
-};
-
-extern int tioce_init_provider(void);
-
-#endif  /* __ASM_IA64_SN_CE_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/tiocp.h b/arch/ia64/include/asm/sn/tiocp.h
deleted file mode 100644
index e8ad0bb5b6c5..000000000000
--- a/arch/ia64/include/asm/sn/tiocp.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_PCI_TIOCP_H
-#define _ASM_IA64_SN_PCI_TIOCP_H
-
-#define TIOCP_HOST_INTR_ADDR            0x003FFFFFFFFFFFFFUL
-#define TIOCP_PCI64_CMDTYPE_MEM         (0x1ull << 60)
-#define TIOCP_PCI64_CMDTYPE_MSI         (0x3ull << 60)
-
-
-/*****************************************************************************
- *********************** TIOCP MMR structure mapping ***************************
- *****************************************************************************/
-
-struct tiocp{
-
-    /* 0x000000-0x00FFFF -- Local Registers */
-
-    /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
-    u64		cp_id;				/* 0x000000 */
-    u64		cp_stat;			/* 0x000008 */
-    u64		cp_err_upper;			/* 0x000010 */
-    u64		cp_err_lower;			/* 0x000018 */
-    #define cp_err cp_err_lower
-    u64		cp_control;			/* 0x000020 */
-    u64		cp_req_timeout;			/* 0x000028 */
-    u64		cp_intr_upper;			/* 0x000030 */
-    u64		cp_intr_lower;			/* 0x000038 */
-    #define cp_intr cp_intr_lower
-    u64		cp_err_cmdword;			/* 0x000040 */
-    u64		_pad_000048;			/* 0x000048 */
-    u64		cp_tflush;			/* 0x000050 */
-
-    /* 0x000058-0x00007F -- Bridge-specific Configuration */
-    u64		cp_aux_err;			/* 0x000058 */
-    u64		cp_resp_upper;			/* 0x000060 */
-    u64		cp_resp_lower;			/* 0x000068 */
-    #define cp_resp cp_resp_lower
-    u64		cp_tst_pin_ctrl;		/* 0x000070 */
-    u64		cp_addr_lkerr;			/* 0x000078 */
-
-    /* 0x000080-0x00008F -- PMU & MAP */
-    u64		cp_dir_map;			/* 0x000080 */
-    u64		_pad_000088;			/* 0x000088 */
-
-    /* 0x000090-0x00009F -- SSRAM */
-    u64		cp_map_fault;			/* 0x000090 */
-    u64		_pad_000098;			/* 0x000098 */
-
-    /* 0x0000A0-0x0000AF -- Arbitration */
-    u64		cp_arb;				/* 0x0000A0 */
-    u64		_pad_0000A8;			/* 0x0000A8 */
-
-    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
-    u64		cp_ate_parity_err;		/* 0x0000B0 */
-    u64		_pad_0000B8;			/* 0x0000B8 */
-
-    /* 0x0000C0-0x0000FF -- PCI/GIO */
-    u64		cp_bus_timeout;			/* 0x0000C0 */
-    u64		cp_pci_cfg;			/* 0x0000C8 */
-    u64		cp_pci_err_upper;		/* 0x0000D0 */
-    u64		cp_pci_err_lower;		/* 0x0000D8 */
-    #define cp_pci_err cp_pci_err_lower
-    u64		_pad_0000E0[4];			/* 0x0000{E0..F8} */
-
-    /* 0x000100-0x0001FF -- Interrupt */
-    u64		cp_int_status;			/* 0x000100 */
-    u64		cp_int_enable;			/* 0x000108 */
-    u64		cp_int_rst_stat;		/* 0x000110 */
-    u64		cp_int_mode;			/* 0x000118 */
-    u64		cp_int_device;			/* 0x000120 */
-    u64		cp_int_host_err;		/* 0x000128 */
-    u64		cp_int_addr[8];			/* 0x0001{30,,,68} */
-    u64		cp_err_int_view;		/* 0x000170 */
-    u64		cp_mult_int;			/* 0x000178 */
-    u64		cp_force_always[8];		/* 0x0001{80,,,B8} */
-    u64		cp_force_pin[8];		/* 0x0001{C0,,,F8} */
-
-    /* 0x000200-0x000298 -- Device */
-    u64		cp_device[4];			/* 0x0002{00,,,18} */
-    u64		_pad_000220[4];			/* 0x0002{20,,,38} */
-    u64		cp_wr_req_buf[4];		/* 0x0002{40,,,58} */
-    u64		_pad_000260[4];			/* 0x0002{60,,,78} */
-    u64		cp_rrb_map[2];			/* 0x0002{80,,,88} */
-    #define cp_even_resp cp_rrb_map[0]			/* 0x000280 */
-    #define cp_odd_resp  cp_rrb_map[1]			/* 0x000288 */
-    u64		cp_resp_status;			/* 0x000290 */
-    u64		cp_resp_clear;			/* 0x000298 */
-
-    u64		_pad_0002A0[12];		/* 0x0002{A0..F8} */
-
-    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
-    struct {
-	u64	upper;				/* 0x0003{00,,,F0} */
-	u64	lower;				/* 0x0003{08,,,F8} */
-    } cp_buf_addr_match[16];
-
-    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
-    struct {
-	u64	flush_w_touch;			/* 0x000{400,,,5C0} */
-	u64	flush_wo_touch;			/* 0x000{408,,,5C8} */
-	u64	inflight;			/* 0x000{410,,,5D0} */
-	u64	prefetch;			/* 0x000{418,,,5D8} */
-	u64	total_pci_retry;		/* 0x000{420,,,5E0} */
-	u64	max_pci_retry;			/* 0x000{428,,,5E8} */
-	u64	max_latency;			/* 0x000{430,,,5F0} */
-	u64	clear_all;			/* 0x000{438,,,5F8} */
-    } cp_buf_count[8];
-
-
-    /* 0x000600-0x0009FF -- PCI/X registers */
-    u64		cp_pcix_bus_err_addr;		/* 0x000600 */
-    u64		cp_pcix_bus_err_attr;		/* 0x000608 */
-    u64		cp_pcix_bus_err_data;		/* 0x000610 */
-    u64		cp_pcix_pio_split_addr;		/* 0x000618 */
-    u64		cp_pcix_pio_split_attr;		/* 0x000620 */
-    u64		cp_pcix_dma_req_err_attr;	/* 0x000628 */
-    u64		cp_pcix_dma_req_err_addr;	/* 0x000630 */
-    u64		cp_pcix_timeout;		/* 0x000638 */
-
-    u64		_pad_000640[24];		/* 0x000{640,,,6F8} */
-
-    /* 0x000700-0x000737 -- Debug Registers */
-    u64		cp_ct_debug_ctl;		/* 0x000700 */
-    u64		cp_br_debug_ctl;		/* 0x000708 */
-    u64		cp_mux3_debug_ctl;		/* 0x000710 */
-    u64		cp_mux4_debug_ctl;		/* 0x000718 */
-    u64		cp_mux5_debug_ctl;		/* 0x000720 */
-    u64		cp_mux6_debug_ctl;		/* 0x000728 */
-    u64		cp_mux7_debug_ctl;		/* 0x000730 */
-
-    u64		_pad_000738[89];		/* 0x000{738,,,9F8} */
-
-    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
-    struct {
-	u64	cp_buf_addr;			/* 0x000{A00,,,AF0} */
-	u64	cp_buf_attr;			/* 0X000{A08,,,AF8} */
-    } cp_pcix_read_buf_64[16];
-
-    struct {
-	u64	cp_buf_addr;			/* 0x000{B00,,,BE0} */
-	u64	cp_buf_attr;			/* 0x000{B08,,,BE8} */
-	u64	cp_buf_valid;			/* 0x000{B10,,,BF0} */
-	u64	__pad1;				/* 0x000{B18,,,BF8} */
-    } cp_pcix_write_buf_64[8];
-
-    /* End of Local Registers -- Start of Address Map space */
-
-    char	_pad_000c00[0x010000 - 0x000c00];
-
-    /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
-    u64		cp_int_ate_ram[1024];		/* 0x010000-0x011FF8 */
-
-    char	_pad_012000[0x14000 - 0x012000];
-
-    /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
-    u64		cp_int_ate_ram_mp[1024];	/* 0x014000-0x015FF8 */
-
-    char	_pad_016000[0x18000 - 0x016000];
-
-    /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
-    u64		cp_wr_req_lower[256];		/* 0x18000 - 0x187F8 */
-    u64		cp_wr_req_upper[256];		/* 0x18800 - 0x18FF8 */
-    u64		cp_wr_req_parity[256];		/* 0x19000 - 0x197F8 */
-
-    char	_pad_019800[0x1C000 - 0x019800];
-
-    /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
-    u64		cp_rd_resp_lower[512];		/* 0x1C000 - 0x1CFF8 */
-    u64		cp_rd_resp_upper[512];		/* 0x1D000 - 0x1DFF8 */
-    u64		cp_rd_resp_parity[512];		/* 0x1E000 - 0x1EFF8 */
-
-    char	_pad_01F000[0x20000 - 0x01F000];
-
-    /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used)  */
-    char	_pad_020000[0x021000 - 0x20000];
-
-    /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
-    union {
-	u8	c[0x1000 / 1];			/* 0x02{0000,,,7FFF} */
-	u16	s[0x1000 / 2];			/* 0x02{0000,,,7FFF} */
-	u32	l[0x1000 / 4];			/* 0x02{0000,,,7FFF} */
-	u64	d[0x1000 / 8];			/* 0x02{0000,,,7FFF} */
-	union {
-	    u8	c[0x100 / 1];
-	    u16	s[0x100 / 2];
-	    u32	l[0x100 / 4];
-	    u64	d[0x100 / 8];
-	} f[8];
-    } cp_type0_cfg_dev[7];				/* 0x02{1000,,,7FFF} */
-
-    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
-    union {
-	u8	c[0x1000 / 1];			/* 0x028000-0x029000 */
-	u16	s[0x1000 / 2];			/* 0x028000-0x029000 */
-	u32	l[0x1000 / 4];			/* 0x028000-0x029000 */
-	u64	d[0x1000 / 8];			/* 0x028000-0x029000 */
-	union {
-	    u8	c[0x100 / 1];
-	    u16	s[0x100 / 2];
-	    u32	l[0x100 / 4];
-	    u64	d[0x100 / 8];
-	} f[8];
-    } cp_type1_cfg;					/* 0x028000-0x029000 */
-
-    char		_pad_029000[0x030000-0x029000];
-
-    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
-    union {
-	u8	c[8 / 1];
-	u16	s[8 / 2];
-	u32	l[8 / 4];
-	u64	d[8 / 8];
-    } cp_pci_iack;					/* 0x030000-0x030007 */
-
-    char		_pad_030007[0x040000-0x030008];
-
-    /* 0x040000-0x040007 -- PCIX Special Cycle */
-    union {
-	u8	c[8 / 1];
-	u16	s[8 / 2];
-	u32	l[8 / 4];
-	u64	d[8 / 8];
-    } cp_pcix_cycle;					/* 0x040000-0x040007 */
-
-    char		_pad_040007[0x200000-0x040008];
-
-    /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
-    union {
-	u8	c[0x100000 / 1];
-	u16	s[0x100000 / 2];
-	u32	l[0x100000 / 4];
-	u64	d[0x100000 / 8];
-    } cp_devio_raw[6];					/* 0x200000-0x7FFFFF */
-
-    #define cp_devio(n)  cp_devio_raw[((n)<2)?(n*2):(n+2)]
-
-    char		_pad_800000[0xA00000-0x800000];
-
-    /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush  */
-    union {
-	u8	c[0x100000 / 1];
-	u16	s[0x100000 / 2];
-	u32	l[0x100000 / 4];
-	u64	d[0x100000 / 8];
-    } cp_devio_raw_flush[6];				/* 0xA00000-0xBFFFFF */
-
-    #define cp_devio_flush(n)  cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
-
-};
-
-#endif 	/* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/arch/ia64/include/asm/sn/tiocx.h b/arch/ia64/include/asm/sn/tiocx.h
deleted file mode 100644
index d29728492f36..000000000000
--- a/arch/ia64/include/asm/sn/tiocx.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_TIO_TIOCX_H
-#define _ASM_IA64_SN_TIO_TIOCX_H
-
-#ifdef __KERNEL__
-
-struct cx_id_s {
-	unsigned int part_num;
-	unsigned int mfg_num;
-	int nasid;
-};
-
-struct cx_dev {
-	struct cx_id_s cx_id;
-	int bt;				/* board/blade type */
-	void *soft;			/* driver specific */
-	struct hubdev_info *hubdev;
-	struct device dev;
-	struct cx_drv *driver;
-};
-
-struct cx_device_id {
-	unsigned int part_num;
-	unsigned int mfg_num;
-};
-
-struct cx_drv {
-	char *name;
-	const struct cx_device_id *id_table;
-	struct device_driver driver;
-	int (*probe) (struct cx_dev * dev, const struct cx_device_id * id);
-	int (*remove) (struct cx_dev * dev);
-};
-
-/* create DMA address by stripping AS bits */
-#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
-
-#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) |  \
-                                  ((((u64)(a)) & 0xffffc000000000UL) <<2))
-
-#define TIO_CE_ASIC_PARTNUM 0xce00
-#define TIOCX_CORELET 3
-
-/* These are taken from tio_mmr_as.h */
-#define TIO_ICE_FRZ_CFG               TIO_MMR_ADDR_MOD(0x00000000b0008100UL)
-#define TIO_ICE_PMI_TX_CFG            TIO_MMR_ADDR_MOD(0x00000000b000b100UL)
-#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3 TIO_MMR_ADDR_MOD(0x00000000b000be18UL)
-#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK 0x000000000000000fUL
-
-#define to_cx_dev(n) container_of(n, struct cx_dev, dev)
-#define to_cx_driver(drv) container_of(drv, struct cx_drv, driver)
-
-extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
-extern void tiocx_irq_free(struct sn_irq_info *);
-extern int cx_device_unregister(struct cx_dev *);
-extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
-extern int cx_driver_unregister(struct cx_drv *);
-extern int cx_driver_register(struct cx_drv *);
-extern u64 tiocx_dma_addr(u64 addr);
-extern u64 tiocx_swin_base(int nasid);
-extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
-extern u64 tiocx_mmr_load(int nasid, u64 offset);
-
-#endif				//  __KERNEL__
-#endif				// _ASM_IA64_SN_TIO_TIOCX__
diff --git a/arch/ia64/include/asm/sn/types.h b/arch/ia64/include/asm/sn/types.h
deleted file mode 100644
index 8e04ee211e59..000000000000
--- a/arch/ia64/include/asm/sn/types.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc.  All Rights Reserved.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_IA64_SN_TYPES_H
-#define _ASM_IA64_SN_TYPES_H
-
-#include <linux/types.h>
-
-typedef unsigned long 	cpuid_t;
-typedef signed short	nasid_t;	/* node id in numa-as-id space */
-typedef signed char	partid_t;	/* partition ID type */
-typedef unsigned int    moduleid_t;     /* user-visible module number type */
-typedef unsigned int    cmoduleid_t;    /* kernel compact module id type */
-typedef unsigned char	slotid_t;	/* slot (blade) within module */
-typedef unsigned char	slabid_t;	/* slab (asic) within slot */
-typedef u64 nic_t;
-typedef unsigned long iopaddr_t;
-typedef unsigned long paddr_t;
-typedef short cnodeid_t;
-
-#endif /* _ASM_IA64_SN_TYPES_H */
diff --git a/arch/ia64/include/asm/switch_to.h b/arch/ia64/include/asm/switch_to.h
index b10f31ec522c..9011e90a6b97 100644
--- a/arch/ia64/include/asm/switch_to.h
+++ b/arch/ia64/include/asm/switch_to.h
@@ -69,7 +69,6 @@ extern void ia64_load_extra (struct task_struct *task);
 	if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) &&	       \
 		     (task_cpu(current) !=				       \
 		      		      task_thread_info(current)->last_cpu))) { \
-		platform_migrate(current);				       \
 		task_thread_info(current)->last_cpu = task_cpu(current);       \
 	}								       \
 } while (0)
diff --git a/arch/ia64/include/asm/tlb.h b/arch/ia64/include/asm/tlb.h
index 86ec034ba499..f1f257d632b3 100644
--- a/arch/ia64/include/asm/tlb.h
+++ b/arch/ia64/include/asm/tlb.h
@@ -45,7 +45,6 @@
 #include <asm/pgalloc.h>
 #include <asm/processor.h>
 #include <asm/tlbflush.h>
-#include <asm/machvec.h>
 
 #include <asm-generic/tlb.h>
 
diff --git a/arch/ia64/include/asm/uv/uv.h b/arch/ia64/include/asm/uv/uv.h
index 71df93ee3bc0..48d4526bf4cd 100644
--- a/arch/ia64/include/asm/uv/uv.h
+++ b/arch/ia64/include/asm/uv/uv.h
@@ -2,12 +2,29 @@
 #ifndef _ASM_IA64_UV_UV_H
 #define _ASM_IA64_UV_UV_H
 
-#include <asm/sn/simulator.h>
+#ifdef CONFIG_IA64_SGI_UV
+extern bool ia64_is_uv;
 
 static inline int is_uv_system(void)
 {
-	/* temporary support for running on hardware simulator */
-	return IS_MEDUSA() || ia64_platform_is("uv");
+	return ia64_is_uv;
 }
 
+void __init uv_probe_system_type(void);
+void __init uv_setup(char **cmdline_p);
+#else /* CONFIG_IA64_SGI_UV */
+static inline int is_uv_system(void)
+{
+	return false;
+}
+
+static inline void __init uv_probe_system_type(void)
+{
+}
+
+static inline void __init uv_setup(char **cmdline_p)
+{
+}
+#endif /* CONFIG_IA64_SGI_UV */
+
 #endif	/* _ASM_IA64_UV_UV_H */
diff --git a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile
index 4ba05140b249..1a8df6669eee 100644
--- a/arch/ia64/kernel/Makefile
+++ b/arch/ia64/kernel/Makefile
@@ -10,15 +10,14 @@ endif
 extra-y	:= head.o vmlinux.lds
 
 obj-y := entry.o efi.o efi_stub.o gate-data.o fsys.o ia64_ksyms.o irq.o irq_ia64.o	\
-	 irq_lsapic.o ivt.o machvec.o pal.o patch.o process.o perfmon.o ptrace.o sal.o		\
+	 irq_lsapic.o ivt.o pal.o patch.o process.o perfmon.o ptrace.o sal.o		\
 	 salinfo.o setup.o signal.o sys_ia64.o time.o traps.o unaligned.o \
-	 unwind.o mca.o mca_asm.o topology.o dma-mapping.o
+	 unwind.o mca.o mca_asm.o topology.o dma-mapping.o iosapic.o acpi.o \
+	 acpi-ext.o
 
-obj-$(CONFIG_ACPI)		+= acpi.o acpi-ext.o
 obj-$(CONFIG_IA64_BRL_EMU)	+= brl_emu.o
 
 obj-$(CONFIG_IA64_PALINFO)	+= palinfo.o
-obj-$(CONFIG_IOSAPIC)		+= iosapic.o
 obj-$(CONFIG_MODULES)		+= module.o
 obj-$(CONFIG_SMP)		+= smp.o smpboot.o
 obj-$(CONFIG_NUMA)		+= numa.o
@@ -31,7 +30,7 @@ obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o crash.o
 obj-$(CONFIG_CRASH_DUMP)	+= crash_dump.o
 obj-$(CONFIG_IA64_UNCACHED_ALLOCATOR)	+= uncached.o
 obj-$(CONFIG_AUDIT)		+= audit.o
-obj-$(CONFIG_PCI_MSI)		+= msi_ia64.o
+obj-y				+= msi_ia64.o
 mca_recovery-y			+= mca_drv.o mca_drv_asm.o
 obj-$(CONFIG_IA64_MC_ERR_INJECT)+= err_inject.o
 obj-$(CONFIG_STACKTRACE)	+= stacktrace.o
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index c597ab5275b8..70d1587ddcd4 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -31,7 +31,6 @@
 #include <acpi/processor.h>
 #include <asm/io.h>
 #include <asm/iosapic.h>
-#include <asm/machvec.h>
 #include <asm/page.h>
 #include <asm/numa.h>
 #include <asm/sal.h>
@@ -45,77 +44,6 @@ unsigned int acpi_cpei_phys_cpuid;
 
 unsigned long acpi_wakeup_address = 0;
 
-#ifdef CONFIG_IA64_GENERIC
-static unsigned long __init acpi_find_rsdp(void)
-{
-	unsigned long rsdp_phys = 0;
-
-	if (efi.acpi20 != EFI_INVALID_TABLE_ADDR)
-		rsdp_phys = efi.acpi20;
-	else if (efi.acpi != EFI_INVALID_TABLE_ADDR)
-		printk(KERN_WARNING PREFIX
-		       "v1.0/r0.71 tables no longer supported\n");
-	return rsdp_phys;
-}
-
-const char __init *
-acpi_get_sysname(void)
-{
-	unsigned long rsdp_phys;
-	struct acpi_table_rsdp *rsdp;
-	struct acpi_table_xsdt *xsdt;
-	struct acpi_table_header *hdr;
-#ifdef CONFIG_INTEL_IOMMU
-	u64 i, nentries;
-#endif
-
-	rsdp_phys = acpi_find_rsdp();
-	if (!rsdp_phys) {
-		printk(KERN_ERR
-		       "ACPI 2.0 RSDP not found, default to \"dig\"\n");
-		return "dig";
-	}
-
-	rsdp = (struct acpi_table_rsdp *)__va(rsdp_phys);
-	if (strncmp(rsdp->signature, ACPI_SIG_RSDP, sizeof(ACPI_SIG_RSDP) - 1)) {
-		printk(KERN_ERR
-		       "ACPI 2.0 RSDP signature incorrect, default to \"dig\"\n");
-		return "dig";
-	}
-
-	xsdt = (struct acpi_table_xsdt *)__va(rsdp->xsdt_physical_address);
-	hdr = &xsdt->header;
-	if (strncmp(hdr->signature, ACPI_SIG_XSDT, sizeof(ACPI_SIG_XSDT) - 1)) {
-		printk(KERN_ERR
-		       "ACPI 2.0 XSDT signature incorrect, default to \"dig\"\n");
-		return "dig";
-	}
-
-	if (!strcmp(hdr->oem_id, "HP")) {
-		return "hpzx1";
-	} else if (!strcmp(hdr->oem_id, "SGI")) {
-		if (!strcmp(hdr->oem_table_id + 4, "UV"))
-			return "uv";
-		else
-			return "sn2";
-	}
-
-#ifdef CONFIG_INTEL_IOMMU
-	/* Look for Intel IOMMU */
-	nentries = (hdr->length - sizeof(*hdr)) /
-			 sizeof(xsdt->table_offset_entry[0]);
-	for (i = 0; i < nentries; i++) {
-		hdr = __va(xsdt->table_offset_entry[i]);
-		if (strncmp(hdr->signature, ACPI_SIG_DMAR,
-			sizeof(ACPI_SIG_DMAR) - 1) == 0)
-			return "dig_vtd";
-	}
-#endif
-
-	return "dig";
-}
-#endif /* CONFIG_IA64_GENERIC */
-
 #define ACPI_MAX_PLATFORM_INTERRUPTS	256
 
 /* Array to record platform interrupt vectors for generic interrupt routing. */
@@ -407,7 +335,7 @@ get_processor_proximity_domain(struct acpi_srat_cpu_affinity *pa)
 	int pxm;
 
 	pxm = pa->proximity_domain_lo;
-	if (ia64_platform_is("sn2") || acpi_srat_revision >= 2)
+	if (acpi_srat_revision >= 2)
 		pxm += pa->proximity_domain_hi[0] << 8;
 	return pxm;
 }
@@ -418,7 +346,7 @@ get_memory_proximity_domain(struct acpi_srat_mem_affinity *ma)
 	int pxm;
 
 	pxm = ma->proximity_domain;
-	if (!ia64_platform_is("sn2") && acpi_srat_revision <= 1)
+	if (acpi_srat_revision <= 1)
 		pxm &= 0xff;
 
 	return pxm;
@@ -710,9 +638,8 @@ int __init acpi_boot_init(void)
 
 	if (acpi_table_parse_madt
 	    (ACPI_MADT_TYPE_IO_SAPIC, acpi_parse_iosapic, NR_IOSAPICS) < 1) {
-		if (!ia64_platform_is("sn2"))
-			printk(KERN_ERR PREFIX
-			       "Error parsing MADT - no IOSAPIC entries\n");
+		printk(KERN_ERR PREFIX
+		       "Error parsing MADT - no IOSAPIC entries\n");
 	}
 
 	/* System-Level Interrupt Routing */
diff --git a/arch/ia64/kernel/dma-mapping.c b/arch/ia64/kernel/dma-mapping.c
index ad7d9963de34..4a3262795890 100644
--- a/arch/ia64/kernel/dma-mapping.c
+++ b/arch/ia64/kernel/dma-mapping.c
@@ -1,6 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <linux/dma-direct.h>
-#include <linux/swiotlb.h>
 #include <linux/export.h>
 
 /* Set this to 1 if there is a HW IOMMU in the system */
@@ -9,13 +8,6 @@ int iommu_detected __read_mostly;
 const struct dma_map_ops *dma_ops;
 EXPORT_SYMBOL(dma_ops);
 
-const struct dma_map_ops *dma_get_ops(struct device *dev)
-{
-	return dma_ops;
-}
-EXPORT_SYMBOL(dma_get_ops);
-
-#ifdef CONFIG_SWIOTLB
 void *arch_dma_alloc(struct device *dev, size_t size,
 		dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
 {
@@ -33,9 +25,3 @@ long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr,
 {
 	return page_to_pfn(virt_to_page(cpu_addr));
 }
-
-void __init swiotlb_dma_init(void)
-{
-	swiotlb_init(1);
-}
-#endif
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index fe6e4946672e..fad4db20ce65 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -67,10 +67,7 @@
  *     used as architecture-independent interrupt handling mechanism in Linux.
  *     As an IRQ is a number, we have to have
  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
- *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
- *     platform can implement platform_irq_to_vector(irq) and
- *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
- *     Please see also arch/ia64/include/asm/hw_irq.h for those APIs.
+ *     systems, we use one-to-one mapping between IA-64 vector and IRQ.
  *
  * To sum up, there are three levels of mappings involved:
  *
@@ -96,7 +93,6 @@
 #include <asm/hw_irq.h>
 #include <asm/io.h>
 #include <asm/iosapic.h>
-#include <asm/machvec.h>
 #include <asm/processor.h>
 #include <asm/ptrace.h>
 
@@ -646,10 +642,8 @@ get_target_cpu (unsigned int gsi, int irq)
 	if (!cpu_online(smp_processor_id()))
 		return cpu_physical_id(smp_processor_id());
 
-#ifdef CONFIG_ACPI
 	if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
 		return get_cpei_target_cpu();
-#endif
 
 #ifdef CONFIG_NUMA
 	{
diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c
index 8ed81b252694..0a8e5e585edc 100644
--- a/arch/ia64/kernel/irq.c
+++ b/arch/ia64/kernel/irq.c
@@ -35,18 +35,6 @@ void ack_bad_irq(unsigned int irq)
 	printk(KERN_ERR "Unexpected irq vector 0x%x on CPU %u!\n", irq, smp_processor_id());
 }
 
-#ifdef CONFIG_IA64_GENERIC
-ia64_vector __ia64_irq_to_vector(int irq)
-{
-	return irq_cfg[irq].vector;
-}
-
-unsigned int __ia64_local_vector_to_irq (ia64_vector vec)
-{
-	return __this_cpu_read(vector_irq[vec]);
-}
-#endif
-
 /*
  * Interrupt statistics:
  */
@@ -73,17 +61,6 @@ void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
 		irq_redir[irq] = (char) (redir & 0xff);
 	}
 }
-
-bool is_affinity_mask_valid(const struct cpumask *cpumask)
-{
-	if (ia64_platform_is("sn2")) {
-		/* Only allow one CPU to be specified in the smp_affinity mask */
-		if (cpumask_weight(cpumask) != 1)
-			return false;
-	}
-	return true;
-}
-
 #endif /* CONFIG_SMP */
 
 int __init arch_early_irq_init(void)
diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c
index ab87d6c25b15..f10208478131 100644
--- a/arch/ia64/kernel/irq_ia64.c
+++ b/arch/ia64/kernel/irq_ia64.c
@@ -37,7 +37,6 @@
 #include <asm/intrinsics.h>
 #include <asm/io.h>
 #include <asm/hw_irq.h>
-#include <asm/machvec.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 
@@ -53,7 +52,6 @@
 #define IRQ_USED		(1)
 #define IRQ_RSVD		(2)
 
-/* These can be overridden in platform_irq_init */
 int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
 int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
 
@@ -250,7 +248,7 @@ void __setup_vector_irq(int cpu)
 	}
 }
 
-#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
+#ifdef CONFIG_SMP
 
 static enum vector_domain_type {
 	VECTOR_DOMAIN_NONE,
@@ -314,7 +312,7 @@ void irq_complete_move(unsigned irq)
 	cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask);
 	cfg->move_cleanup_count = cpumask_weight(&cleanup_mask);
 	for_each_cpu(i, &cleanup_mask)
-		platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
+		ia64_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
 	cfg->move_in_progress = 0;
 }
 
@@ -634,21 +632,16 @@ ia64_native_register_ipi(void)
 void __init
 init_IRQ (void)
 {
-#ifdef CONFIG_ACPI
 	acpi_boot_init();
-#endif
 	ia64_register_ipi();
 	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
 #ifdef CONFIG_SMP
-#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
 	if (vector_domain_type != VECTOR_DOMAIN_NONE)
 		register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
 #endif
-#endif
 #ifdef CONFIG_PERFMON
 	pfm_init_percpu();
 #endif
-	platform_irq_init();
 }
 
 void
diff --git a/arch/ia64/kernel/kprobes.c b/arch/ia64/kernel/kprobes.c
index 5de801a2c0f0..b8356edbde65 100644
--- a/arch/ia64/kernel/kprobes.c
+++ b/arch/ia64/kernel/kprobes.c
@@ -979,32 +979,6 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
 	return ret;
 }
 
-struct param_bsp_cfm {
-	unsigned long ip;
-	unsigned long *bsp;
-	unsigned long cfm;
-};
-
-static void ia64_get_bsp_cfm(struct unw_frame_info *info, void *arg)
-{
-	unsigned long ip;
-	struct param_bsp_cfm *lp = arg;
-
-	do {
-		unw_get_ip(info, &ip);
-		if (ip == 0)
-			break;
-		if (ip == lp->ip) {
-			unw_get_bsp(info, (unsigned long*)&lp->bsp);
-			unw_get_cfm(info, (unsigned long*)&lp->cfm);
-			return;
-		}
-	} while (unw_unwind(info) >= 0);
-	lp->bsp = NULL;
-	lp->cfm = 0;
-	return;
-}
-
 unsigned long arch_deref_entry_point(void *entry)
 {
 	return ((struct fnptr *)entry)->ip;
diff --git a/arch/ia64/kernel/machine_kexec.c b/arch/ia64/kernel/machine_kexec.c
index 3b1dd5496d08..efc9b568401c 100644
--- a/arch/ia64/kernel/machine_kexec.c
+++ b/arch/ia64/kernel/machine_kexec.c
@@ -127,7 +127,6 @@ static void ia64_machine_kexec(struct unw_frame_info *info, void *arg)
 	ia64_srlz_d();
 	while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR)
 		ia64_eoi();
-	platform_kernel_launch_event();
 	rnk = (relocate_new_kernel_t)&code_addr;
 	(*rnk)(image->head, image->start, ia64_boot_param,
 		     GRANULEROUNDDOWN((unsigned long) pal_addr));
diff --git a/arch/ia64/kernel/machvec.c b/arch/ia64/kernel/machvec.c
deleted file mode 100644
index ebd82535f51b..000000000000
--- a/arch/ia64/kernel/machvec.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/dma-mapping.h>
-#include <asm/machvec.h>
-
-#ifdef CONFIG_IA64_GENERIC
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-
-#include <asm/page.h>
-
-struct ia64_machine_vector ia64_mv = {
-	.mmiowb	= ___ia64_mmiowb
-};
-EXPORT_SYMBOL(ia64_mv);
-
-static struct ia64_machine_vector * __init
-lookup_machvec (const char *name)
-{
-	extern struct ia64_machine_vector machvec_start[];
-	extern struct ia64_machine_vector machvec_end[];
-	struct ia64_machine_vector *mv;
-
-	for (mv = machvec_start; mv < machvec_end; ++mv)
-		if (strcmp (mv->name, name) == 0)
-			return mv;
-
-	return 0;
-}
-
-void __init
-machvec_init (const char *name)
-{
-	struct ia64_machine_vector *mv;
-
-	if (!name)
-		name = acpi_get_sysname();
-	mv = lookup_machvec(name);
-	if (!mv)
-		panic("generic kernel failed to find machine vector for"
-		      " platform %s!", name);
-
-	ia64_mv = *mv;
-	printk(KERN_INFO "booting generic kernel on platform %s\n", name);
-}
-
-void __init
-machvec_init_from_cmdline(const char *cmdline)
-{
-	char str[64];
-	const char *start;
-	char *end;
-
-	if (! (start = strstr(cmdline, "machvec=")) )
-		return machvec_init(NULL);
-
-	strlcpy(str, start + strlen("machvec="), sizeof(str));
-	if ( (end = strchr(str, ' ')) )
-		*end = '\0';
-
-	return machvec_init(str);
-}
-
-#endif /* CONFIG_IA64_GENERIC */
-
-void
-machvec_setup (char **arg)
-{
-}
-EXPORT_SYMBOL(machvec_setup);
-
-void
-machvec_timer_interrupt (int irq, void *dev_id)
-{
-}
-EXPORT_SYMBOL(machvec_timer_interrupt);
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 79190d877fa7..bf2cb9294795 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -91,7 +91,6 @@
 #include <linux/gfp.h>
 
 #include <asm/delay.h>
-#include <asm/machvec.h>
 #include <asm/meminit.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
@@ -149,9 +148,7 @@ static ia64_mc_info_t		ia64_mc_info;
 #define CPE_HISTORY_LENGTH    5
 #define CMC_HISTORY_LENGTH    5
 
-#ifdef CONFIG_ACPI
 static struct timer_list cpe_poll_timer;
-#endif
 static struct timer_list cmc_poll_timer;
 /*
  * This variable tells whether we are currently in polling mode.
@@ -532,8 +529,6 @@ int mca_recover_range(unsigned long addr)
 }
 EXPORT_SYMBOL_GPL(mca_recover_range);
 
-#ifdef CONFIG_ACPI
-
 int cpe_vector = -1;
 int ia64_cpe_irq = -1;
 
@@ -595,9 +590,6 @@ out:
 	return IRQ_HANDLED;
 }
 
-#endif /* CONFIG_ACPI */
-
-#ifdef CONFIG_ACPI
 /*
  * ia64_mca_register_cpev
  *
@@ -625,7 +617,6 @@ ia64_mca_register_cpev (int cpev)
 	IA64_MCA_DEBUG("%s: corrected platform error "
 		       "vector %#x registered\n", __func__, cpev);
 }
-#endif /* CONFIG_ACPI */
 
 /*
  * ia64_mca_cmc_vector_setup
@@ -744,7 +735,7 @@ ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused)
 static void
 ia64_mca_wakeup(int cpu)
 {
-	platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
+	ia64_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
 }
 
 /*
@@ -1490,7 +1481,7 @@ ia64_mca_cmc_int_caller(int cmc_irq, void *arg)
 	cpuid = cpumask_next(cpuid+1, cpu_online_mask);
 
 	if (cpuid < nr_cpu_ids) {
-		platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
+		ia64_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
 	} else {
 		/* If no log record, switch out of polling mode */
 		if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
@@ -1523,7 +1514,7 @@ static void
 ia64_mca_cmc_poll (struct timer_list *unused)
 {
 	/* Trigger a CMC interrupt cascade  */
-	platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CMCP_VECTOR,
+	ia64_send_ipi(cpumask_first(cpu_online_mask), IA64_CMCP_VECTOR,
 							IA64_IPI_DM_INT, 0);
 }
 
@@ -1540,8 +1531,6 @@ ia64_mca_cmc_poll (struct timer_list *unused)
  * Outputs
  * 	handled
  */
-#ifdef CONFIG_ACPI
-
 static irqreturn_t
 ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
 {
@@ -1560,7 +1549,7 @@ ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
 	cpuid = cpumask_next(cpuid+1, cpu_online_mask);
 
 	if (cpuid < NR_CPUS) {
-		platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
+		ia64_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
 	} else {
 		/*
 		 * If a log was recorded, increase our polling frequency,
@@ -1600,12 +1589,10 @@ static void
 ia64_mca_cpe_poll (struct timer_list *unused)
 {
 	/* Trigger a CPE interrupt cascade  */
-	platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CPEP_VECTOR,
+	ia64_send_ipi(cpumask_first(cpu_online_mask), IA64_CPEP_VECTOR,
 							IA64_IPI_DM_INT, 0);
 }
 
-#endif /* CONFIG_ACPI */
-
 static int
 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
 {
@@ -1799,7 +1786,6 @@ static struct irqaction mca_wkup_irqaction = {
 	.name =		"mca_wkup"
 };
 
-#ifdef CONFIG_ACPI
 static struct irqaction mca_cpe_irqaction = {
 	.handler =	ia64_mca_cpe_int_handler,
 	.name =		"cpe_hndlr"
@@ -1809,7 +1795,6 @@ static struct irqaction mca_cpep_irqaction = {
 	.handler =	ia64_mca_cpe_int_caller,
 	.name =		"cpe_poll"
 };
-#endif /* CONFIG_ACPI */
 
 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
  * these stacks can never sleep, they cannot return from the kernel to user
@@ -2081,10 +2066,8 @@ void __init ia64_mca_irq_init(void)
 	/* Setup the MCA wakeup interrupt vector */
 	register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
 
-#ifdef CONFIG_ACPI
 	/* Setup the CPEI/P handler */
 	register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
-#endif
 }
 
 /*
@@ -2112,7 +2095,6 @@ ia64_mca_late_init(void)
 			  ia64_mca_cpu_online, NULL);
 	IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__);
 
-#ifdef CONFIG_ACPI
 	/* Setup the CPEI/P vector and handler */
 	cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
 	timer_setup(&cpe_poll_timer, ia64_mca_cpe_poll, 0);
@@ -2143,7 +2125,6 @@ ia64_mca_late_init(void)
 			IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__);
 		}
 	}
-#endif
 
 	return 0;
 }
diff --git a/arch/ia64/kernel/mca_drv.c b/arch/ia64/kernel/mca_drv.c
index cd7972ede1d6..4d0ab323dee8 100644
--- a/arch/ia64/kernel/mca_drv.c
+++ b/arch/ia64/kernel/mca_drv.c
@@ -26,7 +26,6 @@
 #include <linux/slab.h>
 
 #include <asm/delay.h>
-#include <asm/machvec.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include <asm/sal.h>
diff --git a/arch/ia64/kernel/module.c b/arch/ia64/kernel/module.c
index 326448f9df16..1a42ba885188 100644
--- a/arch/ia64/kernel/module.c
+++ b/arch/ia64/kernel/module.c
@@ -914,10 +914,14 @@ module_finalize (const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, struct module *mo
 void
 module_arch_cleanup (struct module *mod)
 {
-	if (mod->arch.init_unw_table)
+	if (mod->arch.init_unw_table) {
 		unw_remove_unwind_table(mod->arch.init_unw_table);
-	if (mod->arch.core_unw_table)
+		mod->arch.init_unw_table = NULL;
+	}
+	if (mod->arch.core_unw_table) {
 		unw_remove_unwind_table(mod->arch.core_unw_table);
+		mod->arch.core_unw_table = NULL;
+	}
 }
 
 void *dereference_module_function_descriptor(struct module *mod, void *ptr)
diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c
index 519d9432f407..df5c28f252e3 100644
--- a/arch/ia64/kernel/msi_ia64.c
+++ b/arch/ia64/kernel/msi_ia64.c
@@ -43,7 +43,7 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata,
 }
 #endif /* CONFIG_SMP */
 
-int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
+int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
 {
 	struct msi_msg	msg;
 	unsigned long	dest_phys_id;
@@ -77,7 +77,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
 	return 0;
 }
 
-void ia64_teardown_msi_irq(unsigned int irq)
+void arch_teardown_msi_irq(unsigned int irq)
 {
 	destroy_irq(irq);
 }
@@ -111,23 +111,6 @@ static struct irq_chip ia64_msi_chip = {
 	.irq_retrigger		= ia64_msi_retrigger_irq,
 };
 
-
-int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
-{
-	if (platform_setup_msi_irq)
-		return platform_setup_msi_irq(pdev, desc);
-
-	return ia64_setup_msi_irq(pdev, desc);
-}
-
-void arch_teardown_msi_irq(unsigned int irq)
-{
-	if (platform_teardown_msi_irq)
-		return platform_teardown_msi_irq(irq);
-
-	return ia64_teardown_msi_irq(irq);
-}
-
 #ifdef CONFIG_INTEL_IOMMU
 #ifdef CONFIG_SMP
 static int dmar_msi_set_affinity(struct irq_data *data,
diff --git a/arch/ia64/kernel/pci-dma.c b/arch/ia64/kernel/pci-dma.c
index f5d49cd3fbb0..c90221733c6b 100644
--- a/arch/ia64/kernel/pci-dma.c
+++ b/arch/ia64/kernel/pci-dma.c
@@ -10,7 +10,6 @@
 #include <linux/module.h>
 #include <linux/dmar.h>
 #include <asm/iommu.h>
-#include <asm/machvec.h>
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <asm/page.h>
@@ -32,24 +31,3 @@ static int __init pci_iommu_init(void)
 
 /* Must execute after PCI subsystem */
 fs_initcall(pci_iommu_init);
-
-void __init pci_iommu_alloc(void)
-{
-	/*
-	 * The order of these functions is important for
-	 * fall-back/fail-over reasons
-	 */
-	detect_intel_iommu();
-
-#ifdef CONFIG_SWIOTLB
-	if (!iommu_detected) {
-#ifdef CONFIG_IA64_GENERIC
-		printk(KERN_INFO "PCI-DMA: Re-initialize machine vector.\n");
-		machvec_init("dig");
-		swiotlb_dma_init();
-#else
-		panic("Unable to find Intel IOMMU");
-#endif /* CONFIG_IA64_GENERIC */
-	}
-#endif /* CONFIG_SWIOTLB */
-}
diff --git a/arch/ia64/kernel/sal.c b/arch/ia64/kernel/sal.c
index 9b2331ac10ce..c455ece977ad 100644
--- a/arch/ia64/kernel/sal.c
+++ b/arch/ia64/kernel/sal.c
@@ -110,13 +110,6 @@ check_versions (struct ia64_sal_systab *systab)
 		sal_revision = SAL_VERSION_CODE(2, 8);
 		sal_version = SAL_VERSION_CODE(0, 0);
 	}
-
-	if (ia64_platform_is("sn2") && (sal_revision == SAL_VERSION_CODE(2, 9)))
-		/*
-		 * SGI Altix has hard-coded version 2.9 in their prom
-		 * but they actually implement 3.2, so let's fix it here.
-		 */
-		sal_revision = SAL_VERSION_CODE(3, 2);
 }
 
 static void __init
@@ -256,7 +249,7 @@ check_sal_cache_flush (void)
 	 * Send ourselves a timer interrupt, wait until it's reported, and see
 	 * if SAL_CACHE_FLUSH drops it.
 	 */
-	platform_send_ipi(cpu, IA64_TIMER_VECTOR, IA64_IPI_DM_INT, 0);
+	ia64_send_ipi(cpu, IA64_TIMER_VECTOR, IA64_IPI_DM_INT, 0);
 
 	while (!ia64_get_irr(IA64_TIMER_VECTOR))
 		cpu_relax();
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index c9cfa760cd57..18de565d5825 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -30,6 +30,7 @@
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/cpu.h>
+#include <linux/kdev_t.h>
 #include <linux/kernel.h>
 #include <linux/memblock.h>
 #include <linux/reboot.h>
@@ -41,6 +42,7 @@
 #include <linux/threads.h>
 #include <linux/screen_info.h>
 #include <linux/dmi.h>
+#include <linux/root_dev.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
 #include <linux/efi.h>
@@ -50,7 +52,6 @@
 #include <linux/kexec.h>
 #include <linux/crash_dump.h>
 
-#include <asm/machvec.h>
 #include <asm/mca.h>
 #include <asm/meminit.h>
 #include <asm/page.h>
@@ -63,12 +64,14 @@
 #include <asm/smp.h>
 #include <asm/tlbflush.h>
 #include <asm/unistd.h>
-#include <asm/hpsim.h>
+#include <asm/uv/uv.h>
 
 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
 # error "struct cpuinfo_ia64 too big!"
 #endif
 
+char ia64_platform_name[64];
+
 #ifdef CONFIG_SMP
 unsigned long __per_cpu_offset[NR_CPUS];
 EXPORT_SYMBOL(__per_cpu_offset);
@@ -260,11 +263,11 @@ __initcall(register_memory);
  * in kdump case. See the comment in sba_init() in sba_iommu.c.
  *
  * So, the only machvec that really supports loading the kdump kernel
- * over 4 GB is "sn2".
+ * over 4 GB is "uv".
  */
 static int __init check_crashkernel_memory(unsigned long pbase, size_t size)
 {
-	if (ia64_platform_is("sn2") || ia64_platform_is("uv"))
+	if (is_uv_system())
 		return 1;
 	else
 		return pbase < (1UL << 32);
@@ -461,23 +464,44 @@ io_port_init (void)
 static inline int __init
 early_console_setup (char *cmdline)
 {
-	int earlycons = 0;
-
-#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
-	{
-		extern int sn_serial_console_early_setup(void);
-		if (!sn_serial_console_early_setup())
-			earlycons++;
-	}
-#endif
 #ifdef CONFIG_EFI_PCDP
 	if (!efi_setup_pcdp_console(cmdline))
-		earlycons++;
+		return 0;
 #endif
-	if (!simcons_register())
-		earlycons++;
+	return -1;
+}
+
+static void __init
+screen_info_setup(void)
+{
+	unsigned int orig_x, orig_y, num_cols, num_rows, font_height;
+
+	memset(&screen_info, 0, sizeof(screen_info));
+
+	if (!ia64_boot_param->console_info.num_rows ||
+	    !ia64_boot_param->console_info.num_cols) {
+		printk(KERN_WARNING "invalid screen-info, guessing 80x25\n");
+		orig_x = 0;
+		orig_y = 0;
+		num_cols = 80;
+		num_rows = 25;
+		font_height = 16;
+	} else {
+		orig_x = ia64_boot_param->console_info.orig_x;
+		orig_y = ia64_boot_param->console_info.orig_y;
+		num_cols = ia64_boot_param->console_info.num_cols;
+		num_rows = ia64_boot_param->console_info.num_rows;
+		font_height = 400 / num_rows;
+	}
 
-	return (earlycons) ? 0 : -1;
+	screen_info.orig_x = orig_x;
+	screen_info.orig_y = orig_y;
+	screen_info.orig_video_cols  = num_cols;
+	screen_info.orig_video_lines = num_rows;
+	screen_info.orig_video_points = font_height;
+	screen_info.orig_video_mode = 3;	/* XXX fake */
+	screen_info.orig_video_isVGA = 1;	/* XXX fake */
+	screen_info.orig_video_ega_bx = 3;	/* XXX fake */
 }
 
 static inline void
@@ -536,35 +560,25 @@ setup_arch (char **cmdline_p)
 	efi_init();
 	io_port_init();
 
-#ifdef CONFIG_IA64_GENERIC
-	/* machvec needs to be parsed from the command line
-	 * before parse_early_param() is called to ensure
-	 * that ia64_mv is initialised before any command line
-	 * settings may cause console setup to occur
-	 */
-	machvec_init_from_cmdline(*cmdline_p);
-#endif
-
+	uv_probe_system_type();
 	parse_early_param();
 
 	if (early_console_setup(*cmdline_p) == 0)
 		mark_bsp_online();
 
-#ifdef CONFIG_ACPI
 	/* Initialize the ACPI boot-time table parser */
 	acpi_table_init();
 	early_acpi_boot_init();
-# ifdef CONFIG_ACPI_NUMA
+#ifdef CONFIG_ACPI_NUMA
 	acpi_numa_init();
 	acpi_numa_fixup();
-#  ifdef CONFIG_ACPI_HOTPLUG_CPU
+#ifdef CONFIG_ACPI_HOTPLUG_CPU
 	prefill_possible_map();
-#  endif
+#endif
 	per_cpu_scan_finalize((cpumask_weight(&early_cpu_possible_map) == 0 ?
 		32 : cpumask_weight(&early_cpu_possible_map)),
 		additional_cpus > 0 ? additional_cpus : 0);
-# endif
-#endif /* CONFIG_APCI_BOOT */
+#endif /* CONFIG_ACPI_NUMA */
 
 #ifdef CONFIG_SMP
 	smp_build_cpu_map();
@@ -614,10 +628,21 @@ setup_arch (char **cmdline_p)
 	if (!nomca)
 		ia64_mca_init();
 
-	platform_setup(cmdline_p);
-#ifndef CONFIG_IA64_HP_SIM
-	check_sal_cache_flush();
+	/*
+	 * Default to /dev/sda2.  This assumes that the EFI partition
+	 * is physical disk 1 partition 1 and the Linux root disk is
+	 * physical disk 1 partition 2.
+	 */
+	ROOT_DEV = Root_SDA2;		/* default to second partition on first drive */
+
+	if (is_uv_system())
+		uv_setup(cmdline_p);
+#ifdef CONFIG_SMP
+	else
+		init_smp_config();
 #endif
+
+	screen_info_setup();
 	paging_init();
 
 	clear_sched_clock_stable();
@@ -1046,7 +1071,6 @@ cpu_init (void)
 		ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8);
 		max_num_phys_stacked = num_phys_stacked;
 	}
-	platform_cpu_init();
 }
 
 void __init
diff --git a/arch/ia64/kernel/signal.c b/arch/ia64/kernel/signal.c
index e5044aed9452..d07ed65c9c6e 100644
--- a/arch/ia64/kernel/signal.c
+++ b/arch/ia64/kernel/signal.c
@@ -363,19 +363,19 @@ ia64_do_signal (struct sigscratch *scr, long in_syscall)
 
 		if (unlikely(restart)) {
 			switch (errno) {
-			      case ERESTART_RESTARTBLOCK:
-			      case ERESTARTNOHAND:
+			case ERESTART_RESTARTBLOCK:
+			case ERESTARTNOHAND:
 				scr->pt.r8 = EINTR;
 				/* note: scr->pt.r10 is already -1 */
 				break;
-
-			      case ERESTARTSYS:
+			case ERESTARTSYS:
 				if ((ksig.ka.sa.sa_flags & SA_RESTART) == 0) {
 					scr->pt.r8 = EINTR;
 					/* note: scr->pt.r10 is already -1 */
 					break;
 				}
-			      case ERESTARTNOINTR:
+				/*FALLTHRU*/
+			case ERESTARTNOINTR:
 				ia64_decrement_ip(&scr->pt);
 				restart = 0; /* don't restart twice if handle_signal() fails... */
 			}
diff --git a/arch/ia64/kernel/smp.c b/arch/ia64/kernel/smp.c
index 133b63355814..de35c54f033d 100644
--- a/arch/ia64/kernel/smp.c
+++ b/arch/ia64/kernel/smp.c
@@ -36,7 +36,6 @@
 #include <linux/atomic.h>
 #include <asm/current.h>
 #include <asm/delay.h>
-#include <asm/machvec.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/page.h>
@@ -146,7 +145,7 @@ static inline void
 send_IPI_single (int dest_cpu, int op)
 {
 	set_bit(op, &per_cpu(ipi_operation, dest_cpu));
-	platform_send_ipi(dest_cpu, IA64_IPI_VECTOR, IA64_IPI_DM_INT, 0);
+	ia64_send_ipi(dest_cpu, IA64_IPI_VECTOR, IA64_IPI_DM_INT, 0);
 }
 
 /*
@@ -213,7 +212,7 @@ kdump_smp_send_init(void)
 	for_each_online_cpu(cpu) {
 		if (cpu != self_cpu) {
 			if(kdump_status[cpu] == 0)
-				platform_send_ipi(cpu, 0, IA64_IPI_DM_INIT, 0);
+				ia64_send_ipi(cpu, 0, IA64_IPI_DM_INIT, 0);
 		}
 	}
 }
@@ -224,7 +223,7 @@ kdump_smp_send_init(void)
 void
 smp_send_reschedule (int cpu)
 {
-	platform_send_ipi(cpu, IA64_IPI_RESCHEDULE, IA64_IPI_DM_INT, 0);
+	ia64_send_ipi(cpu, IA64_IPI_RESCHEDULE, IA64_IPI_DM_INT, 0);
 }
 EXPORT_SYMBOL_GPL(smp_send_reschedule);
 
@@ -234,7 +233,7 @@ EXPORT_SYMBOL_GPL(smp_send_reschedule);
 static void
 smp_send_local_flush_tlb (int cpu)
 {
-	platform_send_ipi(cpu, IA64_IPI_LOCAL_TLB_FLUSH, IA64_IPI_DM_INT, 0);
+	ia64_send_ipi(cpu, IA64_IPI_LOCAL_TLB_FLUSH, IA64_IPI_DM_INT, 0);
 }
 
 void
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index d0474a0c67db..6501d9a9a21b 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -47,7 +47,6 @@
 #include <asm/delay.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/machvec.h>
 #include <asm/mca.h>
 #include <asm/page.h>
 #include <asm/pgalloc.h>
@@ -57,7 +56,6 @@
 #include <asm/sal.h>
 #include <asm/tlbflush.h>
 #include <asm/unistd.h>
-#include <asm/sn/arch.h>
 
 #define SMP_DEBUG 0
 
@@ -468,7 +466,7 @@ do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
 	Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
 
 	set_brendez_area(cpu);
-	platform_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
+	ia64_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
 
 	/*
 	 * Wait 10s total for the AP to start
@@ -658,11 +656,6 @@ int __cpu_disable(void)
 		return (-EBUSY);
 	}
 
-	if (ia64_platform_is("sn2")) {
-		if (!sn_cpu_disable_allowed(cpu))
-			return -EBUSY;
-	}
-
 	set_cpu_online(cpu, false);
 
 	if (migrate_platform_irqs(cpu)) {
diff --git a/arch/ia64/kernel/sys_ia64.c b/arch/ia64/kernel/sys_ia64.c
index 9ebe1d633abc..e14db25146c2 100644
--- a/arch/ia64/kernel/sys_ia64.c
+++ b/arch/ia64/kernel/sys_ia64.c
@@ -166,21 +166,3 @@ ia64_mremap (unsigned long addr, unsigned long old_len, unsigned long new_len, u
 		force_successful_syscall_return();
 	return addr;
 }
-
-#ifndef CONFIG_PCI
-
-asmlinkage long
-sys_pciconfig_read (unsigned long bus, unsigned long dfn, unsigned long off, unsigned long len,
-		    void *buf)
-{
-	return -ENOSYS;
-}
-
-asmlinkage long
-sys_pciconfig_write (unsigned long bus, unsigned long dfn, unsigned long off, unsigned long len,
-		     void *buf)
-{
-	return -ENOSYS;
-}
-
-#endif /* CONFIG_PCI */
diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c
index 4ecd81b0e8ec..1e95d32c8877 100644
--- a/arch/ia64/kernel/time.c
+++ b/arch/ia64/kernel/time.c
@@ -25,7 +25,6 @@
 #include <linux/platform_device.h>
 #include <linux/sched/cputime.h>
 
-#include <asm/machvec.h>
 #include <asm/delay.h>
 #include <asm/hw_irq.h>
 #include <asm/ptrace.h>
@@ -167,8 +166,6 @@ timer_interrupt (int irq, void *dev_id)
 		return IRQ_HANDLED;
 	}
 
-	platform_timer_interrupt(irq, dev_id);
-
 	new_itm = local_cpu_data->itm_next;
 
 	if (!time_after(ia64_get_itc(), new_itm))
diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c
index e311ee13e61d..09fc385c2acd 100644
--- a/arch/ia64/kernel/topology.c
+++ b/arch/ia64/kernel/topology.c
@@ -42,7 +42,6 @@ EXPORT_SYMBOL_GPL(arch_fix_phys_package_id);
 #ifdef CONFIG_HOTPLUG_CPU
 int __ref arch_register_cpu(int num)
 {
-#ifdef CONFIG_ACPI
 	/*
 	 * If CPEI can be re-targeted or if this is not
 	 * CPEI target, then it is hotpluggable
@@ -50,7 +49,6 @@ int __ref arch_register_cpu(int num)
 	if (can_cpei_retarget() || !is_cpu_cpei_target(num))
 		sysfs_cpus[num].cpu.hotpluggable = 1;
 	map_cpu_to_node(num, node_cpuid[num].nid);
-#endif
 	return register_cpu(&sysfs_cpus[num].cpu, num);
 }
 EXPORT_SYMBOL(arch_register_cpu);
@@ -58,9 +56,7 @@ EXPORT_SYMBOL(arch_register_cpu);
 void __ref arch_unregister_cpu(int num)
 {
 	unregister_cpu(&sysfs_cpus[num].cpu);
-#ifdef CONFIG_ACPI
 	unmap_cpu_from_node(num, cpu_to_node(num));
-#endif
 }
 EXPORT_SYMBOL(arch_unregister_cpu);
 #else
diff --git a/arch/ia64/kernel/unaligned.c b/arch/ia64/kernel/unaligned.c
index eb7d5df59fa3..2d4e65ba5c3e 100644
--- a/arch/ia64/kernel/unaligned.c
+++ b/arch/ia64/kernel/unaligned.c
@@ -1431,7 +1431,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs)
 		if (u.insn.x)
 			/* oops, really a semaphore op (cmpxchg, etc) */
 			goto failure;
-		/* no break */
+		/*FALLTHRU*/
 	      case LDS_IMM_OP:
 	      case LDSA_IMM_OP:
 	      case LDFS_OP:
@@ -1459,7 +1459,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs)
 		if (u.insn.x)
 			/* oops, really a semaphore op (cmpxchg, etc) */
 			goto failure;
-		/* no break */
+		/*FALLTHRU*/
 	      case LD_IMM_OP:
 	      case LDA_IMM_OP:
 	      case LDBIAS_IMM_OP:
@@ -1475,7 +1475,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs)
 		if (u.insn.x)
 			/* oops, really a semaphore op (cmpxchg, etc) */
 			goto failure;
-		/* no break */
+		/*FALLTHRU*/
 	      case ST_IMM_OP:
 	      case STREL_IMM_OP:
 		ret = emulate_store_int(ifa, u.insn, regs);
diff --git a/arch/ia64/kernel/uncached.c b/arch/ia64/kernel/uncached.c
index 16c6d377c502..3776ef225125 100644
--- a/arch/ia64/kernel/uncached.c
+++ b/arch/ia64/kernel/uncached.c
@@ -24,7 +24,6 @@
 #include <asm/pgtable.h>
 #include <linux/atomic.h>
 #include <asm/tlbflush.h>
-#include <asm/sn/arch.h>
 
 
 extern void __init efi_memmap_walk_uc(efi_freemem_callback_t, void *);
@@ -129,10 +128,7 @@ static int uncached_add_chunk(struct uncached_pool *uc_pool, int nid)
 
 	preempt_disable();
 
-	if (ia64_platform_is("sn2"))
-		sn_flush_all_caches(uc_addr, IA64_GRANULE_SIZE);
-	else
-		flush_icache_range(uc_addr, uc_addr + IA64_GRANULE_SIZE);
+	flush_icache_range(uc_addr, uc_addr + IA64_GRANULE_SIZE);
 
 	/* flush the just introduced uncached translation from the TLB */
 	local_flush_tlb_all();
diff --git a/arch/ia64/kernel/vmlinux.lds.S b/arch/ia64/kernel/vmlinux.lds.S
index 0da58cf8e213..d9d4e21107cd 100644
--- a/arch/ia64/kernel/vmlinux.lds.S
+++ b/arch/ia64/kernel/vmlinux.lds.S
@@ -141,16 +141,6 @@ SECTIONS {
 		__end___mckinley_e9_bundles = .;
 	}
 
-#if defined(CONFIG_IA64_GENERIC)
-	/* Machine Vector */
-	. = ALIGN(16);
-	.machvec : AT(ADDR(.machvec) - LOAD_OFFSET) {
-		machvec_start = .;
-		*(.machvec)
-		machvec_end = .;
-	}
-#endif
-
 #ifdef	CONFIG_SMP
 	. = ALIGN(PERCPU_PAGE_SIZE);
 	__cpu0_per_cpu = .;
diff --git a/arch/ia64/lib/io.c b/arch/ia64/lib/io.c
index d107eaf3790d..c3e02462ed16 100644
--- a/arch/ia64/lib/io.c
+++ b/arch/ia64/lib/io.c
@@ -49,117 +49,3 @@ void memset_io(volatile void __iomem *dst, int c, long count)
 	}
 }
 EXPORT_SYMBOL(memset_io);
-
-#ifdef CONFIG_IA64_GENERIC
-
-#undef __ia64_inb
-#undef __ia64_inw
-#undef __ia64_inl
-#undef __ia64_outb
-#undef __ia64_outw
-#undef __ia64_outl
-#undef __ia64_readb
-#undef __ia64_readw
-#undef __ia64_readl
-#undef __ia64_readq
-#undef __ia64_readb_relaxed
-#undef __ia64_readw_relaxed
-#undef __ia64_readl_relaxed
-#undef __ia64_readq_relaxed
-#undef __ia64_writeb
-#undef __ia64_writew
-#undef __ia64_writel
-#undef __ia64_writeq
-#undef __ia64_mmiowb
-
-unsigned int
-__ia64_inb (unsigned long port)
-{
-	return ___ia64_inb(port);
-}
-
-unsigned int
-__ia64_inw (unsigned long port)
-{
-	return ___ia64_inw(port);
-}
-
-unsigned int
-__ia64_inl (unsigned long port)
-{
-	return ___ia64_inl(port);
-}
-
-void
-__ia64_outb (unsigned char val, unsigned long port)
-{
-	___ia64_outb(val, port);
-}
-
-void
-__ia64_outw (unsigned short val, unsigned long port)
-{
-	___ia64_outw(val, port);
-}
-
-void
-__ia64_outl (unsigned int val, unsigned long port)
-{
-	___ia64_outl(val, port);
-}
-
-unsigned char
-__ia64_readb (void __iomem *addr)
-{
-	return ___ia64_readb (addr);
-}
-
-unsigned short
-__ia64_readw (void __iomem *addr)
-{
-	return ___ia64_readw (addr);
-}
-
-unsigned int
-__ia64_readl (void __iomem *addr)
-{
-	return ___ia64_readl (addr);
-}
-
-unsigned long
-__ia64_readq (void __iomem *addr)
-{
-	return ___ia64_readq (addr);
-}
-
-unsigned char
-__ia64_readb_relaxed (void __iomem *addr)
-{
-	return ___ia64_readb (addr);
-}
-
-unsigned short
-__ia64_readw_relaxed (void __iomem *addr)
-{
-	return ___ia64_readw (addr);
-}
-
-unsigned int
-__ia64_readl_relaxed (void __iomem *addr)
-{
-	return ___ia64_readl (addr);
-}
-
-unsigned long
-__ia64_readq_relaxed (void __iomem *addr)
-{
-	return ___ia64_readq (addr);
-}
-
-void
-__ia64_mmiowb(void)
-{
-	___ia64_mmiowb();
-}
-
-#endif /* CONFIG_IA64_GENERIC */
diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
index 05490dd073e6..921f3efe3538 100644
--- a/arch/ia64/mm/discontig.c
+++ b/arch/ia64/mm/discontig.c
@@ -396,8 +396,7 @@ static void __meminit scatter_node_data(void)
  *
  * Each node's per-node area has a copy of the global pg_data_t list, so
  * we copy that to each node here, as well as setting the per-cpu pointer
- * to the local node data structure.  The active_cpus field of the per-node
- * structure gets setup by the platform_cpu_init() function later.
+ * to the local node data structure.
  */
 static void __init initialize_pernode_data(void)
 {
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index aae75fd7b810..678b98a09c85 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -9,6 +9,7 @@
 #include <linux/init.h>
 
 #include <linux/dma-noncoherent.h>
+#include <linux/dmar.h>
 #include <linux/efi.h>
 #include <linux/elf.h>
 #include <linux/memblock.h>
@@ -23,10 +24,10 @@
 #include <linux/proc_fs.h>
 #include <linux/bitops.h>
 #include <linux/kexec.h>
+#include <linux/swiotlb.h>
 
 #include <asm/dma.h>
 #include <asm/io.h>
-#include <asm/machvec.h>
 #include <asm/numa.h>
 #include <asm/patch.h>
 #include <asm/pgalloc.h>
@@ -67,7 +68,6 @@ __ia64_sync_icache_dcache (pte_t pte)
 	set_bit(PG_arch_1, &page->flags);	/* mark page as clean */
 }
 
-#ifdef CONFIG_SWIOTLB
 /*
  * Since DMA is i-cache coherent, any (complete) pages that were written via
  * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to
@@ -82,7 +82,6 @@ void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
 		set_bit(PG_arch_1, &pfn_to_page(pfn)->flags);
 	} while (++pfn <= PHYS_PFN(paddr + size - 1));
 }
-#endif
 
 inline void
 ia64_set_rbs_bot (void)
@@ -632,13 +631,17 @@ mem_init (void)
 	BUG_ON(PTRS_PER_PMD * sizeof(pmd_t) != PAGE_SIZE);
 	BUG_ON(PTRS_PER_PTE * sizeof(pte_t) != PAGE_SIZE);
 
-#ifdef CONFIG_PCI
 	/*
-	 * This needs to be called _after_ the command line has been parsed but _before_
-	 * any drivers that may need the PCI DMA interface are initialized or bootmem has
-	 * been freed.
+	 * This needs to be called _after_ the command line has been parsed but
+	 * _before_ any drivers that may need the PCI DMA interface are
+	 * initialized or bootmem has been freed.
 	 */
-	platform_dma_init();
+#ifdef CONFIG_INTEL_IOMMU
+	detect_intel_iommu();
+	if (!iommu_detected)
+#endif
+#ifdef CONFIG_SWIOTLB
+		swiotlb_init(1);
 #endif
 
 #ifdef CONFIG_FLATMEM
diff --git a/arch/ia64/mm/tlb.c b/arch/ia64/mm/tlb.c
index 0714df1b7854..72cc568bc841 100644
--- a/arch/ia64/mm/tlb.c
+++ b/arch/ia64/mm/tlb.c
@@ -245,7 +245,8 @@ resetsema:
 	spinaphore_init(&ptcg_sem, max_purges);
 }
 
-void
+#ifdef CONFIG_SMP
+static void
 ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
 		       unsigned long end, unsigned long nbits)
 {
@@ -282,6 +283,7 @@ ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
                 activate_context(active_mm);
         }
 }
+#endif /* CONFIG_SMP */
 
 void
 local_flush_tlb_all (void)
@@ -332,7 +334,7 @@ __flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
 	preempt_disable();
 #ifdef CONFIG_SMP
 	if (mm != current->active_mm || cpumask_weight(mm_cpumask(mm)) != 1) {
-		platform_global_tlb_purge(mm, start, end, nbits);
+		ia64_global_tlb_purge(mm, start, end, nbits);
 		preempt_enable();
 		return;
 	}
diff --git a/arch/ia64/pci/fixup.c b/arch/ia64/pci/fixup.c
index e1fa45b2148c..acb55a41260d 100644
--- a/arch/ia64/pci/fixup.c
+++ b/arch/ia64/pci/fixup.c
@@ -8,8 +8,7 @@
 #include <linux/init.h>
 #include <linux/vgaarb.h>
 #include <linux/screen_info.h>
-
-#include <asm/machvec.h>
+#include <asm/uv/uv.h>
 
 /*
  * Fixup to mark boot BIOS video selected by BIOS before it changes
@@ -35,8 +34,7 @@ static void pci_fixup_video(struct pci_dev *pdev)
 	u16 config;
 	struct resource *res;
 
-	if ((strcmp(ia64_platform_name, "dig") != 0)
-	    && (strcmp(ia64_platform_name, "hpzx1")  != 0))
+	if (is_uv_system())
 		return;
 	/* Maybe, this machine supports legacy memory map. */
 
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 165e561dc81a..211757e34198 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -24,7 +24,6 @@
 #include <linux/memblock.h>
 #include <linux/export.h>
 
-#include <asm/machvec.h>
 #include <asm/page.h>
 #include <asm/io.h>
 #include <asm/sal.h>
@@ -372,7 +371,6 @@ void pcibios_fixup_bus(struct pci_bus *b)
 	}
 	list_for_each_entry(dev, &b->devices, bus_list)
 		pcibios_fixup_device_resources(dev);
-	platform_pci_fixup_bus(b);
 }
 
 void pcibios_add_bus(struct pci_bus *bus)
@@ -413,7 +411,7 @@ pcibios_disable_device (struct pci_dev *dev)
 }
 
 /**
- * ia64_pci_get_legacy_mem - generic legacy mem routine
+ * pci_get_legacy_mem - generic legacy mem routine
  * @bus: bus to get legacy memory base address for
  *
  * Find the base of legacy memory for @bus.  This is typically the first
@@ -424,7 +422,7 @@ pcibios_disable_device (struct pci_dev *dev)
  * This is the ia64 generic version of this routine.  Other platforms
  * are free to override it with a machine vector.
  */
-char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
+char *pci_get_legacy_mem(struct pci_bus *bus)
 {
 	return (char *)__IA64_UNCACHED_OFFSET;
 }
@@ -473,7 +471,7 @@ pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
 }
 
 /**
- * ia64_pci_legacy_read - read from legacy I/O space
+ * pci_legacy_read - read from legacy I/O space
  * @bus: bus to read
  * @port: legacy port value
  * @val: caller allocated storage for returned value
@@ -485,7 +483,7 @@ pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
  * overridden by the platform.  This is necessary on platforms that don't
  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
  */
-int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
+int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 {
 	int ret = size;
 
@@ -508,7 +506,7 @@ int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 }
 
 /**
- * ia64_pci_legacy_write - perform a legacy I/O write
+ * pci_legacy_write - perform a legacy I/O write
  * @bus: bus pointer
  * @port: port to write
  * @val: value to write
@@ -516,7 +514,7 @@ int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
  *
  * Simply writes @size bytes of @val to @port.
  */
-int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
+int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 {
 	int ret = size;
 
diff --git a/arch/ia64/sn/Makefile b/arch/ia64/sn/Makefile
deleted file mode 100644
index 79a7df02e812..000000000000
--- a/arch/ia64/sn/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# arch/ia64/sn/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2004 Silicon Graphics, Inc.  All Rights Reserved.
-#
-# Makefile for the sn ia64 subplatform
-#
-
-obj-y += kernel/ pci/
diff --git a/arch/ia64/sn/include/ioerror.h b/arch/ia64/sn/include/ioerror.h
deleted file mode 100644
index e68f2b0789a7..000000000000
--- a/arch/ia64/sn/include/ioerror.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_IOERROR_H
-#define _ASM_IA64_SN_IOERROR_H
-
-/*
- * IO error structure.
- *
- * This structure would expand to hold the information retrieved from
- * all IO related error registers.
- *
- * This structure is defined to hold all system specific
- * information related to a single error.
- *
- * This serves a couple of purpose.
- *      - Error handling often involves translating one form of address to other
- *        form. So, instead of having different data structures at each level,
- *        we have a single structure, and the appropriate fields get filled in
- *        at each layer.
- *      - This provides a way to dump all error related information in any layer
- *        of erorr handling (debugging aid).
- *
- * A second possibility is to allow each layer to define its own error
- * data structure, and fill in the proper fields. This has the advantage
- * of isolating the layers.
- * A big concern is the potential stack usage (and overflow), if each layer
- * defines these structures on stack (assuming we don't want to do kmalloc.
- *
- * Any layer wishing to pass extra information to a layer next to it in
- * error handling hierarchy, can do so as a separate parameter.
- */
-
-typedef struct io_error_s {
-    /* Bit fields indicating which structure fields are valid */
-    union {
-	struct {
-	    unsigned                ievb_errortype:1;
-	    unsigned                ievb_widgetnum:1;
-	    unsigned                ievb_widgetdev:1;
-	    unsigned                ievb_srccpu:1;
-	    unsigned                ievb_srcnode:1;
-	    unsigned                ievb_errnode:1;
-	    unsigned                ievb_sysioaddr:1;
-	    unsigned                ievb_xtalkaddr:1;
-	    unsigned                ievb_busspace:1;
-	    unsigned                ievb_busaddr:1;
-	    unsigned                ievb_vaddr:1;
-	    unsigned                ievb_memaddr:1;
-	    unsigned		    ievb_epc:1;
-	    unsigned		    ievb_ef:1;
-	    unsigned		    ievb_tnum:1;
-	} iev_b;
-	unsigned                iev_a;
-    } ie_v;
-
-    short                   ie_errortype;	/* error type: extra info about error */
-    short                   ie_widgetnum;	/* Widget number that's in error */
-    short                   ie_widgetdev;	/* Device within widget in error */
-    cpuid_t                 ie_srccpu;	/* CPU on srcnode generating error */
-    cnodeid_t               ie_srcnode;		/* Node which caused the error   */
-    cnodeid_t               ie_errnode;		/* Node where error was noticed  */
-    iopaddr_t               ie_sysioaddr;	/* Sys specific IO address       */
-    iopaddr_t               ie_xtalkaddr;	/* Xtalk (48bit) addr of Error   */
-    iopaddr_t               ie_busspace;	/* Bus specific address space    */
-    iopaddr_t               ie_busaddr;		/* Bus specific address          */
-    caddr_t                 ie_vaddr;	/* Virtual address of error      */
-    iopaddr_t               ie_memaddr;		/* Physical memory address       */
-    caddr_t		    ie_epc;		/* pc when error reported	 */
-    caddr_t		    ie_ef;		/* eframe when error reported	 */
-    short		    ie_tnum;		/* Xtalk TNUM field */
-} ioerror_t;
-
-#define	IOERROR_INIT(e)		do { (e)->ie_v.iev_a = 0; } while (0)
-#define	IOERROR_SETVALUE(e,f,v)	do { (e)->ie_ ## f = (v); (e)->ie_v.iev_b.ievb_ ## f = 1; } while (0)
-
-#endif /* _ASM_IA64_SN_IOERROR_H */
diff --git a/arch/ia64/sn/include/tio.h b/arch/ia64/sn/include/tio.h
deleted file mode 100644
index 6b2e7b75eb19..000000000000
--- a/arch/ia64/sn/include/tio.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_TIO_H
-#define _ASM_IA64_SN_TIO_H
-
-#define	TIO_MMR_ADDR_MOD
-
-#define TIO_NODE_ID     TIO_MMR_ADDR_MOD(0x0000000090060e80)
-
-#define TIO_ITTE_BASE   0xb0008800        /* base of translation table entries */
-#define TIO_ITTE(bigwin)        (TIO_ITTE_BASE + 8*(bigwin))
-
-#define TIO_ITTE_OFFSET_BITS    8       /* size of offset field */
-#define TIO_ITTE_OFFSET_MASK    ((1<<TIO_ITTE_OFFSET_BITS)-1)
-#define TIO_ITTE_OFFSET_SHIFT   0
-
-#define TIO_ITTE_WIDGET_BITS    2       /* size of widget field */
-#define TIO_ITTE_WIDGET_MASK    ((1<<TIO_ITTE_WIDGET_BITS)-1)
-#define TIO_ITTE_WIDGET_SHIFT   12
-#define TIO_ITTE_VALID_MASK	0x1
-#define TIO_ITTE_VALID_SHIFT	16
-
-#define TIO_ITTE_WIDGET(itte) \
-	(((itte) >> TIO_ITTE_WIDGET_SHIFT) & TIO_ITTE_WIDGET_MASK)
-#define TIO_ITTE_VALID(itte) \
-	(((itte) >> TIO_ITTE_VALID_SHIFT) & TIO_ITTE_VALID_MASK)
-
-#define TIO_ITTE_PUT(nasid, bigwin, widget, addr, valid) \
-        REMOTE_HUB_S((nasid), TIO_ITTE(bigwin), \
-                (((((addr) >> TIO_BWIN_SIZE_BITS) & \
-                   TIO_ITTE_OFFSET_MASK) << TIO_ITTE_OFFSET_SHIFT) | \
-                (((widget) & TIO_ITTE_WIDGET_MASK) << TIO_ITTE_WIDGET_SHIFT)) | \
-		(( (valid) & TIO_ITTE_VALID_MASK) << TIO_ITTE_VALID_SHIFT))
-
-#endif /*  _ASM_IA64_SN_TIO_H */
diff --git a/arch/ia64/sn/include/xtalk/hubdev.h b/arch/ia64/sn/include/xtalk/hubdev.h
deleted file mode 100644
index 8182583c762c..000000000000
--- a/arch/ia64/sn/include/xtalk/hubdev.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H
-#define _ASM_IA64_SN_XTALK_HUBDEV_H
-
-#include "xtalk/xwidgetdev.h"
-
-#define HUB_WIDGET_ID_MAX 0xf
-#define DEV_PER_WIDGET (2*2*8)
-#define IIO_ITTE_WIDGET_BITS    4       /* size of widget field */
-#define IIO_ITTE_WIDGET_MASK    ((1<<IIO_ITTE_WIDGET_BITS)-1)
-#define IIO_ITTE_WIDGET_SHIFT   8
-
-#define IIO_ITTE_WIDGET(itte)	\
-	(((itte) >> IIO_ITTE_WIDGET_SHIFT) & IIO_ITTE_WIDGET_MASK)
-
-/*
- * Use the top big window as a surrogate for the first small window
- */
-#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
-#define IIO_NUM_ITTES   7
-#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
-
-/* This struct is shared between the PROM and the kernel.
- * Changes to this struct will require corresponding changes to the kernel.
- */
-struct sn_flush_device_common {
-	int sfdl_bus;
-	int sfdl_slot;
-	int sfdl_pin;
-	struct common_bar_list {
-		unsigned long start;
-		unsigned long end;
-	} sfdl_bar_list[6];
-	unsigned long sfdl_force_int_addr;
-	unsigned long sfdl_flush_value;
-	volatile unsigned long *sfdl_flush_addr;
-	u32 sfdl_persistent_busnum;
-	u32 sfdl_persistent_segment;
-	struct pcibus_info *sfdl_pcibus_info;
-};
-
-/* This struct is kernel only and is not used by the PROM */
-struct sn_flush_device_kernel {
-	spinlock_t sfdl_flush_lock;
-	struct sn_flush_device_common *common;
-};
-
-/* 01/16/06 This struct is the old PROM/kernel struct and needs to be included
- * for older official PROMs to function on the new kernel base.  This struct
- * will be removed when the next official PROM release occurs. */
-
-struct sn_flush_device_war {
-	struct sn_flush_device_common common;
-	u32 filler; /* older PROMs expect the default size of a spinlock_t */
-};
-
-/*
- * **widget_p - Used as an array[wid_num][device] of sn_flush_device_kernel.
- */
-struct sn_flush_nasid_entry  {
-	struct sn_flush_device_kernel **widget_p; // Used as an array of wid_num
-	u64 iio_itte[8];
-};
-
-struct hubdev_info {
-	geoid_t				hdi_geoid;
-	short				hdi_nasid;
-	short				hdi_peer_nasid;   /* Dual Porting Peer */
-
-	struct sn_flush_nasid_entry	hdi_flush_nasid_list;
-	struct xwidget_info		hdi_xwidget_info[HUB_WIDGET_ID_MAX + 1];
-
-
-	void				*hdi_nodepda;
-	void				*hdi_node_vertex;
-	u32				max_segment_number;
-	u32				max_pcibus_number;
-};
-
-extern void hubdev_init_node(nodepda_t *, cnodeid_t);
-extern void hub_error_init(struct hubdev_info *);
-extern void ice_error_init(struct hubdev_info *);
-
-
-#endif /* _ASM_IA64_SN_XTALK_HUBDEV_H */
diff --git a/arch/ia64/sn/include/xtalk/xbow.h b/arch/ia64/sn/include/xtalk/xbow.h
deleted file mode 100644
index 90f37a4133d0..000000000000
--- a/arch/ia64/sn/include/xtalk/xbow.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All Rights
- * Reserved.
- */
-#ifndef _ASM_IA64_SN_XTALK_XBOW_H
-#define _ASM_IA64_SN_XTALK_XBOW_H
-
-#define XBOW_PORT_8	0x8
-#define XBOW_PORT_C	0xc
-#define XBOW_PORT_F	0xf
-
-#define MAX_XBOW_PORTS	8	/* number of ports on xbow chip */
-#define BASE_XBOW_PORT	XBOW_PORT_8	/* Lowest external port */
-
-#define	XBOW_CREDIT	4
-
-#define MAX_XBOW_NAME 	16
-
-/* Register set for each xbow link */
-typedef volatile struct xb_linkregs_s {
-/*
- * we access these through synergy unswizzled space, so the address
- * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
- * That's why we put the register first and filler second.
- */
-	u32 link_ibf;
-	u32 filler0;	/* filler for proper alignment */
-	u32 link_control;
-	u32 filler1;
-	u32 link_status;
-	u32 filler2;
-	u32 link_arb_upper;
-	u32 filler3;
-	u32 link_arb_lower;
-	u32 filler4;
-	u32 link_status_clr;
-	u32 filler5;
-	u32 link_reset;
-	u32 filler6;
-	u32 link_aux_status;
-	u32 filler7;
-} xb_linkregs_t;
-
-typedef volatile struct xbow_s {
-	/* standard widget configuration 0x000000-0x000057 */
-	struct widget_cfg xb_widget;  /* 0x000000 */
-
-	/* helper fieldnames for accessing bridge widget */
-
-#define xb_wid_id 		xb_widget.w_id
-#define xb_wid_stat 		xb_widget.w_status
-#define xb_wid_err_upper 	xb_widget.w_err_upper_addr
-#define xb_wid_err_lower 	xb_widget.w_err_lower_addr
-#define xb_wid_control		xb_widget.w_control
-#define xb_wid_req_timeout 	xb_widget.w_req_timeout
-#define xb_wid_int_upper 	xb_widget.w_intdest_upper_addr
-#define xb_wid_int_lower 	xb_widget.w_intdest_lower_addr
-#define xb_wid_err_cmdword 	xb_widget.w_err_cmd_word
-#define xb_wid_llp 		xb_widget.w_llp_cfg
-#define xb_wid_stat_clr 	xb_widget.w_tflush
-
-/*
- * we access these through synergy unswizzled space, so the address
- * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
- * That's why we put the register first and filler second.
- */
-	/* xbow-specific widget configuration    0x000058-0x0000FF */
-	u32 xb_wid_arb_reload; /* 0x00005C */
-	u32 _pad_000058;
-	u32 xb_perf_ctr_a;	/* 0x000064 */
-	u32 _pad_000060;
-	u32 xb_perf_ctr_b;	/* 0x00006c */
-	u32 _pad_000068;
-	u32 xb_nic;		/* 0x000074 */
-	u32 _pad_000070;
-
-	/* Xbridge only */
-	u32 xb_w0_rst_fnc;	/* 0x00007C */
-	u32 _pad_000078;
-	u32 xb_l8_rst_fnc;	/* 0x000084 */
-	u32 _pad_000080;
-	u32 xb_l9_rst_fnc;	/* 0x00008c */
-	u32 _pad_000088;
-	u32 xb_la_rst_fnc;	/* 0x000094 */
-	u32 _pad_000090;
-	u32 xb_lb_rst_fnc;	/* 0x00009c */
-	u32 _pad_000098;
-	u32 xb_lc_rst_fnc;	/* 0x0000a4 */
-	u32 _pad_0000a0;
-	u32 xb_ld_rst_fnc;	/* 0x0000ac */
-	u32 _pad_0000a8;
-	u32 xb_le_rst_fnc;	/* 0x0000b4 */
-	u32 _pad_0000b0;
-	u32 xb_lf_rst_fnc;	/* 0x0000bc */
-	u32 _pad_0000b8;
-	u32 xb_lock;		/* 0x0000c4 */
-	u32 _pad_0000c0;
-	u32 xb_lock_clr;	/* 0x0000cc */
-	u32 _pad_0000c8;
-	/* end of Xbridge only */
-	u32 _pad_0000d0[12];
-
-	/* Link Specific Registers, port 8..15   0x000100-0x000300 */
-	xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS];
-} xbow_t;
-
-#define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
-
-#define XB_FLAGS_EXISTS		0x1	/* device exists */
-#define XB_FLAGS_MASTER		0x2
-#define XB_FLAGS_SLAVE		0x0
-#define XB_FLAGS_GBR		0x4
-#define XB_FLAGS_16BIT		0x8
-#define XB_FLAGS_8BIT		0x0
-
-/* is widget port number valid?  (based on version 7.0 of xbow spec) */
-#define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F)
-
-/* whether to use upper or lower arbitration register, given source widget id */
-#define XBOW_ARB_IS_UPPER(wid) 	((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B)
-#define XBOW_ARB_IS_LOWER(wid) 	((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F)
-
-/* offset of arbitration register, given source widget id */
-#define XBOW_ARB_OFF(wid) 	(XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
-
-#define	XBOW_WID_ID		WIDGET_ID
-#define	XBOW_WID_STAT		WIDGET_STATUS
-#define	XBOW_WID_ERR_UPPER	WIDGET_ERR_UPPER_ADDR
-#define	XBOW_WID_ERR_LOWER	WIDGET_ERR_LOWER_ADDR
-#define	XBOW_WID_CONTROL	WIDGET_CONTROL
-#define	XBOW_WID_REQ_TO		WIDGET_REQ_TIMEOUT
-#define	XBOW_WID_INT_UPPER	WIDGET_INTDEST_UPPER_ADDR
-#define	XBOW_WID_INT_LOWER	WIDGET_INTDEST_LOWER_ADDR
-#define	XBOW_WID_ERR_CMDWORD	WIDGET_ERR_CMD_WORD
-#define	XBOW_WID_LLP		WIDGET_LLP_CFG
-#define	XBOW_WID_STAT_CLR	WIDGET_TFLUSH
-#define XBOW_WID_ARB_RELOAD 	0x5c
-#define XBOW_WID_PERF_CTR_A 	0x64
-#define XBOW_WID_PERF_CTR_B 	0x6c
-#define XBOW_WID_NIC 		0x74
-
-/* Xbridge only */
-#define XBOW_W0_RST_FNC		0x00007C
-#define	XBOW_L8_RST_FNC		0x000084
-#define	XBOW_L9_RST_FNC		0x00008c
-#define	XBOW_LA_RST_FNC		0x000094
-#define	XBOW_LB_RST_FNC		0x00009c
-#define	XBOW_LC_RST_FNC		0x0000a4
-#define	XBOW_LD_RST_FNC		0x0000ac
-#define	XBOW_LE_RST_FNC		0x0000b4
-#define	XBOW_LF_RST_FNC		0x0000bc
-#define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \
-				(XBOW_W0_RST_FNC + ((x) - 7) * 8) : \
-				((x) == 0) ? XBOW_W0_RST_FNC : 0
-#define XBOW_LOCK		0x0000c4
-#define XBOW_LOCK_CLR		0x0000cc
-/* End of Xbridge only */
-
-/* used only in ide, but defined here within the reserved portion */
-/* of the widget0 address space (before 0xf4) */
-#define	XBOW_WID_UNDEF		0xe4
-
-/* xbow link register set base, legal value for x is 0x8..0xf */
-#define	XB_LINK_BASE		0x100
-#define	XB_LINK_OFFSET		0x40
-#define	XB_LINK_REG_BASE(x)	(XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET)
-
-#define	XB_LINK_IBUF_FLUSH(x)	(XB_LINK_REG_BASE(x) + 0x4)
-#define	XB_LINK_CTRL(x)		(XB_LINK_REG_BASE(x) + 0xc)
-#define	XB_LINK_STATUS(x)	(XB_LINK_REG_BASE(x) + 0x14)
-#define	XB_LINK_ARB_UPPER(x)	(XB_LINK_REG_BASE(x) + 0x1c)
-#define	XB_LINK_ARB_LOWER(x)	(XB_LINK_REG_BASE(x) + 0x24)
-#define	XB_LINK_STATUS_CLR(x)	(XB_LINK_REG_BASE(x) + 0x2c)
-#define	XB_LINK_RESET(x)	(XB_LINK_REG_BASE(x) + 0x34)
-#define	XB_LINK_AUX_STATUS(x)	(XB_LINK_REG_BASE(x) + 0x3c)
-
-/* link_control(x) */
-#define	XB_CTRL_LINKALIVE_IE		0x80000000	/* link comes alive */
-/* reserved:			0x40000000 */
-#define	XB_CTRL_PERF_CTR_MODE_MSK	0x30000000	/* perf counter mode */
-#define	XB_CTRL_IBUF_LEVEL_MSK		0x0e000000	/* input packet buffer
-							   level */
-#define	XB_CTRL_8BIT_MODE		0x01000000	/* force link into 8
-							   bit mode */
-#define XB_CTRL_BAD_LLP_PKT		0x00800000	/* force bad LLP
-							   packet */
-#define XB_CTRL_WIDGET_CR_MSK		0x007c0000	/* LLP widget credit
-							   mask */
-#define XB_CTRL_WIDGET_CR_SHFT	18			/* LLP widget credit
-							   shift */
-#define XB_CTRL_ILLEGAL_DST_IE		0x00020000	/* illegal destination
-							 */
-#define XB_CTRL_OALLOC_IBUF_IE		0x00010000	/* overallocated input
-							   buffer */
-/* reserved:			0x0000fe00 */
-#define XB_CTRL_BNDWDTH_ALLOC_IE	0x00000100	/* bandwidth alloc */
-#define XB_CTRL_RCV_CNT_OFLOW_IE	0x00000080	/* rcv retry overflow */
-#define XB_CTRL_XMT_CNT_OFLOW_IE	0x00000040	/* xmt retry overflow */
-#define XB_CTRL_XMT_MAX_RTRY_IE		0x00000020	/* max transmit retry */
-#define XB_CTRL_RCV_IE			0x00000010	/* receive */
-#define XB_CTRL_XMT_RTRY_IE		0x00000008	/* transmit retry */
-/* reserved:			0x00000004 */
-#define	XB_CTRL_MAXREQ_TOUT_IE		0x00000002	/* maximum request
-							   timeout */
-#define	XB_CTRL_SRC_TOUT_IE		0x00000001	/* source timeout */
-
-/* link_status(x) */
-#define	XB_STAT_LINKALIVE		XB_CTRL_LINKALIVE_IE
-/* reserved:			0x7ff80000 */
-#define	XB_STAT_MULTI_ERR		0x00040000	/* multi error */
-#define	XB_STAT_ILLEGAL_DST_ERR		XB_CTRL_ILLEGAL_DST_IE
-#define	XB_STAT_OALLOC_IBUF_ERR		XB_CTRL_OALLOC_IBUF_IE
-#define	XB_STAT_BNDWDTH_ALLOC_ID_MSK	0x0000ff00	/* port bitmask */
-#define	XB_STAT_RCV_CNT_OFLOW_ERR	XB_CTRL_RCV_CNT_OFLOW_IE
-#define	XB_STAT_XMT_CNT_OFLOW_ERR	XB_CTRL_XMT_CNT_OFLOW_IE
-#define	XB_STAT_XMT_MAX_RTRY_ERR	XB_CTRL_XMT_MAX_RTRY_IE
-#define	XB_STAT_RCV_ERR			XB_CTRL_RCV_IE
-#define	XB_STAT_XMT_RTRY_ERR		XB_CTRL_XMT_RTRY_IE
-/* reserved:			0x00000004 */
-#define	XB_STAT_MAXREQ_TOUT_ERR		XB_CTRL_MAXREQ_TOUT_IE
-#define	XB_STAT_SRC_TOUT_ERR		XB_CTRL_SRC_TOUT_IE
-
-/* link_aux_status(x) */
-#define	XB_AUX_STAT_RCV_CNT	0xff000000
-#define	XB_AUX_STAT_XMT_CNT	0x00ff0000
-#define	XB_AUX_STAT_TOUT_DST	0x0000ff00
-#define	XB_AUX_LINKFAIL_RST_BAD	0x00000040
-#define	XB_AUX_STAT_PRESENT	0x00000020
-#define	XB_AUX_STAT_PORT_WIDTH	0x00000010
-/*	reserved:		0x0000000f */
-
-/*
- * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
- * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf
- */
-#define	XB_ARB_GBR_MSK		0x1f
-#define	XB_ARB_RR_MSK		0x7
-#define	XB_ARB_GBR_SHFT(x)	(((x) & 0x3) * 8)
-#define	XB_ARB_RR_SHFT(x)	(((x) & 0x3) * 8 + 5)
-#define	XB_ARB_GBR_CNT(reg,x)	((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK)
-#define	XB_ARB_RR_CNT(reg,x)	((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK)
-
-/* XBOW_WID_STAT */
-#define	XB_WID_STAT_LINK_INTR_SHFT	(24)
-#define	XB_WID_STAT_LINK_INTR_MASK	(0xFF << XB_WID_STAT_LINK_INTR_SHFT)
-#define	XB_WID_STAT_LINK_INTR(x) \
-	(0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
-#define	XB_WID_STAT_WIDGET0_INTR	0x00800000
-#define XB_WID_STAT_SRCID_MASK		0x000003c0	/* Xbridge only */
-#define	XB_WID_STAT_REG_ACC_ERR		0x00000020
-#define XB_WID_STAT_RECV_TOUT		0x00000010	/* Xbridge only */
-#define XB_WID_STAT_ARB_TOUT		0x00000008	/* Xbridge only */
-#define	XB_WID_STAT_XTALK_ERR		0x00000004
-#define XB_WID_STAT_DST_TOUT		0x00000002	/* Xbridge only */
-#define	XB_WID_STAT_MULTI_ERR		0x00000001
-
-#define XB_WID_STAT_SRCID_SHFT		6
-
-/* XBOW_WID_CONTROL */
-#define XB_WID_CTRL_REG_ACC_IE		XB_WID_STAT_REG_ACC_ERR
-#define XB_WID_CTRL_RECV_TOUT		XB_WID_STAT_RECV_TOUT
-#define XB_WID_CTRL_ARB_TOUT		XB_WID_STAT_ARB_TOUT
-#define XB_WID_CTRL_XTALK_IE		XB_WID_STAT_XTALK_ERR
-
-/* XBOW_WID_INT_UPPER */
-/* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */
-
-/* XBOW WIDGET part number, in the ID register */
-#define XBOW_WIDGET_PART_NUM	0x0		/* crossbow */
-#define XXBOW_WIDGET_PART_NUM	0xd000		/* Xbridge */
-#define	XBOW_WIDGET_MFGR_NUM	0x0
-#define	XXBOW_WIDGET_MFGR_NUM	0x0
-#define PXBOW_WIDGET_PART_NUM   0xd100		/* PIC */
-
-#define	XBOW_REV_1_0		0x1	/* xbow rev 1.0 is "1" */
-#define	XBOW_REV_1_1		0x2	/* xbow rev 1.1 is "2" */
-#define XBOW_REV_1_2		0x3	/* xbow rev 1.2 is "3" */
-#define XBOW_REV_1_3		0x4	/* xbow rev 1.3 is "4" */
-#define XBOW_REV_2_0		0x5	/* xbow rev 2.0 is "5" */
-
-#define XXBOW_PART_REV_1_0		(XXBOW_WIDGET_PART_NUM << 4 | 0x1 )
-#define XXBOW_PART_REV_2_0		(XXBOW_WIDGET_PART_NUM << 4 | 0x2 )
-
-/* XBOW_WID_ARB_RELOAD */
-#define	XBOW_WID_ARB_RELOAD_INT	0x3f	/* GBR reload interval */
-
-#define IS_XBRIDGE_XBOW(wid) \
-	(XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \
-	XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
-
-#define IS_PIC_XBOW(wid) \
-	(XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \
-	XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
-
-#define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv)
-
-#endif /* _ASM_IA64_SN_XTALK_XBOW_H */
diff --git a/arch/ia64/sn/include/xtalk/xwidgetdev.h b/arch/ia64/sn/include/xtalk/xwidgetdev.h
deleted file mode 100644
index 2800eda0fd68..000000000000
--- a/arch/ia64/sn/include/xtalk/xwidgetdev.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved.
- */
-#ifndef _ASM_IA64_SN_XTALK_XWIDGET_H
-#define _ASM_IA64_SN_XTALK_XWIDGET_H
-
-/* WIDGET_ID */
-#define WIDGET_REV_NUM                  0xf0000000
-#define WIDGET_PART_NUM                 0x0ffff000
-#define WIDGET_MFG_NUM                  0x00000ffe
-#define WIDGET_REV_NUM_SHFT             28
-#define WIDGET_PART_NUM_SHFT            12
-#define WIDGET_MFG_NUM_SHFT             1
-
-#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
-#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
-#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
-#define XWIDGET_PART_REV_NUM(widgetid) ((XWIDGET_PART_NUM(widgetid) << 4) | \
-                                        XWIDGET_REV_NUM(widgetid))
-#define XWIDGET_PART_REV_NUM_REV(partrev) (partrev & 0xf)
-
-/* widget configuration registers */
-struct widget_cfg{
-	u32	w_id;	/* 0x04 */
-	u32	w_pad_0;	/* 0x00 */
-	u32	w_status;	/* 0x0c */
-	u32	w_pad_1;	/* 0x08 */
-	u32	w_err_upper_addr;	/* 0x14 */
-	u32	w_pad_2;	/* 0x10 */
-	u32	w_err_lower_addr;	/* 0x1c */
-	u32	w_pad_3;	/* 0x18 */
-	u32	w_control;	/* 0x24 */
-	u32	w_pad_4;	/* 0x20 */
-	u32	w_req_timeout;	/* 0x2c */
-	u32	w_pad_5;	/* 0x28 */
-	u32	w_intdest_upper_addr;	/* 0x34 */
-	u32	w_pad_6;	/* 0x30 */
-	u32	w_intdest_lower_addr;	/* 0x3c */
-	u32	w_pad_7;	/* 0x38 */
-	u32	w_err_cmd_word;	/* 0x44 */
-	u32	w_pad_8;	/* 0x40 */
-	u32	w_llp_cfg;	/* 0x4c */
-	u32	w_pad_9;	/* 0x48 */
-	u32	w_tflush;	/* 0x54 */
-	u32	w_pad_10;	/* 0x50 */
-};
-
-/*
- * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
- */
-struct xwidget_hwid{
-	int		mfg_num;
-	int		rev_num;
-	int		part_num;
-};
-
-struct xwidget_info{
-
-	struct xwidget_hwid	xwi_hwid;	/* Widget Identification */
-	char			xwi_masterxid;	/* Hub's Widget Port Number */
-	void			*xwi_hubinfo;     /* Hub's provider private info */
-	u64			*xwi_hub_provider; /* prom provider functions */
-	void			*xwi_vertex;
-};
-
-#endif                          /* _ASM_IA64_SN_XTALK_XWIDGET_H */
diff --git a/arch/ia64/sn/kernel/Makefile b/arch/ia64/sn/kernel/Makefile
deleted file mode 100644
index 9c349dd23265..000000000000
--- a/arch/ia64/sn/kernel/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-# arch/ia64/sn/kernel/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1999,2001-2006,2008 Silicon Graphics, Inc.  All Rights Reserved.
-#
-
-ccflags-y := -I $(srctree)/arch/ia64/sn/include
-
-obj-y				+= setup.o bte.o bte_error.o irq.o mca.o idle.o \
-				   huberror.o io_acpi_init.o io_common.o \
-				   io_init.o iomv.o klconflib.o pio_phys.o \
-				   sn2/
-obj-$(CONFIG_IA64_GENERIC)      += machvec.o
-obj-$(CONFIG_SGI_TIOCX)		+= tiocx.o
-obj-$(CONFIG_PCI_MSI)		+= msi_sn.o
diff --git a/arch/ia64/sn/kernel/bte.c b/arch/ia64/sn/kernel/bte.c
deleted file mode 100644
index 9900e6d4add6..000000000000
--- a/arch/ia64/sn/kernel/bte.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2000-2007 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#include <linux/module.h>
-#include <asm/sn/nodepda.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/pda.h>
-#include <asm/sn/shubio.h>
-#include <asm/nodedata.h>
-#include <asm/delay.h>
-
-#include <linux/memblock.h>
-#include <linux/string.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-
-#include <asm/sn/bte.h>
-
-#ifndef L1_CACHE_MASK
-#define L1_CACHE_MASK (L1_CACHE_BYTES - 1)
-#endif
-
-/* two interfaces on two btes */
-#define MAX_INTERFACES_TO_TRY		4
-#define MAX_NODES_TO_TRY		2
-
-static struct bteinfo_s *bte_if_on_node(nasid_t nasid, int interface)
-{
-	nodepda_t *tmp_nodepda;
-
-	if (nasid_to_cnodeid(nasid) == -1)
-		return (struct bteinfo_s *)NULL;
-
-	tmp_nodepda = NODEPDA(nasid_to_cnodeid(nasid));
-	return &tmp_nodepda->bte_if[interface];
-
-}
-
-static inline void bte_start_transfer(struct bteinfo_s *bte, u64 len, u64 mode)
-{
-	if (is_shub2()) {
-		BTE_CTRL_STORE(bte, (IBLS_BUSY | ((len) | (mode) << 24)));
-	} else {
-		BTE_LNSTAT_STORE(bte, len);
-		BTE_CTRL_STORE(bte, mode);
-	}
-}
-
-/************************************************************************
- * Block Transfer Engine copy related functions.
- *
- ***********************************************************************/
-
-/*
- * bte_copy(src, dest, len, mode, notification)
- *
- * Use the block transfer engine to move kernel memory from src to dest
- * using the assigned mode.
- *
- * Parameters:
- *   src - physical address of the transfer source.
- *   dest - physical address of the transfer destination.
- *   len - number of bytes to transfer from source to dest.
- *   mode - hardware defined.  See reference information
- *          for IBCT0/1 in the SHUB Programmers Reference
- *   notification - kernel virtual address of the notification cache
- *                  line.  If NULL, the default is used and
- *                  the bte_copy is synchronous.
- *
- * NOTE:  This function requires src, dest, and len to
- * be cacheline aligned.
- */
-bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
-{
-	u64 transfer_size;
-	u64 transfer_stat;
-	u64 notif_phys_addr;
-	struct bteinfo_s *bte;
-	bte_result_t bte_status;
-	unsigned long irq_flags;
-	unsigned long itc_end = 0;
-	int nasid_to_try[MAX_NODES_TO_TRY];
-	int my_nasid = cpuid_to_nasid(raw_smp_processor_id());
-	int bte_if_index, nasid_index;
-	int bte_first, btes_per_node = BTES_PER_NODE;
-
-	BTE_PRINTK(("bte_copy(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%p)\n",
-		    src, dest, len, mode, notification));
-
-	if (len == 0) {
-		return BTE_SUCCESS;
-	}
-
-	BUG_ON(len & L1_CACHE_MASK);
-	BUG_ON(src & L1_CACHE_MASK);
-	BUG_ON(dest & L1_CACHE_MASK);
-	BUG_ON(len > BTE_MAX_XFER);
-
-	/*
-	 * Start with interface corresponding to cpu number
-	 */
-	bte_first = raw_smp_processor_id() % btes_per_node;
-
-	if (mode & BTE_USE_DEST) {
-		/* try remote then local */
-		nasid_to_try[0] = NASID_GET(dest);
-		if (mode & BTE_USE_ANY) {
-			nasid_to_try[1] = my_nasid;
-		} else {
-			nasid_to_try[1] = 0;
-		}
-	} else {
-		/* try local then remote */
-		nasid_to_try[0] = my_nasid;
-		if (mode & BTE_USE_ANY) {
-			nasid_to_try[1] = NASID_GET(dest);
-		} else {
-			nasid_to_try[1] = 0;
-		}
-	}
-
-retry_bteop:
-	do {
-		local_irq_save(irq_flags);
-
-		bte_if_index = bte_first;
-		nasid_index = 0;
-
-		/* Attempt to lock one of the BTE interfaces. */
-		while (nasid_index < MAX_NODES_TO_TRY) {
-			bte = bte_if_on_node(nasid_to_try[nasid_index],bte_if_index);
-
-			if (bte == NULL) {
-				nasid_index++;
-				continue;
-			}
-
-			if (spin_trylock(&bte->spinlock)) {
-				if (!(*bte->most_rcnt_na & BTE_WORD_AVAILABLE) ||
-				    (BTE_LNSTAT_LOAD(bte) & BTE_ACTIVE)) {
-					/* Got the lock but BTE still busy */
-					spin_unlock(&bte->spinlock);
-				} else {
-					/* we got the lock and it's not busy */
-					break;
-				}
-			}
-
-			bte_if_index = (bte_if_index + 1) % btes_per_node; /* Next interface */
-			if (bte_if_index == bte_first) {
-				/*
-				 * We've tried all interfaces on this node
-				 */
-				nasid_index++;
-			}
-
-			bte = NULL;
-		}
-
-		if (bte != NULL) {
-			break;
-		}
-
-		local_irq_restore(irq_flags);
-
-		if (!(mode & BTE_WACQUIRE)) {
-			return BTEFAIL_NOTAVAIL;
-		}
-	} while (1);
-
-	if (notification == NULL) {
-		/* User does not want to be notified. */
-		bte->most_rcnt_na = &bte->notify;
-	} else {
-		bte->most_rcnt_na = notification;
-	}
-
-	/* Calculate the number of cache lines to transfer. */
-	transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK);
-
-	/* Initialize the notification to a known value. */
-	*bte->most_rcnt_na = BTE_WORD_BUSY;
-	notif_phys_addr = (u64)bte->most_rcnt_na;
-
-	/* Set the source and destination registers */
-	BTE_PRINTKV(("IBSA = 0x%lx)\n", src));
-	BTE_SRC_STORE(bte, src);
-	BTE_PRINTKV(("IBDA = 0x%lx)\n", dest));
-	BTE_DEST_STORE(bte, dest);
-
-	/* Set the notification register */
-	BTE_PRINTKV(("IBNA = 0x%lx)\n", notif_phys_addr));
-	BTE_NOTIF_STORE(bte, notif_phys_addr);
-
-	/* Initiate the transfer */
-	BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode)));
-	bte_start_transfer(bte, transfer_size, BTE_VALID_MODE(mode));
-
-	itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec);
-
-	spin_unlock_irqrestore(&bte->spinlock, irq_flags);
-
-	if (notification != NULL) {
-		return BTE_SUCCESS;
-	}
-
-	while ((transfer_stat = *bte->most_rcnt_na) == BTE_WORD_BUSY) {
-		cpu_relax();
-		if (ia64_get_itc() > itc_end) {
-			BTE_PRINTK(("BTE timeout nasid 0x%x bte%d IBLS = 0x%lx na 0x%lx\n",
-				NASID_GET(bte->bte_base_addr), bte->bte_num,
-				BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na) );
-			bte->bte_error_count++;
-			bte->bh_error = IBLS_ERROR;
-			bte_error_handler(NODEPDA(bte->bte_cnode));
-			*bte->most_rcnt_na = BTE_WORD_AVAILABLE;
-			goto retry_bteop;
-		}
-	}
-
-	BTE_PRINTKV((" Delay Done.  IBLS = 0x%lx, most_rcnt_na = 0x%lx\n",
-		     BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
-
-	if (transfer_stat & IBLS_ERROR) {
-		bte_status = BTE_GET_ERROR_STATUS(transfer_stat);
-	} else {
-		bte_status = BTE_SUCCESS;
-	}
-	*bte->most_rcnt_na = BTE_WORD_AVAILABLE;
-
-	BTE_PRINTK(("Returning status is 0x%lx and most_rcnt_na is 0x%lx\n",
-		    BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
-
-	return bte_status;
-}
-
-EXPORT_SYMBOL(bte_copy);
-
-/*
- * bte_unaligned_copy(src, dest, len, mode)
- *
- * use the block transfer engine to move kernel
- * memory from src to dest using the assigned mode.
- *
- * Parameters:
- *   src - physical address of the transfer source.
- *   dest - physical address of the transfer destination.
- *   len - number of bytes to transfer from source to dest.
- *   mode - hardware defined.  See reference information
- *          for IBCT0/1 in the SGI documentation.
- *
- * NOTE: If the source, dest, and len are all cache line aligned,
- * then it would be _FAR_ preferable to use bte_copy instead.
- */
-bte_result_t bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode)
-{
-	int destFirstCacheOffset;
-	u64 headBteSource;
-	u64 headBteLen;
-	u64 headBcopySrcOffset;
-	u64 headBcopyDest;
-	u64 headBcopyLen;
-	u64 footBteSource;
-	u64 footBteLen;
-	u64 footBcopyDest;
-	u64 footBcopyLen;
-	bte_result_t rv;
-	char *bteBlock, *bteBlock_unaligned;
-
-	if (len == 0) {
-		return BTE_SUCCESS;
-	}
-
-	/* temporary buffer used during unaligned transfers */
-	bteBlock_unaligned = kmalloc(len + 3 * L1_CACHE_BYTES, GFP_KERNEL);
-	if (bteBlock_unaligned == NULL) {
-		return BTEFAIL_NOTAVAIL;
-	}
-	bteBlock = (char *)L1_CACHE_ALIGN((u64) bteBlock_unaligned);
-
-	headBcopySrcOffset = src & L1_CACHE_MASK;
-	destFirstCacheOffset = dest & L1_CACHE_MASK;
-
-	/*
-	 * At this point, the transfer is broken into
-	 * (up to) three sections.  The first section is
-	 * from the start address to the first physical
-	 * cache line, the second is from the first physical
-	 * cache line to the last complete cache line,
-	 * and the third is from the last cache line to the
-	 * end of the buffer.  The first and third sections
-	 * are handled by bte copying into a temporary buffer
-	 * and then bcopy'ing the necessary section into the
-	 * final location.  The middle section is handled with
-	 * a standard bte copy.
-	 *
-	 * One nasty exception to the above rule is when the
-	 * source and destination are not symmetrically
-	 * mis-aligned.  If the source offset from the first
-	 * cache line is different from the destination offset,
-	 * we make the first section be the entire transfer
-	 * and the bcopy the entire block into place.
-	 */
-	if (headBcopySrcOffset == destFirstCacheOffset) {
-
-		/*
-		 * Both the source and destination are the same
-		 * distance from a cache line boundary so we can
-		 * use the bte to transfer the bulk of the
-		 * data.
-		 */
-		headBteSource = src & ~L1_CACHE_MASK;
-		headBcopyDest = dest;
-		if (headBcopySrcOffset) {
-			headBcopyLen =
-			    (len >
-			     (L1_CACHE_BYTES -
-			      headBcopySrcOffset) ? L1_CACHE_BYTES
-			     - headBcopySrcOffset : len);
-			headBteLen = L1_CACHE_BYTES;
-		} else {
-			headBcopyLen = 0;
-			headBteLen = 0;
-		}
-
-		if (len > headBcopyLen) {
-			footBcopyLen = (len - headBcopyLen) & L1_CACHE_MASK;
-			footBteLen = L1_CACHE_BYTES;
-
-			footBteSource = src + len - footBcopyLen;
-			footBcopyDest = dest + len - footBcopyLen;
-
-			if (footBcopyDest == (headBcopyDest + headBcopyLen)) {
-				/*
-				 * We have two contiguous bcopy
-				 * blocks.  Merge them.
-				 */
-				headBcopyLen += footBcopyLen;
-				headBteLen += footBteLen;
-			} else if (footBcopyLen > 0) {
-				rv = bte_copy(footBteSource,
-					      ia64_tpa((unsigned long)bteBlock),
-					      footBteLen, mode, NULL);
-				if (rv != BTE_SUCCESS) {
-					kfree(bteBlock_unaligned);
-					return rv;
-				}
-
-				memcpy(__va(footBcopyDest),
-				       (char *)bteBlock, footBcopyLen);
-			}
-		} else {
-			footBcopyLen = 0;
-			footBteLen = 0;
-		}
-
-		if (len > (headBcopyLen + footBcopyLen)) {
-			/* now transfer the middle. */
-			rv = bte_copy((src + headBcopyLen),
-				      (dest +
-				       headBcopyLen),
-				      (len - headBcopyLen -
-				       footBcopyLen), mode, NULL);
-			if (rv != BTE_SUCCESS) {
-				kfree(bteBlock_unaligned);
-				return rv;
-			}
-
-		}
-	} else {
-
-		/*
-		 * The transfer is not symmetric, we will
-		 * allocate a buffer large enough for all the
-		 * data, bte_copy into that buffer and then
-		 * bcopy to the destination.
-		 */
-
-		headBcopySrcOffset = src & L1_CACHE_MASK;
-		headBcopyDest = dest;
-		headBcopyLen = len;
-
-		headBteSource = src - headBcopySrcOffset;
-		/* Add the leading and trailing bytes from source */
-		headBteLen = L1_CACHE_ALIGN(len + headBcopySrcOffset);
-	}
-
-	if (headBcopyLen > 0) {
-		rv = bte_copy(headBteSource,
-			      ia64_tpa((unsigned long)bteBlock), headBteLen,
-			      mode, NULL);
-		if (rv != BTE_SUCCESS) {
-			kfree(bteBlock_unaligned);
-			return rv;
-		}
-
-		memcpy(__va(headBcopyDest), ((char *)bteBlock +
-					     headBcopySrcOffset), headBcopyLen);
-	}
-	kfree(bteBlock_unaligned);
-	return BTE_SUCCESS;
-}
-
-EXPORT_SYMBOL(bte_unaligned_copy);
-
-/************************************************************************
- * Block Transfer Engine initialization functions.
- *
- ***********************************************************************/
-static void bte_recovery_timeout(struct timer_list *t)
-{
-	struct nodepda_s *nodepda = from_timer(nodepda, t, bte_recovery_timer);
-
-	bte_error_handler(nodepda);
-}
-
-/*
- * bte_init_node(nodepda, cnode)
- *
- * Initialize the nodepda structure with BTE base addresses and
- * spinlocks.
- */
-void bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode)
-{
-	int i;
-
-	/*
-	 * Indicate that all the block transfer engines on this node
-	 * are available.
-	 */
-
-	/*
-	 * Allocate one bte_recover_t structure per node.  It holds
-	 * the recovery lock for node.  All the bte interface structures
-	 * will point at this one bte_recover structure to get the lock.
-	 */
-	spin_lock_init(&mynodepda->bte_recovery_lock);
-	timer_setup(&mynodepda->bte_recovery_timer, bte_recovery_timeout, 0);
-
-	for (i = 0; i < BTES_PER_NODE; i++) {
-		u64 *base_addr;
-
-		/* Which link status register should we use? */
-		base_addr = (u64 *)
-		    REMOTE_HUB_ADDR(cnodeid_to_nasid(cnode), BTE_BASE_ADDR(i));
-		mynodepda->bte_if[i].bte_base_addr = base_addr;
-		mynodepda->bte_if[i].bte_source_addr = BTE_SOURCE_ADDR(base_addr);
-		mynodepda->bte_if[i].bte_destination_addr = BTE_DEST_ADDR(base_addr);
-		mynodepda->bte_if[i].bte_control_addr = BTE_CTRL_ADDR(base_addr);
-		mynodepda->bte_if[i].bte_notify_addr = BTE_NOTIF_ADDR(base_addr);
-
-		/*
-		 * Initialize the notification and spinlock
-		 * so the first transfer can occur.
-		 */
-		mynodepda->bte_if[i].most_rcnt_na =
-		    &(mynodepda->bte_if[i].notify);
-		mynodepda->bte_if[i].notify = BTE_WORD_AVAILABLE;
-		spin_lock_init(&mynodepda->bte_if[i].spinlock);
-
-		mynodepda->bte_if[i].bte_cnode = cnode;
-		mynodepda->bte_if[i].bte_error_count = 0;
-		mynodepda->bte_if[i].bte_num = i;
-		mynodepda->bte_if[i].cleanup_active = 0;
-		mynodepda->bte_if[i].bh_error = 0;
-	}
-
-}
diff --git a/arch/ia64/sn/kernel/bte_error.c b/arch/ia64/sn/kernel/bte_error.c
deleted file mode 100644
index d92786c09b34..000000000000
--- a/arch/ia64/sn/kernel/bte_error.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2000-2007 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#include <linux/types.h>
-#include <asm/sn/sn_sal.h>
-#include "ioerror.h"
-#include <asm/sn/addrs.h>
-#include <asm/sn/shubio.h>
-#include <asm/sn/geo.h>
-#include "xtalk/xwidgetdev.h"
-#include "xtalk/hubdev.h"
-#include <asm/sn/bte.h>
-#include <asm/param.h>
-
-/*
- * Bte error handling is done in two parts.  The first captures
- * any crb related errors.  Since there can be multiple crbs per
- * interface and multiple interfaces active, we need to wait until
- * all active crbs are completed.  This is the first job of the
- * second part error handler.  When all bte related CRBs are cleanly
- * completed, it resets the interfaces and gets them ready for new
- * transfers to be queued.
- */
-
-/*
- * Wait until all BTE related CRBs are completed
- * and then reset the interfaces.
- */
-static int shub1_bte_error_handler(struct nodepda_s *err_nodepda)
-{
-	struct timer_list *recovery_timer = &err_nodepda->bte_recovery_timer;
-	nasid_t nasid;
-	int i;
-	int valid_crbs;
-	ii_imem_u_t imem;	/* II IMEM Register */
-	ii_icrb0_d_u_t icrbd;	/* II CRB Register D */
-	ii_ibcr_u_t ibcr;
-	ii_icmr_u_t icmr;
-	ii_ieclr_u_t ieclr;
-
-	BTE_PRINTK(("shub1_bte_error_handler(%p) - %d\n", err_nodepda,
-		    smp_processor_id()));
-
-	if ((err_nodepda->bte_if[0].bh_error == BTE_SUCCESS) &&
-	    (err_nodepda->bte_if[1].bh_error == BTE_SUCCESS)) {
-		BTE_PRINTK(("eh:%p:%d Nothing to do.\n", err_nodepda,
-			    smp_processor_id()));
-		return 1;
-	}
-
-	/* Determine information about our hub */
-	nasid = cnodeid_to_nasid(err_nodepda->bte_if[0].bte_cnode);
-
-	/*
-	 * A BTE transfer can use multiple CRBs.  We need to make sure
-	 * that all the BTE CRBs are complete (or timed out) before
-	 * attempting to clean up the error.  Resetting the BTE while
-	 * there are still BTE CRBs active will hang the BTE.
-	 * We should look at all the CRBs to see if they are allocated
-	 * to the BTE and see if they are still active.  When none
-	 * are active, we can continue with the cleanup.
-	 *
-	 * We also want to make sure that the local NI port is up.
-	 * When a router resets the NI port can go down, while it
-	 * goes through the LLP handshake, but then comes back up.
-	 */
-	icmr.ii_icmr_regval = REMOTE_HUB_L(nasid, IIO_ICMR);
-	if (icmr.ii_icmr_fld_s.i_crb_mark != 0) {
-		/*
-		 * There are errors which still need to be cleaned up by
-		 * hubiio_crb_error_handler
-		 */
-		mod_timer(recovery_timer, jiffies + (HZ * 5));
-		BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda,
-			    smp_processor_id()));
-		return 1;
-	}
-	if (icmr.ii_icmr_fld_s.i_crb_vld != 0) {
-
-		valid_crbs = icmr.ii_icmr_fld_s.i_crb_vld;
-
-		for (i = 0; i < IIO_NUM_CRBS; i++) {
-			if (!((1 << i) & valid_crbs)) {
-				/* This crb was not marked as valid, ignore */
-				continue;
-			}
-			icrbd.ii_icrb0_d_regval =
-			    REMOTE_HUB_L(nasid, IIO_ICRB_D(i));
-			if (icrbd.d_bteop) {
-				mod_timer(recovery_timer, jiffies + (HZ * 5));
-				BTE_PRINTK(("eh:%p:%d Valid %d, Giving up\n",
-					    err_nodepda, smp_processor_id(),
-					    i));
-				return 1;
-			}
-		}
-	}
-
-	BTE_PRINTK(("eh:%p:%d Cleaning up\n", err_nodepda, smp_processor_id()));
-	/* Re-enable both bte interfaces */
-	imem.ii_imem_regval = REMOTE_HUB_L(nasid, IIO_IMEM);
-	imem.ii_imem_fld_s.i_b0_esd = imem.ii_imem_fld_s.i_b1_esd = 1;
-	REMOTE_HUB_S(nasid, IIO_IMEM, imem.ii_imem_regval);
-
-	/* Clear BTE0/1 error bits */
-	ieclr.ii_ieclr_regval = 0;
-	if (err_nodepda->bte_if[0].bh_error != BTE_SUCCESS)
-		ieclr.ii_ieclr_fld_s.i_e_bte_0 = 1;
-	if (err_nodepda->bte_if[1].bh_error != BTE_SUCCESS)
-		ieclr.ii_ieclr_fld_s.i_e_bte_1 = 1;
-	REMOTE_HUB_S(nasid, IIO_IECLR, ieclr.ii_ieclr_regval);
-
-	/* Reinitialize both BTE state machines. */
-	ibcr.ii_ibcr_regval = REMOTE_HUB_L(nasid, IIO_IBCR);
-	ibcr.ii_ibcr_fld_s.i_soft_reset = 1;
-	REMOTE_HUB_S(nasid, IIO_IBCR, ibcr.ii_ibcr_regval);
-
-	del_timer(recovery_timer);
-	return 0;
-}
-
-/*
- * Wait until all BTE related CRBs are completed
- * and then reset the interfaces.
- */
-static int shub2_bte_error_handler(struct nodepda_s *err_nodepda)
-{
-	struct timer_list *recovery_timer = &err_nodepda->bte_recovery_timer;
-	struct bteinfo_s *bte;
-	nasid_t nasid;
-	u64 status;
-	int i;
-
-	nasid = cnodeid_to_nasid(err_nodepda->bte_if[0].bte_cnode);
-
-	/*
-	 * Verify that all the BTEs are complete
-	 */
-	for (i = 0; i < BTES_PER_NODE; i++) {
-		bte = &err_nodepda->bte_if[i];
-		status = BTE_LNSTAT_LOAD(bte);
-		if (status & IBLS_ERROR) {
-			bte->bh_error = BTE_SHUB2_ERROR(status);
-			continue;
-		}
-		if (!(status & IBLS_BUSY))
-			continue;
-		mod_timer(recovery_timer, jiffies + (HZ * 5));
-		BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda,
-			    smp_processor_id()));
-		return 1;
-	}
-	if (ia64_sn_bte_recovery(nasid))
-		panic("bte_error_handler(): Fatal BTE Error");
-
-	del_timer(recovery_timer);
-	return 0;
-}
-
-/*
- * Wait until all BTE related CRBs are completed
- * and then reset the interfaces.
- */
-void bte_error_handler(struct nodepda_s *err_nodepda)
-{
-	spinlock_t *recovery_lock = &err_nodepda->bte_recovery_lock;
-	int i;
-	unsigned long irq_flags;
-	volatile u64 *notify;
-	bte_result_t bh_error;
-
-	BTE_PRINTK(("bte_error_handler(%p) - %d\n", err_nodepda,
-		    smp_processor_id()));
-
-	spin_lock_irqsave(recovery_lock, irq_flags);
-
-	/*
-	 * Lock all interfaces on this node to prevent new transfers
-	 * from being queued.
-	 */
-	for (i = 0; i < BTES_PER_NODE; i++) {
-		if (err_nodepda->bte_if[i].cleanup_active) {
-			continue;
-		}
-		spin_lock(&err_nodepda->bte_if[i].spinlock);
-		BTE_PRINTK(("eh:%p:%d locked %d\n", err_nodepda,
-			    smp_processor_id(), i));
-		err_nodepda->bte_if[i].cleanup_active = 1;
-	}
-
-	if (is_shub1()) {
-		if (shub1_bte_error_handler(err_nodepda)) {
-			spin_unlock_irqrestore(recovery_lock, irq_flags);
-			return;
-		}
-	} else {
-		if (shub2_bte_error_handler(err_nodepda)) {
-			spin_unlock_irqrestore(recovery_lock, irq_flags);
-			return;
-		}
-	}
-
-	for (i = 0; i < BTES_PER_NODE; i++) {
-		bh_error = err_nodepda->bte_if[i].bh_error;
-		if (bh_error != BTE_SUCCESS) {
-			/* There is an error which needs to be notified */
-			notify = err_nodepda->bte_if[i].most_rcnt_na;
-			BTE_PRINTK(("cnode %d bte %d error=0x%lx\n",
-				    err_nodepda->bte_if[i].bte_cnode,
-				    err_nodepda->bte_if[i].bte_num,
-				    IBLS_ERROR | (u64) bh_error));
-			*notify = IBLS_ERROR | bh_error;
-			err_nodepda->bte_if[i].bh_error = BTE_SUCCESS;
-		}
-
-		err_nodepda->bte_if[i].cleanup_active = 0;
-		BTE_PRINTK(("eh:%p:%d Unlocked %d\n", err_nodepda,
-			    smp_processor_id(), i));
-		spin_unlock(&err_nodepda->bte_if[i].spinlock);
-	}
-
-	spin_unlock_irqrestore(recovery_lock, irq_flags);
-}
-
-/*
- * First part error handler.  This is called whenever any error CRB interrupt
- * is generated by the II.
- */
-void
-bte_crb_error_handler(cnodeid_t cnode, int btenum,
-                      int crbnum, ioerror_t * ioe, int bteop)
-{
-	struct bteinfo_s *bte;
-
-
-	bte = &(NODEPDA(cnode)->bte_if[btenum]);
-
-	/*
-	 * The caller has already figured out the error type, we save that
-	 * in the bte handle structure for the thread exercising the
-	 * interface to consume.
-	 */
-	bte->bh_error = ioe->ie_errortype + BTEFAIL_OFFSET;
-	bte->bte_error_count++;
-
-	BTE_PRINTK(("Got an error on cnode %d bte %d: HW error type 0x%x\n",
-		bte->bte_cnode, bte->bte_num, ioe->ie_errortype));
-	bte_error_handler(NODEPDA(cnode));
-}
-
diff --git a/arch/ia64/sn/kernel/huberror.c b/arch/ia64/sn/kernel/huberror.c
deleted file mode 100644
index 97fa56dddf50..000000000000
--- a/arch/ia64/sn/kernel/huberror.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000,2002-2007 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <asm/delay.h>
-#include <asm/sn/sn_sal.h>
-#include "ioerror.h"
-#include <asm/sn/addrs.h>
-#include <asm/sn/shubio.h>
-#include <asm/sn/geo.h>
-#include "xtalk/xwidgetdev.h"
-#include "xtalk/hubdev.h"
-#include <asm/sn/bte.h>
-
-void hubiio_crb_error_handler(struct hubdev_info *hubdev_info);
-extern void bte_crb_error_handler(cnodeid_t, int, int, ioerror_t *,
-				  int);
-static irqreturn_t hub_eint_handler(int irq, void *arg)
-{
-	struct hubdev_info *hubdev_info;
-	struct ia64_sal_retval ret_stuff;
-	nasid_t nasid;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-	hubdev_info = (struct hubdev_info *)arg;
-	nasid = hubdev_info->hdi_nasid;
-
-	if (is_shub1()) {
-		SAL_CALL_NOLOCK(ret_stuff, SN_SAL_HUB_ERROR_INTERRUPT,
-			(u64) nasid, 0, 0, 0, 0, 0, 0);
-
-		if ((int)ret_stuff.v0)
-			panic("%s: Fatal %s Error", __func__,
-				((nasid & 1) ? "TIO" : "HUBII"));
-
-		if (!(nasid & 1)) /* Not a TIO, handle CRB errors */
-			(void)hubiio_crb_error_handler(hubdev_info);
-	} else
-		if (nasid & 1) {	/* TIO errors */
-			SAL_CALL_NOLOCK(ret_stuff, SN_SAL_HUB_ERROR_INTERRUPT,
-				(u64) nasid, 0, 0, 0, 0, 0, 0);
-
-			if ((int)ret_stuff.v0)
-				panic("%s: Fatal TIO Error", __func__);
-		} else
-			bte_error_handler(NODEPDA(nasid_to_cnodeid(nasid)));
-
-	return IRQ_HANDLED;
-}
-
-/*
- * Free the hub CRB "crbnum" which encountered an error.
- * Assumption is, error handling was successfully done,
- * and we now want to return the CRB back to Hub for normal usage.
- *
- * In order to free the CRB, all that's needed is to de-allocate it
- *
- * Assumption:
- *      No other processor is mucking around with the hub control register.
- *      So, upper layer has to single thread this.
- */
-void hubiio_crb_free(struct hubdev_info *hubdev_info, int crbnum)
-{
-	ii_icrb0_b_u_t icrbb;
-
-	/*
-	 * The hardware does NOT clear the mark bit, so it must get cleared
-	 * here to be sure the error is not processed twice.
-	 */
-	icrbb.ii_icrb0_b_regval = REMOTE_HUB_L(hubdev_info->hdi_nasid,
-					       IIO_ICRB_B(crbnum));
-	icrbb.b_mark = 0;
-	REMOTE_HUB_S(hubdev_info->hdi_nasid, IIO_ICRB_B(crbnum),
-		     icrbb.ii_icrb0_b_regval);
-	/*
-	 * Deallocate the register wait till hub indicates it's done.
-	 */
-	REMOTE_HUB_S(hubdev_info->hdi_nasid, IIO_ICDR, (IIO_ICDR_PND | crbnum));
-	while (REMOTE_HUB_L(hubdev_info->hdi_nasid, IIO_ICDR) & IIO_ICDR_PND)
-		cpu_relax();
-
-}
-
-/*
- * hubiio_crb_error_handler
- *
- *	This routine gets invoked when a hub gets an error 
- *	interrupt. So, the routine is running in interrupt context
- *	at error interrupt level.
- * Action:
- *	It's responsible for identifying ALL the CRBs that are marked
- *	with error, and process them. 
- *	
- * 	If you find the CRB that's marked with error, map this to the
- *	reason it caused error, and invoke appropriate error handler.
- *
- *	XXX Be aware of the information in the context register.
- *
- * NOTE:
- *	Use REMOTE_HUB_* macro instead of LOCAL_HUB_* so that the interrupt
- *	handler can be run on any node. (not necessarily the node 
- *	corresponding to the hub that encountered error).
- */
-
-void hubiio_crb_error_handler(struct hubdev_info *hubdev_info)
-{
-	nasid_t nasid;
-	ii_icrb0_a_u_t icrba;	/* II CRB Register A */
-	ii_icrb0_b_u_t icrbb;	/* II CRB Register B */
-	ii_icrb0_c_u_t icrbc;	/* II CRB Register C */
-	ii_icrb0_d_u_t icrbd;	/* II CRB Register D */
-	ii_icrb0_e_u_t icrbe;	/* II CRB Register D */
-	int i;
-	int num_errors = 0;	/* Num of errors handled */
-	ioerror_t ioerror;
-
-	nasid = hubdev_info->hdi_nasid;
-
-	/*
-	 * XXX - Add locking for any recovery actions
-	 */
-	/*
-	 * Scan through all CRBs in the Hub, and handle the errors
-	 * in any of the CRBs marked.
-	 */
-	for (i = 0; i < IIO_NUM_CRBS; i++) {
-		/* Check this crb entry to see if it is in error. */
-		icrbb.ii_icrb0_b_regval = REMOTE_HUB_L(nasid, IIO_ICRB_B(i));
-
-		if (icrbb.b_mark == 0) {
-			continue;
-		}
-
-		icrba.ii_icrb0_a_regval = REMOTE_HUB_L(nasid, IIO_ICRB_A(i));
-
-		IOERROR_INIT(&ioerror);
-
-		/* read other CRB error registers. */
-		icrbc.ii_icrb0_c_regval = REMOTE_HUB_L(nasid, IIO_ICRB_C(i));
-		icrbd.ii_icrb0_d_regval = REMOTE_HUB_L(nasid, IIO_ICRB_D(i));
-		icrbe.ii_icrb0_e_regval = REMOTE_HUB_L(nasid, IIO_ICRB_E(i));
-
-		IOERROR_SETVALUE(&ioerror, errortype, icrbb.b_ecode);
-
-		/* Check if this error is due to BTE operation,
-		 * and handle it separately.
-		 */
-		if (icrbd.d_bteop ||
-		    ((icrbb.b_initiator == IIO_ICRB_INIT_BTE0 ||
-		      icrbb.b_initiator == IIO_ICRB_INIT_BTE1) &&
-		     (icrbb.b_imsgtype == IIO_ICRB_IMSGT_BTE ||
-		      icrbb.b_imsgtype == IIO_ICRB_IMSGT_SN1NET))) {
-
-			int bte_num;
-
-			if (icrbd.d_bteop)
-				bte_num = icrbc.c_btenum;
-			else	/* b_initiator bit 2 gives BTE number */
-				bte_num = (icrbb.b_initiator & 0x4) >> 2;
-
-			hubiio_crb_free(hubdev_info, i);
-
-			bte_crb_error_handler(nasid_to_cnodeid(nasid), bte_num,
-					      i, &ioerror, icrbd.d_bteop);
-			num_errors++;
-			continue;
-		}
-	}
-}
-
-/*
- * Function	: hub_error_init
- * Purpose	: initialize the error handling requirements for a given hub.
- * Parameters	: cnode, the compact nodeid.
- * Assumptions	: Called only once per hub, either by a local cpu. Or by a
- *			remote cpu, when this hub is headless.(cpuless)
- * Returns	: None
- */
-void hub_error_init(struct hubdev_info *hubdev_info)
-{
-
-	if (request_irq(SGI_II_ERROR, hub_eint_handler, IRQF_SHARED,
-			"SN_hub_error", hubdev_info)) {
-		printk(KERN_ERR "hub_error_init: Failed to request_irq for 0x%p\n",
-		    hubdev_info);
-		return;
-	}
-	irq_set_handler(SGI_II_ERROR, handle_level_irq);
-	sn_set_err_irq_affinity(SGI_II_ERROR);
-}
-
-
-/*
- * Function	: ice_error_init
- * Purpose	: initialize the error handling requirements for a given tio.
- * Parameters	: cnode, the compact nodeid.
- * Assumptions	: Called only once per tio.
- * Returns	: None
- */
-void ice_error_init(struct hubdev_info *hubdev_info)
-{
-
-        if (request_irq
-            (SGI_TIO_ERROR, (void *)hub_eint_handler, IRQF_SHARED, "SN_TIO_error",
-             (void *)hubdev_info)) {
-                printk("ice_error_init: request_irq() error hubdev_info 0x%p\n",
-                       hubdev_info);
-		return;
-	}
-	irq_set_handler(SGI_TIO_ERROR, handle_level_irq);
-	sn_set_err_irq_affinity(SGI_TIO_ERROR);
-}
-
diff --git a/arch/ia64/sn/kernel/idle.c b/arch/ia64/sn/kernel/idle.c
deleted file mode 100644
index 49d178f022b5..000000000000
--- a/arch/ia64/sn/kernel/idle.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
- */
-
-#include <asm/sn/leds.h>
-
-void snidle(int state)
-{
-	if (state) {
-		if (pda->idle_flag == 0) {
-			/* 
-			 * Turn the activity LED off.
-			 */
-			set_led_bits(0, LED_CPU_ACTIVITY);
-		}
-
-		pda->idle_flag = 1;
-	} else {
-		/* 
-		 * Turn the activity LED on.
-		 */
-		set_led_bits(LED_CPU_ACTIVITY, LED_CPU_ACTIVITY);
-
-		pda->idle_flag = 0;
-	}
-}
diff --git a/arch/ia64/sn/kernel/io_acpi_init.c b/arch/ia64/sn/kernel/io_acpi_init.c
deleted file mode 100644
index c31fe637b0b4..000000000000
--- a/arch/ia64/sn/kernel/io_acpi_init.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <asm/sn/types.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/sn_sal.h>
-#include "xtalk/hubdev.h"
-#include <linux/acpi.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-
-
-/*
- * The code in this file will only be executed when running with
- * a PROM that has ACPI IO support. (i.e., SN_ACPI_BASE_SUPPORT() == 1)
- */
-
-
-/*
- * This value must match the UUID the PROM uses
- * (io/acpi/defblk.c) when building a vendor descriptor.
- */
-struct acpi_vendor_uuid sn_uuid = {
-	.subtype = 0,
-	.data	= { 0x2c, 0xc6, 0xa6, 0xfe, 0x9c, 0x44, 0xda, 0x11,
-		    0xa2, 0x7c, 0x08, 0x00, 0x69, 0x13, 0xea, 0x51 },
-};
-
-struct sn_pcidev_match {
-	u8 bus;
-	unsigned int devfn;
-	acpi_handle handle;
-};
-
-/*
- * Perform the early IO init in PROM.
- */
-static long
-sal_ioif_init(u64 *result)
-{
-	struct ia64_sal_retval isrv = {0,0,0,0};
-
-	SAL_CALL_NOLOCK(isrv,
-			SN_SAL_IOIF_INIT, 0, 0, 0, 0, 0, 0, 0);
-	*result = isrv.v0;
-	return isrv.status;
-}
-
-/*
- * sn_acpi_hubdev_init() - This function is called by acpi_ns_get_device_callback()
- *			   for all SGIHUB and SGITIO acpi devices defined in the
- *			   DSDT. It obtains the hubdev_info pointer from the
- *			   ACPI vendor resource, which the PROM setup, and sets up the
- *			   hubdev_info in the pda.
- */
-
-static acpi_status __init
-sn_acpi_hubdev_init(acpi_handle handle, u32 depth, void *context, void **ret)
-{
-	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	u64 addr;
-	struct hubdev_info *hubdev;
-	struct hubdev_info *hubdev_ptr;
-	int i;
-	u64 nasid;
-	struct acpi_resource *resource;
-	acpi_status status;
-	struct acpi_resource_vendor_typed *vendor;
-	extern void sn_common_hubdev_init(struct hubdev_info *);
-
-	status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS,
-					  &sn_uuid, &buffer);
-	if (ACPI_FAILURE(status)) {
-		acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
-		printk(KERN_ERR
-		       "sn_acpi_hubdev_init: acpi_get_vendor_resource() "
-		       "(0x%x) failed for: %s\n", status,
-			(char *)name_buffer.pointer);
-		kfree(name_buffer.pointer);
-		return AE_OK;		/* Continue walking namespace */
-	}
-
-	resource = buffer.pointer;
-	vendor = &resource->data.vendor_typed;
-	if ((vendor->byte_length - sizeof(struct acpi_vendor_uuid)) !=
-	    sizeof(struct hubdev_info *)) {
-		acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
-		printk(KERN_ERR
-		       "sn_acpi_hubdev_init: Invalid vendor data length: "
-		       "%d for: %s\n",
-			vendor->byte_length, (char *)name_buffer.pointer);
-		kfree(name_buffer.pointer);
-		goto exit;
-	}
-
-	memcpy(&addr, vendor->byte_data, sizeof(struct hubdev_info *));
-	hubdev_ptr = __va((struct hubdev_info *) addr);
-
-	nasid = hubdev_ptr->hdi_nasid;
-	i = nasid_to_cnodeid(nasid);
-	hubdev = (struct hubdev_info *)(NODEPDA(i)->pdinfo);
-	*hubdev = *hubdev_ptr;
-	sn_common_hubdev_init(hubdev);
-
-exit:
-	kfree(buffer.pointer);
-	return AE_OK;		/* Continue walking namespace */
-}
-
-/*
- * sn_get_bussoft_ptr() - The pcibus_bussoft pointer is found in
- *			  the ACPI Vendor resource for this bus.
- */
-static struct pcibus_bussoft *
-sn_get_bussoft_ptr(struct pci_bus *bus)
-{
-	u64 addr;
-	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	acpi_handle handle;
-	struct pcibus_bussoft *prom_bussoft_ptr;
-	struct acpi_resource *resource;
-	acpi_status status;
-	struct acpi_resource_vendor_typed *vendor;
-
-
-	handle = acpi_device_handle(PCI_CONTROLLER(bus)->companion);
-	status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS,
-					  &sn_uuid, &buffer);
-	if (ACPI_FAILURE(status)) {
-		acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
-		printk(KERN_ERR "%s: "
-		       "acpi_get_vendor_resource() failed (0x%x) for: %s\n",
-		       __func__, status, (char *)name_buffer.pointer);
-		kfree(name_buffer.pointer);
-		return NULL;
-	}
-	resource = buffer.pointer;
-	vendor = &resource->data.vendor_typed;
-
-	if ((vendor->byte_length - sizeof(struct acpi_vendor_uuid)) !=
-	     sizeof(struct pcibus_bussoft *)) {
-		printk(KERN_ERR
-		       "%s: Invalid vendor data length %d\n",
-			__func__, vendor->byte_length);
-		kfree(buffer.pointer);
-		return NULL;
-	}
-	memcpy(&addr, vendor->byte_data, sizeof(struct pcibus_bussoft *));
-	prom_bussoft_ptr = __va((struct pcibus_bussoft *) addr);
-	kfree(buffer.pointer);
-
-	return prom_bussoft_ptr;
-}
-
-/*
- * sn_extract_device_info - Extract the pcidev_info and the sn_irq_info
- *			    pointers from the vendor resource using the
- *			    provided acpi handle, and copy the structures
- *			    into the argument buffers.
- */
-static int
-sn_extract_device_info(acpi_handle handle, struct pcidev_info **pcidev_info,
-		    struct sn_irq_info **sn_irq_info)
-{
-	u64 addr;
-	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	struct sn_irq_info *irq_info, *irq_info_prom;
-	struct pcidev_info *pcidev_ptr, *pcidev_prom_ptr;
-	struct acpi_resource *resource;
-	int ret = 0;
-	acpi_status status;
-	struct acpi_resource_vendor_typed *vendor;
-
-	/*
-	 * The pointer to this device's pcidev_info structure in
-	 * the PROM, is in the vendor resource.
-	 */
-	status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS,
-					  &sn_uuid, &buffer);
-	if (ACPI_FAILURE(status)) {
-		acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
-		printk(KERN_ERR
-		       "%s: acpi_get_vendor_resource() failed (0x%x) for: %s\n",
-			__func__, status, (char *)name_buffer.pointer);
-		kfree(name_buffer.pointer);
-		return 1;
-	}
-
-	resource = buffer.pointer;
-	vendor = &resource->data.vendor_typed;
-	if ((vendor->byte_length - sizeof(struct acpi_vendor_uuid)) !=
-	    sizeof(struct pci_devdev_info *)) {
-		acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
-		printk(KERN_ERR
-		       "%s: Invalid vendor data length: %d for: %s\n",
-			 __func__, vendor->byte_length,
-			(char *)name_buffer.pointer);
-		kfree(name_buffer.pointer);
-		ret = 1;
-		goto exit;
-	}
-
-	pcidev_ptr = kzalloc(sizeof(struct pcidev_info), GFP_KERNEL);
-	if (!pcidev_ptr)
-		panic("%s: Unable to alloc memory for pcidev_info", __func__);
-
-	memcpy(&addr, vendor->byte_data, sizeof(struct pcidev_info *));
-	pcidev_prom_ptr = __va(addr);
-	memcpy(pcidev_ptr, pcidev_prom_ptr, sizeof(struct pcidev_info));
-
-	/* Get the IRQ info */
-	irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
-	if (!irq_info)
-		 panic("%s: Unable to alloc memory for sn_irq_info", __func__);
-
-	if (pcidev_ptr->pdi_sn_irq_info) {
-		irq_info_prom = __va(pcidev_ptr->pdi_sn_irq_info);
-		memcpy(irq_info, irq_info_prom, sizeof(struct sn_irq_info));
-	}
-
-	*pcidev_info = pcidev_ptr;
-	*sn_irq_info = irq_info;
-
-exit:
-	kfree(buffer.pointer);
-	return ret;
-}
-
-static unsigned int
-get_host_devfn(acpi_handle device_handle, acpi_handle rootbus_handle)
-{
-	unsigned long long adr;
-	acpi_handle child;
-	unsigned int devfn;
-	int function;
-	acpi_handle parent;
-	int slot;
-	acpi_status status;
-	struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-
-	acpi_get_name(device_handle, ACPI_FULL_PATHNAME, &name_buffer);
-
-	/*
-	 * Do an upward search to find the root bus device, and
-	 * obtain the host devfn from the previous child device.
-	 */
-	child = device_handle;
-	while (child) {
-		status = acpi_get_parent(child, &parent);
-		if (ACPI_FAILURE(status)) {
-			printk(KERN_ERR "%s: acpi_get_parent() failed "
-			       "(0x%x) for: %s\n", __func__, status,
-				(char *)name_buffer.pointer);
-			panic("%s: Unable to find host devfn\n", __func__);
-		}
-		if (parent == rootbus_handle)
-			break;
-		child = parent;
-	}
-	if (!child) {
-		printk(KERN_ERR "%s: Unable to find root bus for: %s\n",
-		       __func__, (char *)name_buffer.pointer);
-		BUG();
-	}
-
-	status = acpi_evaluate_integer(child, METHOD_NAME__ADR, NULL, &adr);
-	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR "%s: Unable to get _ADR (0x%x) for: %s\n",
-		       __func__, status, (char *)name_buffer.pointer);
-		panic("%s: Unable to find host devfn\n", __func__);
-	}
-
-	kfree(name_buffer.pointer);
-
-	slot = (adr >> 16) & 0xffff;
-	function = adr & 0xffff;
-	devfn = PCI_DEVFN(slot, function);
-	return devfn;
-}
-
-/*
- * find_matching_device - Callback routine to find the ACPI device
- *			  that matches up with our pci_dev device.
- *			  Matching is done on bus number and devfn.
- *			  To find the bus number for a particular
- *			  ACPI device, we must look at the _BBN method
- *			  of its parent.
- */
-static acpi_status
-find_matching_device(acpi_handle handle, u32 lvl, void *context, void **rv)
-{
-	unsigned long long bbn = -1;
-	unsigned long long adr;
-	acpi_handle parent = NULL;
-	acpi_status status;
-	unsigned int devfn;
-	int function;
-	int slot;
-	struct sn_pcidev_match *info = context;
-	struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-
-        status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL,
-                                       &adr);
-        if (ACPI_SUCCESS(status)) {
-		status = acpi_get_parent(handle, &parent);
-		if (ACPI_FAILURE(status)) {
-			acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
-			printk(KERN_ERR
-			       "%s: acpi_get_parent() failed (0x%x) for: %s\n",
-				__func__, status, (char *)name_buffer.pointer);
-			kfree(name_buffer.pointer);
-			return AE_OK;
-		}
-		status = acpi_evaluate_integer(parent, METHOD_NAME__BBN,
-					       NULL, &bbn);
-		if (ACPI_FAILURE(status)) {
-			acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
-			printk(KERN_ERR
-			  "%s: Failed to find _BBN in parent of: %s\n",
-					__func__, (char *)name_buffer.pointer);
-			kfree(name_buffer.pointer);
-			return AE_OK;
-		}
-
-                slot = (adr >> 16) & 0xffff;
-                function = adr & 0xffff;
-                devfn = PCI_DEVFN(slot, function);
-                if ((info->devfn == devfn) && (info->bus == bbn)) {
-			/* We have a match! */
-			info->handle = handle;
-			return 1;
-		}
-	}
-	return AE_OK;
-}
-
-/*
- * sn_acpi_get_pcidev_info - Search ACPI namespace for the acpi
- *			     device matching the specified pci_dev,
- *			     and return the pcidev info and irq info.
- */
-int
-sn_acpi_get_pcidev_info(struct pci_dev *dev, struct pcidev_info **pcidev_info,
-			struct sn_irq_info **sn_irq_info)
-{
-	unsigned int host_devfn;
-	struct sn_pcidev_match pcidev_match;
-	acpi_handle rootbus_handle;
-	unsigned long long segment;
-	acpi_status status;
-	struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-
-	rootbus_handle = acpi_device_handle(PCI_CONTROLLER(dev)->companion);
-        status = acpi_evaluate_integer(rootbus_handle, METHOD_NAME__SEG, NULL,
-                                       &segment);
-        if (ACPI_SUCCESS(status)) {
-		if (segment != pci_domain_nr(dev)) {
-			acpi_get_name(rootbus_handle, ACPI_FULL_PATHNAME,
-				&name_buffer);
-			printk(KERN_ERR
-			       "%s: Segment number mismatch, 0x%llx vs 0x%x for: %s\n",
-			       __func__, segment, pci_domain_nr(dev),
-			       (char *)name_buffer.pointer);
-			kfree(name_buffer.pointer);
-			return 1;
-		}
-	} else {
-		acpi_get_name(rootbus_handle, ACPI_FULL_PATHNAME, &name_buffer);
-		printk(KERN_ERR "%s: Unable to get __SEG from: %s\n",
-		       __func__, (char *)name_buffer.pointer);
-		kfree(name_buffer.pointer);
-		return 1;
-	}
-
-	/*
-	 * We want to search all devices in this segment/domain
-	 * of the ACPI namespace for the matching ACPI device,
-	 * which holds the pcidev_info pointer in its vendor resource.
-	 */
-	pcidev_match.bus = dev->bus->number;
-	pcidev_match.devfn = dev->devfn;
-	pcidev_match.handle = NULL;
-
-	acpi_walk_namespace(ACPI_TYPE_DEVICE, rootbus_handle, ACPI_UINT32_MAX,
-			    find_matching_device, NULL, &pcidev_match, NULL);
-
-	if (!pcidev_match.handle) {
-		printk(KERN_ERR
-		       "%s: Could not find matching ACPI device for %s.\n",
-		       __func__, pci_name(dev));
-		return 1;
-	}
-
-	if (sn_extract_device_info(pcidev_match.handle, pcidev_info, sn_irq_info))
-		return 1;
-
-	/* Build up the pcidev_info.pdi_slot_host_handle */
-	host_devfn = get_host_devfn(pcidev_match.handle, rootbus_handle);
-	(*pcidev_info)->pdi_slot_host_handle =
-			((unsigned long) pci_domain_nr(dev) << 40) |
-					/* bus == 0 */
-					host_devfn;
-	return 0;
-}
-
-/*
- * sn_acpi_slot_fixup - Obtain the pcidev_info and sn_irq_info.
- *			Perform any SN specific slot fixup.
- *			At present there does not appear to be
- *			any generic way to handle a ROM image
- *			that has been shadowed by the PROM, so
- *			we pass a pointer to it	within the
- *			pcidev_info structure.
- */
-
-void
-sn_acpi_slot_fixup(struct pci_dev *dev)
-{
-	struct pcidev_info *pcidev_info = NULL;
-	struct sn_irq_info *sn_irq_info = NULL;
-	struct resource *res;
-	size_t size;
-
-	if (sn_acpi_get_pcidev_info(dev, &pcidev_info, &sn_irq_info)) {
-		panic("%s:  Failure obtaining pcidev_info for %s\n",
-		      __func__, pci_name(dev));
-	}
-
-	if (pcidev_info->pdi_pio_mapped_addr[PCI_ROM_RESOURCE]) {
-		/*
-		 * A valid ROM image exists and has been shadowed by the
-		 * PROM. Setup the pci_dev ROM resource with the address
-		 * of the shadowed copy, and the actual length of the ROM image.
-		 */
-		size = pci_resource_len(dev, PCI_ROM_RESOURCE);
-
-		res = &dev->resource[PCI_ROM_RESOURCE];
-
-		pci_disable_rom(dev);
-		if (res->parent)
-			release_resource(res);
-
-		res->start = pcidev_info->pdi_pio_mapped_addr[PCI_ROM_RESOURCE];
-		res->end = res->start + size - 1;
-		res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
-			     IORESOURCE_PCI_FIXED;
-	}
-	sn_pci_fixup_slot(dev, pcidev_info, sn_irq_info);
-}
-EXPORT_SYMBOL(sn_acpi_slot_fixup);
-
-
-/*
- * sn_acpi_bus_fixup -  Perform SN specific setup of software structs
- *			(pcibus_bussoft, pcidev_info) and hardware
- *			registers, for the specified bus and devices under it.
- */
-void
-sn_acpi_bus_fixup(struct pci_bus *bus)
-{
-	struct pci_dev *pci_dev = NULL;
-	struct pcibus_bussoft *prom_bussoft_ptr;
-
-	if (!bus->parent) {	/* If root bus */
-		prom_bussoft_ptr = sn_get_bussoft_ptr(bus);
-		if (prom_bussoft_ptr == NULL) {
-			printk(KERN_ERR
-			       "%s: 0x%04x:0x%02x Unable to "
-			       "obtain prom_bussoft_ptr\n",
-			       __func__, pci_domain_nr(bus), bus->number);
-			return;
-		}
-		sn_common_bus_fixup(bus, prom_bussoft_ptr);
-	}
-	list_for_each_entry(pci_dev, &bus->devices, bus_list) {
-		sn_acpi_slot_fixup(pci_dev);
-	}
-}
-
-/*
- * sn_io_acpi_init - PROM has ACPI support for IO, defining at a minimum the
- *		     nodes and root buses in the DSDT. As a result, bus scanning
- *		     will be initiated by the Linux ACPI code.
- */
-
-void __init
-sn_io_acpi_init(void)
-{
-	u64 result;
-	long status;
-
-	/* SN Altix does not follow the IOSAPIC IRQ routing model */
-	acpi_irq_model = ACPI_IRQ_MODEL_PLATFORM;
-
-	/* Setup hubdev_info for all SGIHUB/SGITIO devices */
-	acpi_get_devices("SGIHUB", sn_acpi_hubdev_init, NULL, NULL);
-	acpi_get_devices("SGITIO", sn_acpi_hubdev_init, NULL, NULL);
-
-	status = sal_ioif_init(&result);
-	if (status || result)
-		panic("sal_ioif_init failed: [%lx] %s\n",
-		      status, ia64_sal_strerror(status));
-}
diff --git a/arch/ia64/sn/kernel/io_common.c b/arch/ia64/sn/kernel/io_common.c
deleted file mode 100644
index d46847323ef6..000000000000
--- a/arch/ia64/sn/kernel/io_common.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/memblock.h>
-#include <linux/export.h>
-#include <linux/slab.h>
-#include <asm/sn/types.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/sn_feature_sets.h>
-#include <asm/sn/geo.h>
-#include <asm/sn/io.h>
-#include <asm/sn/l1.h>
-#include <asm/sn/module.h>
-#include <asm/sn/pcibr_provider.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/simulator.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/tioca_provider.h>
-#include <asm/sn/tioce_provider.h>
-#include "xtalk/hubdev.h"
-#include "xtalk/xwidgetdev.h"
-#include <linux/acpi.h>
-#include <asm/sn/sn2/sn_hwperf.h>
-#include <asm/sn/acpi.h>
-
-extern void sn_init_cpei_timer(void);
-extern void register_sn_procfs(void);
-extern void sn_io_acpi_init(void);
-extern void sn_io_init(void);
-
-
-static struct list_head sn_sysdata_list;
-
-/* sysdata list struct */
-struct sysdata_el {
-	struct list_head entry;
-	void *sysdata;
-};
-
-int sn_ioif_inited;		/* SN I/O infrastructure initialized? */
-
-int sn_acpi_rev;		/* SN ACPI revision */
-EXPORT_SYMBOL_GPL(sn_acpi_rev);
-
-struct sn_pcibus_provider *sn_pci_provider[PCIIO_ASIC_MAX_TYPES];	/* indexed by asic type */
-
-/*
- * Hooks and struct for unsupported pci providers
- */
-
-static dma_addr_t
-sn_default_pci_map(struct pci_dev *pdev, unsigned long paddr, size_t size, int type)
-{
-	return 0;
-}
-
-static void
-sn_default_pci_unmap(struct pci_dev *pdev, dma_addr_t addr, int direction)
-{
-	return;
-}
-
-static void *
-sn_default_pci_bus_fixup(struct pcibus_bussoft *soft, struct pci_controller *controller)
-{
-	return NULL;
-}
-
-static struct sn_pcibus_provider sn_pci_default_provider = {
-	.dma_map = sn_default_pci_map,
-	.dma_map_consistent = sn_default_pci_map,
-	.dma_unmap = sn_default_pci_unmap,
-	.bus_fixup = sn_default_pci_bus_fixup,
-};
-
-/*
- * Retrieve the DMA Flush List given nasid, widget, and device.
- * This list is needed to implement the WAR - Flush DMA data on PIO Reads.
- */
-static inline u64
-sal_get_device_dmaflush_list(u64 nasid, u64 widget_num, u64 device_num,
-			     u64 address)
-{
-	struct ia64_sal_retval ret_stuff;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	SAL_CALL_NOLOCK(ret_stuff,
-			(u64) SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST,
-			(u64) nasid, (u64) widget_num,
-			(u64) device_num, (u64) address, 0, 0, 0);
-	return ret_stuff.status;
-}
-
-/*
- * sn_pcidev_info_get() - Retrieve the pcidev_info struct for the specified
- *			  device.
- */
-inline struct pcidev_info *
-sn_pcidev_info_get(struct pci_dev *dev)
-{
-	struct pcidev_info *pcidev;
-
-	list_for_each_entry(pcidev,
-			    &(SN_PLATFORM_DATA(dev)->pcidev_info), pdi_list) {
-		if (pcidev->pdi_linux_pcidev == dev)
-			return pcidev;
-	}
-	return NULL;
-}
-
-/* Older PROM flush WAR
- *
- * 01/16/06 -- This war will be in place until a new official PROM is released.
- * Additionally note that the struct sn_flush_device_war also has to be
- * removed from arch/ia64/sn/include/xtalk/hubdev.h
- */
-
-static s64 sn_device_fixup_war(u64 nasid, u64 widget, int device,
-			       struct sn_flush_device_common *common)
-{
-	struct sn_flush_device_war *war_list;
-	struct sn_flush_device_war *dev_entry;
-	struct ia64_sal_retval isrv = {0,0,0,0};
-
-	printk_once(KERN_WARNING
-		"PROM version < 4.50 -- implementing old PROM flush WAR\n");
-
-	war_list = kcalloc(DEV_PER_WIDGET, sizeof(*war_list), GFP_KERNEL);
-	BUG_ON(!war_list);
-
-	SAL_CALL_NOLOCK(isrv, SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST,
-			nasid, widget, __pa(war_list), 0, 0, 0 ,0);
-	if (isrv.status)
-		panic("sn_device_fixup_war failed: %s\n",
-		      ia64_sal_strerror(isrv.status));
-
-	dev_entry = war_list + device;
-	memcpy(common,dev_entry, sizeof(*common));
-	kfree(war_list);
-
-	return isrv.status;
-}
-
-/*
- * sn_common_hubdev_init() - This routine is called to initialize the HUB data
- *			     structure for each node in the system.
- */
-void __init
-sn_common_hubdev_init(struct hubdev_info *hubdev)
-{
-
-	struct sn_flush_device_kernel *sn_flush_device_kernel;
-	struct sn_flush_device_kernel *dev_entry;
-	s64 status;
-	int widget, device, size;
-
-	/* Attach the error interrupt handlers */
-	if (hubdev->hdi_nasid & 1)	/* If TIO */
-		ice_error_init(hubdev);
-	else
-		hub_error_init(hubdev);
-
-	for (widget = 0; widget <= HUB_WIDGET_ID_MAX; widget++)
-		hubdev->hdi_xwidget_info[widget].xwi_hubinfo = hubdev;
-
-	if (!hubdev->hdi_flush_nasid_list.widget_p)
-		return;
-
-	size = (HUB_WIDGET_ID_MAX + 1) *
-		sizeof(struct sn_flush_device_kernel *);
-	hubdev->hdi_flush_nasid_list.widget_p =
-		kzalloc(size, GFP_KERNEL);
-	BUG_ON(!hubdev->hdi_flush_nasid_list.widget_p);
-
-	for (widget = 0; widget <= HUB_WIDGET_ID_MAX; widget++) {
-		size = DEV_PER_WIDGET *
-			sizeof(struct sn_flush_device_kernel);
-		sn_flush_device_kernel = kzalloc(size, GFP_KERNEL);
-		BUG_ON(!sn_flush_device_kernel);
-
-		dev_entry = sn_flush_device_kernel;
-		for (device = 0; device < DEV_PER_WIDGET;
-		     device++, dev_entry++) {
-			size = sizeof(struct sn_flush_device_common);
-			dev_entry->common = kzalloc(size, GFP_KERNEL);
-			BUG_ON(!dev_entry->common);
-			if (sn_prom_feature_available(PRF_DEVICE_FLUSH_LIST))
-				status = sal_get_device_dmaflush_list(
-					     hubdev->hdi_nasid, widget, device,
-					     (u64)(dev_entry->common));
-			else
-				status = sn_device_fixup_war(hubdev->hdi_nasid,
-							     widget, device,
-							     dev_entry->common);
-			if (status != SALRET_OK)
-				panic("SAL call failed: %s\n",
-				      ia64_sal_strerror(status));
-
-			spin_lock_init(&dev_entry->sfdl_flush_lock);
-		}
-
-		if (sn_flush_device_kernel)
-			hubdev->hdi_flush_nasid_list.widget_p[widget] =
-							 sn_flush_device_kernel;
-	}
-}
-
-void sn_pci_unfixup_slot(struct pci_dev *dev)
-{
-	struct pci_dev *host_pci_dev = SN_PCIDEV_INFO(dev)->host_pci_dev;
-
-	sn_irq_unfixup(dev);
-	pci_dev_put(host_pci_dev);
-	pci_dev_put(dev);
-}
-
-/*
- * sn_pci_fixup_slot()
- */
-void sn_pci_fixup_slot(struct pci_dev *dev, struct pcidev_info *pcidev_info,
-		       struct sn_irq_info *sn_irq_info)
-{
-	int segment = pci_domain_nr(dev->bus);
-	struct pcibus_bussoft *bs;
-	struct pci_dev *host_pci_dev;
-	unsigned int bus_no, devfn;
-
-	pci_dev_get(dev); /* for the sysdata pointer */
-
-	/* Add pcidev_info to list in pci_controller.platform_data */
-	list_add_tail(&pcidev_info->pdi_list,
-		      &(SN_PLATFORM_DATA(dev->bus)->pcidev_info));
-	/*
-	 * Using the PROMs values for the PCI host bus, get the Linux
-	 * PCI host_pci_dev struct and set up host bus linkages
- 	 */
-
-	bus_no = (pcidev_info->pdi_slot_host_handle >> 32) & 0xff;
-	devfn = pcidev_info->pdi_slot_host_handle & 0xffffffff;
-	host_pci_dev = pci_get_domain_bus_and_slot(segment, bus_no, devfn);
-
-	pcidev_info->host_pci_dev = host_pci_dev;
-	pcidev_info->pdi_linux_pcidev = dev;
-	pcidev_info->pdi_host_pcidev_info = SN_PCIDEV_INFO(host_pci_dev);
-	bs = SN_PCIBUS_BUSSOFT(dev->bus);
-	pcidev_info->pdi_pcibus_info = bs;
-
-	if (bs && bs->bs_asic_type < PCIIO_ASIC_MAX_TYPES) {
-		SN_PCIDEV_BUSPROVIDER(dev) = sn_pci_provider[bs->bs_asic_type];
-	} else {
-		SN_PCIDEV_BUSPROVIDER(dev) = &sn_pci_default_provider;
-	}
-
-	/* Only set up IRQ stuff if this device has a host bus context */
-	if (bs && sn_irq_info->irq_irq) {
-		pcidev_info->pdi_sn_irq_info = sn_irq_info;
-		dev->irq = pcidev_info->pdi_sn_irq_info->irq_irq;
-		sn_irq_fixup(dev, sn_irq_info);
-	} else {
-		pcidev_info->pdi_sn_irq_info = NULL;
-		kfree(sn_irq_info);
-	}
-}
-
-/*
- * sn_common_bus_fixup - Perform platform specific bus fixup.
- *			 Execute the ASIC specific fixup routine
- *			 for this bus.
- */
-void
-sn_common_bus_fixup(struct pci_bus *bus,
-		    struct pcibus_bussoft *prom_bussoft_ptr)
-{
-	int cnode;
-	struct pci_controller *controller;
-	struct hubdev_info *hubdev_info;
-	int nasid;
-	void *provider_soft;
-	struct sn_pcibus_provider *provider;
-	struct sn_platform_data *sn_platform_data;
-
-	controller = PCI_CONTROLLER(bus);
-	/*
-	 * Per-provider fixup.  Copies the bus soft structure from prom
-	 * to local area and links SN_PCIBUS_BUSSOFT().
-	 */
-
-	if (prom_bussoft_ptr->bs_asic_type >= PCIIO_ASIC_MAX_TYPES) {
-		printk(KERN_WARNING "sn_common_bus_fixup: Unsupported asic type, %d",
-		       prom_bussoft_ptr->bs_asic_type);
-		return;
-	}
-
-	if (prom_bussoft_ptr->bs_asic_type == PCIIO_ASIC_TYPE_PPB)
-		return;	/* no further fixup necessary */
-
-	provider = sn_pci_provider[prom_bussoft_ptr->bs_asic_type];
-	if (provider == NULL)
-		panic("sn_common_bus_fixup: No provider registered for this asic type, %d",
-		      prom_bussoft_ptr->bs_asic_type);
-
-	if (provider->bus_fixup)
-		provider_soft = (*provider->bus_fixup) (prom_bussoft_ptr,
-				 controller);
-	else
-		provider_soft = NULL;
-
-	/*
-	 * Generic bus fixup goes here.  Don't reference prom_bussoft_ptr
-	 * after this point.
-	 */
-	controller->platform_data = kzalloc(sizeof(struct sn_platform_data),
-					    GFP_KERNEL);
-	BUG_ON(controller->platform_data == NULL);
-	sn_platform_data =
-			(struct sn_platform_data *) controller->platform_data;
-	sn_platform_data->provider_soft = provider_soft;
-	INIT_LIST_HEAD(&((struct sn_platform_data *)
-			 controller->platform_data)->pcidev_info);
-	nasid = NASID_GET(SN_PCIBUS_BUSSOFT(bus)->bs_base);
-	cnode = nasid_to_cnodeid(nasid);
-	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
-	SN_PCIBUS_BUSSOFT(bus)->bs_xwidget_info =
-	    &(hubdev_info->hdi_xwidget_info[SN_PCIBUS_BUSSOFT(bus)->bs_xid]);
-
-	/*
-	 * If the node information we obtained during the fixup phase is
-	 * invalid then set controller->node to -1 (undetermined)
-	 */
-	if (controller->node >= num_online_nodes()) {
-		struct pcibus_bussoft *b = SN_PCIBUS_BUSSOFT(bus);
-
-		printk(KERN_WARNING "Device ASIC=%u XID=%u PBUSNUM=%u "
-		       "L_IO=%llx L_MEM=%llx BASE=%llx\n",
-		       b->bs_asic_type, b->bs_xid, b->bs_persist_busnum,
-		       b->bs_legacy_io, b->bs_legacy_mem, b->bs_base);
-		printk(KERN_WARNING "on node %d but only %d nodes online."
-		       "Association set to undetermined.\n",
-		       controller->node, num_online_nodes());
-		controller->node = -1;
-	}
-}
-
-void sn_bus_store_sysdata(struct pci_dev *dev)
-{
-	struct sysdata_el *element;
-
-	element = kzalloc(sizeof(struct sysdata_el), GFP_KERNEL);
-	if (!element) {
-		dev_dbg(&dev->dev, "%s: out of memory!\n", __func__);
-		return;
-	}
-	element->sysdata = SN_PCIDEV_INFO(dev);
-	list_add(&element->entry, &sn_sysdata_list);
-}
-
-void sn_bus_free_sysdata(void)
-{
-	struct sysdata_el *element;
-	struct list_head *list, *safe;
-
-	list_for_each_safe(list, safe, &sn_sysdata_list) {
-		element = list_entry(list, struct sysdata_el, entry);
-		list_del(&element->entry);
-		list_del(&(((struct pcidev_info *)
-			     (element->sysdata))->pdi_list));
-		kfree(element->sysdata);
-		kfree(element);
-	}
-	return;
-}
-
-/*
- * hubdev_init_node() - Creates the HUB data structure and link them to it's
- *			own NODE specific data area.
- */
-void __init hubdev_init_node(nodepda_t * npda, cnodeid_t node)
-{
-	struct hubdev_info *hubdev_info;
-	int size;
-
-	size = sizeof(struct hubdev_info);
-
-	if (node >= num_online_nodes())	/* Headless/memless IO nodes */
-		node = 0;
-
-	hubdev_info = (struct hubdev_info *)memblock_alloc_node(size,
-								SMP_CACHE_BYTES,
-								node);
-	if (!hubdev_info)
-		panic("%s: Failed to allocate %d bytes align=0x%x nid=%d\n",
-		      __func__, size, SMP_CACHE_BYTES, node);
-
-	npda->pdinfo = (void *)hubdev_info;
-}
-
-geoid_t
-cnodeid_get_geoid(cnodeid_t cnode)
-{
-	struct hubdev_info *hubdev;
-
-	hubdev = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
-	return hubdev->hdi_geoid;
-}
-
-void sn_generate_path(struct pci_bus *pci_bus, char *address)
-{
-	nasid_t nasid;
-	cnodeid_t cnode;
-	geoid_t geoid;
-	moduleid_t moduleid;
-	u16 bricktype;
-
-	nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);
-	cnode = nasid_to_cnodeid(nasid);
-	geoid = cnodeid_get_geoid(cnode);
-	moduleid = geo_module(geoid);
-
-	sprintf(address, "module_%c%c%c%c%.2d",
-		'0'+RACK_GET_CLASS(MODULE_GET_RACK(moduleid)),
-		'0'+RACK_GET_GROUP(MODULE_GET_RACK(moduleid)),
-		'0'+RACK_GET_NUM(MODULE_GET_RACK(moduleid)),
-		MODULE_GET_BTCHAR(moduleid), MODULE_GET_BPOS(moduleid));
-
-	/* Tollhouse requires slot id to be displayed */
-	bricktype = MODULE_GET_BTYPE(moduleid);
-	if ((bricktype == L1_BRICKTYPE_191010) ||
-	    (bricktype == L1_BRICKTYPE_1932))
-			sprintf(address + strlen(address), "^%d",
-						geo_slot(geoid));
-}
-
-void sn_pci_fixup_bus(struct pci_bus *bus)
-{
-
-	if (SN_ACPI_BASE_SUPPORT())
-		sn_acpi_bus_fixup(bus);
-	else
-		sn_bus_fixup(bus);
-}
-
-/*
- * sn_io_early_init - Perform early IO (and some non-IO) initialization.
- *		      In particular, setup the sn_pci_provider[] array.
- *		      This needs to be done prior to any bus scanning
- *		      (acpi_scan_init()) in the ACPI case, as the SN
- *		      bus fixup code will reference the array.
- */
-static int __init
-sn_io_early_init(void)
-{
-	int i;
-
-	if (!ia64_platform_is("sn2") || IS_RUNNING_ON_FAKE_PROM())
-		return 0;
-
-	/* we set the acpi revision to that of the DSDT table OEM rev. */
-	{
-		struct acpi_table_header *header = NULL;
-
-		acpi_get_table(ACPI_SIG_DSDT, 1, &header);
-		BUG_ON(header == NULL);
-		sn_acpi_rev = header->oem_revision;
-	}
-
-	/*
-	 * prime sn_pci_provider[].  Individual provider init routines will
-	 * override their respective default entries.
-	 */
-
-	for (i = 0; i < PCIIO_ASIC_MAX_TYPES; i++)
-		sn_pci_provider[i] = &sn_pci_default_provider;
-
-	pcibr_init_provider();
-	tioca_init_provider();
-	tioce_init_provider();
-
-	sn_irq_lh_init();
-	INIT_LIST_HEAD(&sn_sysdata_list);
-	sn_init_cpei_timer();
-
-#ifdef CONFIG_PROC_FS
-	register_sn_procfs();
-#endif
-
-	{
-		struct acpi_table_header *header;
-		(void)acpi_get_table(ACPI_SIG_DSDT, 1, &header);
-		printk(KERN_INFO "ACPI  DSDT OEM Rev 0x%x\n",
-			header->oem_revision);
-	}
-	if (SN_ACPI_BASE_SUPPORT())
-		sn_io_acpi_init();
-	else
-		sn_io_init();
-	return 0;
-}
-
-arch_initcall(sn_io_early_init);
-
-/*
- * sn_io_late_init() - Perform any final platform specific IO initialization.
- */
-
-int __init
-sn_io_late_init(void)
-{
-	struct pci_bus *bus;
-	struct pcibus_bussoft *bussoft;
-	cnodeid_t cnode;
-	nasid_t nasid;
-	cnodeid_t near_cnode;
-
-	if (!ia64_platform_is("sn2") || IS_RUNNING_ON_FAKE_PROM())
-		return 0;
-
-	/*
-	 * Setup closest node in pci_controller->node for
-	 * PIC, TIOCP, TIOCE (TIOCA does it during bus fixup using
-	 * info from the PROM).
-	 */
-	bus = NULL;
-	while ((bus = pci_find_next_bus(bus)) != NULL) {
-		bussoft = SN_PCIBUS_BUSSOFT(bus);
-		nasid = NASID_GET(bussoft->bs_base);
-		cnode = nasid_to_cnodeid(nasid);
-		if ((bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) ||
-		    (bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCE) ||
-		    (bussoft->bs_asic_type == PCIIO_ASIC_TYPE_PIC)) {
-			/* PCI Bridge: find nearest node with CPUs */
-			int e = sn_hwperf_get_nearest_node(cnode, NULL,
-							   &near_cnode);
-			if (e < 0) {
-				near_cnode = (cnodeid_t)-1; /* use any node */
-				printk(KERN_WARNING "sn_io_late_init: failed "
-				       "to find near node with CPUs for "
-				       "node %d, err=%d\n", cnode, e);
-			}
-			PCI_CONTROLLER(bus)->node = near_cnode;
-		}
-	}
-
-	sn_ioif_inited = 1;	/* SN I/O infrastructure now initialized */
-
-	return 0;
-}
-
-fs_initcall(sn_io_late_init);
-
-EXPORT_SYMBOL(sn_pci_unfixup_slot);
-EXPORT_SYMBOL(sn_bus_store_sysdata);
-EXPORT_SYMBOL(sn_bus_free_sysdata);
-EXPORT_SYMBOL(sn_generate_path);
-
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
deleted file mode 100644
index d63809a6adfa..000000000000
--- a/arch/ia64/sn/kernel/io_init.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/slab.h>
-#include <linux/export.h>
-#include <asm/sn/types.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/io.h>
-#include <asm/sn/module.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/sn_sal.h>
-#include "xtalk/hubdev.h"
-
-/*
- * The code in this file will only be executed when running with
- * a PROM that does _not_ have base ACPI IO support.
- * (i.e., SN_ACPI_BASE_SUPPORT() == 0)
- */
-
-static int max_segment_number;		 /* Default highest segment number */
-static int max_pcibus_number = 255;	/* Default highest pci bus number */
-
-
-/*
- * Retrieve the hub device info structure for the given nasid.
- */
-static inline u64 sal_get_hubdev_info(u64 handle, u64 address)
-{
-	struct ia64_sal_retval ret_stuff;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	SAL_CALL_NOLOCK(ret_stuff,
-			(u64) SN_SAL_IOIF_GET_HUBDEV_INFO,
-			(u64) handle, (u64) address, 0, 0, 0, 0, 0);
-	return ret_stuff.v0;
-}
-
-/*
- * Retrieve the pci bus information given the bus number.
- */
-static inline u64 sal_get_pcibus_info(u64 segment, u64 busnum, u64 address)
-{
-	struct ia64_sal_retval ret_stuff;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	SAL_CALL_NOLOCK(ret_stuff,
-			(u64) SN_SAL_IOIF_GET_PCIBUS_INFO,
-			(u64) segment, (u64) busnum, (u64) address, 0, 0, 0, 0);
-	return ret_stuff.v0;
-}
-
-/*
- * Retrieve the pci device information given the bus and device|function number.
- */
-static inline u64
-sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
-		    u64 sn_irq_info)
-{
-	struct ia64_sal_retval ret_stuff;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	SAL_CALL_NOLOCK(ret_stuff,
-			(u64) SN_SAL_IOIF_GET_PCIDEV_INFO,
-			(u64) segment, (u64) bus_number, (u64) devfn,
-			(u64) pci_dev,
-			sn_irq_info, 0, 0);
-	return ret_stuff.v0;
-}
-
-
-/*
- * sn_fixup_ionodes() - This routine initializes the HUB data structure for
- *			each node in the system. This function is only
- *			executed when running with a non-ACPI capable PROM.
- */
-static void __init sn_fixup_ionodes(void)
-{
-
-	struct hubdev_info *hubdev;
-	u64 status;
-	u64 nasid;
-	int i;
-	extern void sn_common_hubdev_init(struct hubdev_info *);
-
-	/*
-	 * Get SGI Specific HUB chipset information.
-	 * Inform Prom that this kernel can support domain bus numbering.
-	 */
-	for (i = 0; i < num_cnodes; i++) {
-		hubdev = (struct hubdev_info *)(NODEPDA(i)->pdinfo);
-		nasid = cnodeid_to_nasid(i);
-		hubdev->max_segment_number = 0xffffffff;
-		hubdev->max_pcibus_number = 0xff;
-		status = sal_get_hubdev_info(nasid, (u64) __pa(hubdev));
-		if (status)
-			continue;
-
-		/* Save the largest Domain and pcibus numbers found. */
-		if (hubdev->max_segment_number) {
-			/*
-			 * Dealing with a Prom that supports segments.
-			 */
-			max_segment_number = hubdev->max_segment_number;
-			max_pcibus_number = hubdev->max_pcibus_number;
-		}
-		sn_common_hubdev_init(hubdev);
-	}
-}
-
-/*
- * sn_pci_legacy_window_fixup - Setup PCI resources for
- *				legacy IO and MEM space. This needs to
- *				be done here, as the PROM does not have
- *				ACPI support defining the root buses
- *				and their resources (_CRS),
- */
-static void
-sn_legacy_pci_window_fixup(struct resource *res,
-		u64 legacy_io, u64 legacy_mem)
-{
-		res[0].name = "legacy_io";
-		res[0].flags = IORESOURCE_IO;
-		res[0].start = legacy_io;
-		res[0].end = res[0].start + 0xffff;
-		res[0].parent = &ioport_resource;
-		res[1].name = "legacy_mem";
-		res[1].flags = IORESOURCE_MEM;
-		res[1].start = legacy_mem;
-		res[1].end = res[1].start + (1024 * 1024) - 1;
-		res[1].parent = &iomem_resource;
-}
-
-/*
- * sn_io_slot_fixup() -   We are not running with an ACPI capable PROM,
- *			  and need to convert the pci_dev->resource
- *			  'start' and 'end' addresses to mapped addresses,
- *			  and setup the pci_controller->window array entries.
- */
-void
-sn_io_slot_fixup(struct pci_dev *dev)
-{
-	int idx;
-	struct resource *res;
-	unsigned long size;
-	struct pcidev_info *pcidev_info;
-	struct sn_irq_info *sn_irq_info;
-	int status;
-
-	pcidev_info = kzalloc(sizeof(struct pcidev_info), GFP_KERNEL);
-	if (!pcidev_info)
-		panic("%s: Unable to alloc memory for pcidev_info", __func__);
-
-	sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
-	if (!sn_irq_info)
-		panic("%s: Unable to alloc memory for sn_irq_info", __func__);
-
-	/* Call to retrieve pci device information needed by kernel. */
-	status = sal_get_pcidev_info((u64) pci_domain_nr(dev),
-		(u64) dev->bus->number,
-		dev->devfn,
-		(u64) __pa(pcidev_info),
-		(u64) __pa(sn_irq_info));
-
-	BUG_ON(status); /* Cannot get platform pci device information */
-
-
-	/* Copy over PIO Mapped Addresses */
-	for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
-		if (!pcidev_info->pdi_pio_mapped_addr[idx])
-			continue;
-
-		res = &dev->resource[idx];
-
-		size = res->end - res->start;
-		if (size == 0)
-			continue;
-
-		res->start = pcidev_info->pdi_pio_mapped_addr[idx];
-		res->end = res->start + size;
-
-		/*
-		 * if it's already in the device structure, remove it before
-		 * inserting
-		 */
-		if (res->parent && res->parent->child)
-			release_resource(res);
-
-		if (res->flags & IORESOURCE_IO)
-			insert_resource(&ioport_resource, res);
-		else
-			insert_resource(&iomem_resource, res);
-		/*
-		 * If ROM, mark as shadowed in PROM.
-		 */
-		if (idx == PCI_ROM_RESOURCE) {
-			pci_disable_rom(dev);
-			res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
-				     IORESOURCE_PCI_FIXED;
-		}
-	}
-
-	sn_pci_fixup_slot(dev, pcidev_info, sn_irq_info);
-}
-EXPORT_SYMBOL(sn_io_slot_fixup);
-
-/*
- * sn_pci_controller_fixup() - This routine sets up a bus's resources
- *			       consistent with the Linux PCI abstraction layer.
- */
-static void __init
-sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
-{
-	s64 status = 0;
-	struct pci_controller *controller;
-	struct pcibus_bussoft *prom_bussoft_ptr;
-	struct resource *res;
-	LIST_HEAD(resources);
-
- 	status = sal_get_pcibus_info((u64) segment, (u64) busnum,
- 				     (u64) ia64_tpa(&prom_bussoft_ptr));
- 	if (status > 0)
-		return;		/*bus # does not exist */
-	prom_bussoft_ptr = __va(prom_bussoft_ptr);
-
-	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
-	BUG_ON(!controller);
-	controller->segment = segment;
-
-	res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
-	BUG_ON(!res);
-
-	/*
-	 * Temporarily save the prom_bussoft_ptr for use by sn_bus_fixup().
-	 * (platform_data will be overwritten later in sn_common_bus_fixup())
-	 */
-	controller->platform_data = prom_bussoft_ptr;
-
-	sn_legacy_pci_window_fixup(res,
-			prom_bussoft_ptr->bs_legacy_io,
-			prom_bussoft_ptr->bs_legacy_mem);
-	pci_add_resource_offset(&resources,	&res[0],
-			prom_bussoft_ptr->bs_legacy_io);
-	pci_add_resource_offset(&resources,	&res[1],
-			prom_bussoft_ptr->bs_legacy_mem);
-
-	bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, controller,
-				&resources);
- 	if (bus == NULL) {
-		kfree(res);
-		kfree(controller);
-		return;
-	}
-	pci_bus_add_devices(bus);
-}
-
-/*
- * sn_bus_fixup
- */
-void
-sn_bus_fixup(struct pci_bus *bus)
-{
-	struct pci_dev *pci_dev = NULL;
-	struct pcibus_bussoft *prom_bussoft_ptr;
-
-	if (!bus->parent) {  /* If root bus */
-		prom_bussoft_ptr = PCI_CONTROLLER(bus)->platform_data;
-		if (prom_bussoft_ptr == NULL) {
-			printk(KERN_ERR
-			       "sn_bus_fixup: 0x%04x:0x%02x Unable to "
-			       "obtain prom_bussoft_ptr\n",
-			       pci_domain_nr(bus), bus->number);
-			return;
-		}
-		sn_common_bus_fixup(bus, prom_bussoft_ptr);
-        }
-        list_for_each_entry(pci_dev, &bus->devices, bus_list) {
-                sn_io_slot_fixup(pci_dev);
-        }
-
-}
-
-/*
- * sn_io_init - PROM does not have ACPI support to define nodes or root buses,
- *		so we need to do things the hard way, including initiating the
- *		bus scanning ourselves.
- */
-
-void __init sn_io_init(void)
-{
-	int i, j;
-
-	sn_fixup_ionodes();
-
-	/* busses are not known yet ... */
-	for (i = 0; i <= max_segment_number; i++)
-		for (j = 0; j <= max_pcibus_number; j++)
-			sn_pci_controller_fixup(i, j, NULL);
-}
diff --git a/arch/ia64/sn/kernel/iomv.c b/arch/ia64/sn/kernel/iomv.c
deleted file mode 100644
index 2b22a71663c1..000000000000
--- a/arch/ia64/sn/kernel/iomv.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2003, 2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/module.h>
-#include <linux/acpi.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/vga.h>
-#include <asm/sn/nodepda.h>
-#include <asm/sn/simulator.h>
-#include <asm/sn/pda.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/shub_mmr.h>
-#include <asm/sn/acpi.h>
-
-#define IS_LEGACY_VGA_IOPORT(p) \
-	(((p) >= 0x3b0 && (p) <= 0x3bb) || ((p) >= 0x3c0 && (p) <= 0x3df))
-
-/**
- * sn_io_addr - convert an in/out port to an i/o address
- * @port: port to convert
- *
- * Legacy in/out instructions are converted to ld/st instructions
- * on IA64.  This routine will convert a port number into a valid
- * SN i/o address.  Used by sn_in*() and sn_out*().
- */
-
-void *sn_io_addr(unsigned long port)
-{
-	if (!IS_RUNNING_ON_SIMULATOR()) {
-		if (IS_LEGACY_VGA_IOPORT(port))
-			return (__ia64_mk_io_addr(port));
-		/* On sn2, legacy I/O ports don't point at anything */
-		if (port < (64 * 1024))
-			return NULL;
-		if (SN_ACPI_BASE_SUPPORT())
-			return (__ia64_mk_io_addr(port));
-		else
-			return ((void *)(port | __IA64_UNCACHED_OFFSET));
-	} else {
-		/* but the simulator uses them... */
-		unsigned long addr;
-
-		/*
-		 * word align port, but need more than 10 bits
-		 * for accessing registers in bedrock local block
-		 * (so we don't do port&0xfff)
-		 */
-		addr = (is_shub2() ? 0xc00000028c000000UL : 0xc0000087cc000000UL) | ((port >> 2) << 12);
-		if ((port >= 0x1f0 && port <= 0x1f7) || port == 0x3f6 || port == 0x3f7)
-			addr |= port;
-		return (void *)addr;
-	}
-}
-
-EXPORT_SYMBOL(sn_io_addr);
-
-/**
- * __sn_mmiowb - I/O space memory barrier
- *
- * See arch/ia64/include/asm/io.h and Documentation/driver-api/device-io.rst
- * for details.
- *
- * On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear.
- * See PV 871084 for details about the WAR about zero value.
- *
- */
-void __sn_mmiowb(void)
-{
-	volatile unsigned long *adr = pda->pio_write_status_addr;
-	unsigned long val = pda->pio_write_status_val;
-
-	while ((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != val)
-		cpu_relax();
-}
-
-EXPORT_SYMBOL(__sn_mmiowb);
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
deleted file mode 100644
index d9b576df4f82..000000000000
--- a/arch/ia64/sn/kernel/irq.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/*
- * Platform dependent support for SGI SN
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2000-2008 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#include <linux/irq.h>
-#include <linux/spinlock.h>
-#include <linux/init.h>
-#include <linux/rculist.h>
-#include <linux/slab.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/pcibr_provider.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/shub_mmr.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/sn_feature_sets.h>
-
-static void register_intr_pda(struct sn_irq_info *sn_irq_info);
-static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
-
-extern int sn_ioif_inited;
-struct list_head **sn_irq_lh;
-static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
-
-u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
-				     struct sn_irq_info *sn_irq_info,
-				     int req_irq, nasid_t req_nasid,
-				     int req_slice)
-{
-	struct ia64_sal_retval ret_stuff;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
-			(u64) SAL_INTR_ALLOC, (u64) local_nasid,
-			(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
-			(u64) req_nasid, (u64) req_slice);
-
-	return ret_stuff.status;
-}
-
-void sn_intr_free(nasid_t local_nasid, int local_widget,
-				struct sn_irq_info *sn_irq_info)
-{
-	struct ia64_sal_retval ret_stuff;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
-			(u64) SAL_INTR_FREE, (u64) local_nasid,
-			(u64) local_widget, (u64) sn_irq_info->irq_irq,
-			(u64) sn_irq_info->irq_cookie, 0, 0);
-}
-
-u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
-		      struct sn_irq_info *sn_irq_info,
-		      nasid_t req_nasid, int req_slice)
-{
-	struct ia64_sal_retval ret_stuff;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
-			(u64) SAL_INTR_REDIRECT, (u64) local_nasid,
-			(u64) local_widget, __pa(sn_irq_info),
-			(u64) req_nasid, (u64) req_slice, 0);
-
-	return ret_stuff.status;
-}
-
-static unsigned int sn_startup_irq(struct irq_data *data)
-{
-	return 0;
-}
-
-static void sn_shutdown_irq(struct irq_data *data)
-{
-}
-
-extern void ia64_mca_register_cpev(int);
-
-static void sn_disable_irq(struct irq_data *data)
-{
-	if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
-		ia64_mca_register_cpev(0);
-}
-
-static void sn_enable_irq(struct irq_data *data)
-{
-	if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
-		ia64_mca_register_cpev(data->irq);
-}
-
-static void sn_ack_irq(struct irq_data *data)
-{
-	u64 event_occurred, mask;
-	unsigned int irq = data->irq & 0xff;
-
-	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
-	mask = event_occurred & SH_ALL_INT_MASK;
-	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
-	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
-
-	irq_move_irq(data);
-}
-
-struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
-				       nasid_t nasid, int slice)
-{
-	int vector;
-	int cpuid;
-#ifdef CONFIG_SMP
-	int cpuphys;
-#endif
-	int64_t bridge;
-	int local_widget, status;
-	nasid_t local_nasid;
-	struct sn_irq_info *new_irq_info;
-	struct sn_pcibus_provider *pci_provider;
-
-	bridge = (u64) sn_irq_info->irq_bridge;
-	if (!bridge) {
-		return NULL; /* irq is not a device interrupt */
-	}
-
-	local_nasid = NASID_GET(bridge);
-
-	if (local_nasid & 1)
-		local_widget = TIO_SWIN_WIDGETNUM(bridge);
-	else
-		local_widget = SWIN_WIDGETNUM(bridge);
-	vector = sn_irq_info->irq_irq;
-
-	/* Make use of SAL_INTR_REDIRECT if PROM supports it */
-	status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice);
-	if (!status) {
-		new_irq_info = sn_irq_info;
-		goto finish_up;
-	}
-
-	/*
-	 * PROM does not support SAL_INTR_REDIRECT, or it failed.
-	 * Revert to old method.
-	 */
-	new_irq_info = kmemdup(sn_irq_info, sizeof(struct sn_irq_info),
-			       GFP_ATOMIC);
-	if (new_irq_info == NULL)
-		return NULL;
-
-	/* Free the old PROM new_irq_info structure */
-	sn_intr_free(local_nasid, local_widget, new_irq_info);
-	unregister_intr_pda(new_irq_info);
-
-	/* allocate a new PROM new_irq_info struct */
-	status = sn_intr_alloc(local_nasid, local_widget,
-			       new_irq_info, vector,
-			       nasid, slice);
-
-	/* SAL call failed */
-	if (status) {
-		kfree(new_irq_info);
-		return NULL;
-	}
-
-	register_intr_pda(new_irq_info);
-	spin_lock(&sn_irq_info_lock);
-	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
-	spin_unlock(&sn_irq_info_lock);
-	kfree_rcu(sn_irq_info, rcu);
-
-
-finish_up:
-	/* Update kernels new_irq_info with new target info */
-	cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
-				     new_irq_info->irq_slice);
-	new_irq_info->irq_cpuid = cpuid;
-
-	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
-
-	/*
-	 * If this represents a line interrupt, target it.  If it's
-	 * an msi (irq_int_bit < 0), it's already targeted.
-	 */
-	if (new_irq_info->irq_int_bit >= 0 &&
-	    pci_provider && pci_provider->target_interrupt)
-		(pci_provider->target_interrupt)(new_irq_info);
-
-#ifdef CONFIG_SMP
-	cpuphys = cpu_physical_id(cpuid);
-	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
-#endif
-
-	return new_irq_info;
-}
-
-static int sn_set_affinity_irq(struct irq_data *data,
-			       const struct cpumask *mask, bool force)
-{
-	struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
-	unsigned int irq = data->irq;
-	nasid_t nasid;
-	int slice;
-
-	nasid = cpuid_to_nasid(cpumask_first_and(mask, cpu_online_mask));
-	slice = cpuid_to_slice(cpumask_first_and(mask, cpu_online_mask));
-
-	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
-				 sn_irq_lh[irq], list)
-		(void)sn_retarget_vector(sn_irq_info, nasid, slice);
-
-	return 0;
-}
-
-#ifdef CONFIG_SMP
-void sn_set_err_irq_affinity(unsigned int irq)
-{
-        /*
-         * On systems which support CPU disabling (SHub2), all error interrupts
-         * are targeted at the boot CPU.
-         */
-        if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT))
-                set_irq_affinity_info(irq, cpu_physical_id(0), 0);
-}
-#else
-void sn_set_err_irq_affinity(unsigned int irq) { }
-#endif
-
-static void
-sn_mask_irq(struct irq_data *data)
-{
-}
-
-static void
-sn_unmask_irq(struct irq_data *data)
-{
-}
-
-struct irq_chip irq_type_sn = {
-	.name			= "SN hub",
-	.irq_startup		= sn_startup_irq,
-	.irq_shutdown		= sn_shutdown_irq,
-	.irq_enable		= sn_enable_irq,
-	.irq_disable		= sn_disable_irq,
-	.irq_ack		= sn_ack_irq,
-	.irq_mask		= sn_mask_irq,
-	.irq_unmask		= sn_unmask_irq,
-	.irq_set_affinity	= sn_set_affinity_irq
-};
-
-ia64_vector sn_irq_to_vector(int irq)
-{
-	if (irq >= IA64_NUM_VECTORS)
-		return 0;
-	return (ia64_vector)irq;
-}
-
-unsigned int sn_local_vector_to_irq(u8 vector)
-{
-	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
-}
-
-void sn_irq_init(void)
-{
-	int i;
-
-	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
-	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
-
-	for (i = 0; i < NR_IRQS; i++) {
-		if (irq_get_chip(i) == &no_irq_chip)
-			irq_set_chip(i, &irq_type_sn);
-	}
-}
-
-static void register_intr_pda(struct sn_irq_info *sn_irq_info)
-{
-	int irq = sn_irq_info->irq_irq;
-	int cpu = sn_irq_info->irq_cpuid;
-
-	if (pdacpu(cpu)->sn_last_irq < irq) {
-		pdacpu(cpu)->sn_last_irq = irq;
-	}
-
-	if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
-		pdacpu(cpu)->sn_first_irq = irq;
-}
-
-static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
-{
-	int irq = sn_irq_info->irq_irq;
-	int cpu = sn_irq_info->irq_cpuid;
-	struct sn_irq_info *tmp_irq_info;
-	int i, foundmatch;
-
-	rcu_read_lock();
-	if (pdacpu(cpu)->sn_last_irq == irq) {
-		foundmatch = 0;
-		for (i = pdacpu(cpu)->sn_last_irq - 1;
-		     i && !foundmatch; i--) {
-			list_for_each_entry_rcu(tmp_irq_info,
-						sn_irq_lh[i],
-						list) {
-				if (tmp_irq_info->irq_cpuid == cpu) {
-					foundmatch = 1;
-					break;
-				}
-			}
-		}
-		pdacpu(cpu)->sn_last_irq = i;
-	}
-
-	if (pdacpu(cpu)->sn_first_irq == irq) {
-		foundmatch = 0;
-		for (i = pdacpu(cpu)->sn_first_irq + 1;
-		     i < NR_IRQS && !foundmatch; i++) {
-			list_for_each_entry_rcu(tmp_irq_info,
-						sn_irq_lh[i],
-						list) {
-				if (tmp_irq_info->irq_cpuid == cpu) {
-					foundmatch = 1;
-					break;
-				}
-			}
-		}
-		pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
-	}
-	rcu_read_unlock();
-}
-
-void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
-{
-	nasid_t nasid = sn_irq_info->irq_nasid;
-	int slice = sn_irq_info->irq_slice;
-	int cpu = nasid_slice_to_cpuid(nasid, slice);
-#ifdef CONFIG_SMP
-	int cpuphys;
-#endif
-
-	pci_dev_get(pci_dev);
-	sn_irq_info->irq_cpuid = cpu;
-	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
-
-	/* link it into the sn_irq[irq] list */
-	spin_lock(&sn_irq_info_lock);
-	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
-	reserve_irq_vector(sn_irq_info->irq_irq);
-	if (sn_irq_info->irq_int_bit != -1)
-		irq_set_handler(sn_irq_info->irq_irq, handle_level_irq);
-	spin_unlock(&sn_irq_info_lock);
-
-	register_intr_pda(sn_irq_info);
-#ifdef CONFIG_SMP
-	cpuphys = cpu_physical_id(cpu);
-	set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
-	/*
-	 * Affinity was set by the PROM, prevent it from
-	 * being reset by the request_irq() path.
-	 */
-	irqd_mark_affinity_was_set(irq_get_irq_data(sn_irq_info->irq_irq));
-#endif
-}
-
-void sn_irq_unfixup(struct pci_dev *pci_dev)
-{
-	struct sn_irq_info *sn_irq_info;
-
-	/* Only cleanup IRQ stuff if this device has a host bus context */
-	if (!SN_PCIDEV_BUSSOFT(pci_dev))
-		return;
-
-	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
-	if (!sn_irq_info)
-		return;
-	if (!sn_irq_info->irq_irq) {
-		kfree(sn_irq_info);
-		return;
-	}
-
-	unregister_intr_pda(sn_irq_info);
-	spin_lock(&sn_irq_info_lock);
-	list_del_rcu(&sn_irq_info->list);
-	spin_unlock(&sn_irq_info_lock);
-	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
-		free_irq_vector(sn_irq_info->irq_irq);
-	kfree_rcu(sn_irq_info, rcu);
-	pci_dev_put(pci_dev);
-
-}
-
-static inline void
-sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
-{
-	struct sn_pcibus_provider *pci_provider;
-
-	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
-
-	/* Don't force an interrupt if the irq has been disabled */
-	if (!irqd_irq_disabled(irq_get_irq_data(sn_irq_info->irq_irq)) &&
-	    pci_provider && pci_provider->force_interrupt)
-		(*pci_provider->force_interrupt)(sn_irq_info);
-}
-
-/*
- * Check for lost interrupts.  If the PIC int_status reg. says that
- * an interrupt has been sent, but not handled, and the interrupt
- * is not pending in either the cpu irr regs or in the soft irr regs,
- * and the interrupt is not in service, then the interrupt may have
- * been lost.  Force an interrupt on that pin.  It is possible that
- * the interrupt is in flight, so we may generate a spurious interrupt,
- * but we should never miss a real lost interrupt.
- */
-static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
-{
-	u64 regval;
-	struct pcidev_info *pcidev_info;
-	struct pcibus_info *pcibus_info;
-
-	/*
-	 * Bridge types attached to TIO (anything but PIC) do not need this WAR
-	 * since they do not target Shub II interrupt registers.  If that
-	 * ever changes, this check needs to accommodate.
-	 */
-	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
-		return;
-
-	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
-	if (!pcidev_info)
-		return;
-
-	pcibus_info =
-	    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
-	    pdi_pcibus_info;
-	regval = pcireg_intr_status_get(pcibus_info);
-
-	if (!ia64_get_irr(irq_to_vector(irq))) {
-		if (!test_bit(irq, pda->sn_in_service_ivecs)) {
-			regval &= 0xff;
-			if (sn_irq_info->irq_int_bit & regval &
-			    sn_irq_info->irq_last_intr) {
-				regval &= ~(sn_irq_info->irq_int_bit & regval);
-				sn_call_force_intr_provider(sn_irq_info);
-			}
-		}
-	}
-	sn_irq_info->irq_last_intr = regval;
-}
-
-void sn_lb_int_war_check(void)
-{
-	struct sn_irq_info *sn_irq_info;
-	int i;
-
-	if (!sn_ioif_inited || pda->sn_first_irq == 0)
-		return;
-
-	rcu_read_lock();
-	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
-		list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
-			sn_check_intr(i, sn_irq_info);
-		}
-	}
-	rcu_read_unlock();
-}
-
-void __init sn_irq_lh_init(void)
-{
-	int i;
-
-	sn_irq_lh = kmalloc_array(NR_IRQS, sizeof(struct list_head *),
-				  GFP_KERNEL);
-	if (!sn_irq_lh)
-		panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
-
-	for (i = 0; i < NR_IRQS; i++) {
-		sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
-		if (!sn_irq_lh[i])
-			panic("SN PCI INIT: Failed IRQ memory allocation\n");
-
-		INIT_LIST_HEAD(sn_irq_lh[i]);
-	}
-}
diff --git a/arch/ia64/sn/kernel/klconflib.c b/arch/ia64/sn/kernel/klconflib.c
deleted file mode 100644
index 87682b48ef83..000000000000
--- a/arch/ia64/sn/kernel/klconflib.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/types.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <asm/sn/types.h>
-#include <asm/sn/module.h>
-#include <asm/sn/l1.h>
-
-char brick_types[MAX_BRICK_TYPES + 1] = "cri.xdpn%#=vo^kjbf890123456789...";
-/*
- * Format a module id for printing.
- *
- * There are three possible formats:
- *
- *   MODULE_FORMAT_BRIEF	is the brief 6-character format, including
- *				the actual brick-type as recorded in the 
- *				moduleid_t, eg. 002c15 for a C-brick, or
- *				101#17 for a PX-brick.
- *
- *   MODULE_FORMAT_LONG		is the hwgraph format, eg. rack/002/bay/15
- *				of rack/101/bay/17 (note that the brick
- *				type does not appear in this format).
- *
- *   MODULE_FORMAT_LCD		is like MODULE_FORMAT_BRIEF, except that it
- *				ensures that the module id provided appears
- *				exactly as it would on the LCD display of
- *				the corresponding brick, eg. still 002c15
- *				for a C-brick, but 101p17 for a PX-brick.
- *
- * maule (9/13/04):  Removed top-level check for (fmt == MODULE_FORMAT_LCD)
- * making MODULE_FORMAT_LCD equivalent to MODULE_FORMAT_BRIEF.  It was
- * decided that all callers should assume the returned string should be what
- * is displayed on the brick L1 LCD.
- */
-void
-format_module_id(char *buffer, moduleid_t m, int fmt)
-{
-	int rack, position;
-	unsigned char brickchar;
-
-	rack = MODULE_GET_RACK(m);
-	brickchar = MODULE_GET_BTCHAR(m);
-
-	/* Be sure we use the same brick type character as displayed
-	 * on the brick's LCD
-	 */
-	switch (brickchar) 
-	{
-	case L1_BRICKTYPE_GA:
-	case L1_BRICKTYPE_OPUS_TIO:
-		brickchar = L1_BRICKTYPE_C;
-		break;
-
-	case L1_BRICKTYPE_PX:
-	case L1_BRICKTYPE_PE:
-	case L1_BRICKTYPE_PA:
-	case L1_BRICKTYPE_SA: /* we can move this to the "I's" later
-			       * if that makes more sense
-			       */
-		brickchar = L1_BRICKTYPE_P;
-		break;
-
-	case L1_BRICKTYPE_IX:
-	case L1_BRICKTYPE_IA:
-
-		brickchar = L1_BRICKTYPE_I;
-		break;
-	}
-
-	position = MODULE_GET_BPOS(m);
-
-	if ((fmt == MODULE_FORMAT_BRIEF) || (fmt == MODULE_FORMAT_LCD)) {
-		/* Brief module number format, eg. 002c15 */
-
-		/* Decompress the rack number */
-		*buffer++ = '0' + RACK_GET_CLASS(rack);
-		*buffer++ = '0' + RACK_GET_GROUP(rack);
-		*buffer++ = '0' + RACK_GET_NUM(rack);
-
-		/* Add the brick type */
-		*buffer++ = brickchar;
-	}
-	else if (fmt == MODULE_FORMAT_LONG) {
-		/* Fuller hwgraph format, eg. rack/002/bay/15 */
-
-		strcpy(buffer, "rack" "/");  buffer += strlen(buffer);
-
-		*buffer++ = '0' + RACK_GET_CLASS(rack);
-		*buffer++ = '0' + RACK_GET_GROUP(rack);
-		*buffer++ = '0' + RACK_GET_NUM(rack);
-
-		strcpy(buffer, "/" "bay" "/");  buffer += strlen(buffer);
-	}
-
-	/* Add the bay position, using at least two digits */
-	if (position < 10)
-		*buffer++ = '0';
-	sprintf(buffer, "%d", position);
-}
diff --git a/arch/ia64/sn/kernel/machvec.c b/arch/ia64/sn/kernel/machvec.c
deleted file mode 100644
index 02bb9155840c..000000000000
--- a/arch/ia64/sn/kernel/machvec.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2002-2003 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#define MACHVEC_PLATFORM_NAME	sn2
-#define MACHVEC_PLATFORM_HEADER	<asm/machvec_sn2.h>
-#include <asm/machvec_init.h>
diff --git a/arch/ia64/sn/kernel/mca.c b/arch/ia64/sn/kernel/mca.c
deleted file mode 100644
index bc3bd930c74c..000000000000
--- a/arch/ia64/sn/kernel/mca.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2000-2006 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/timer.h>
-#include <linux/vmalloc.h>
-#include <linux/mutex.h>
-#include <asm/mca.h>
-#include <asm/sal.h>
-#include <asm/sn/sn_sal.h>
-
-/*
- * Interval for calling SAL to poll for errors that do NOT cause error
- * interrupts. SAL will raise a CPEI if any errors are present that
- * need to be logged.
- */
-#define CPEI_INTERVAL	(5*HZ)
-
-struct timer_list sn_cpei_timer;
-void sn_init_cpei_timer(void);
-
-/* Printing oemdata from mca uses data that is not passed through SAL, it is
- * global.  Only one user at a time.
- */
-static DEFINE_MUTEX(sn_oemdata_mutex);
-static u8 **sn_oemdata;
-static u64 *sn_oemdata_size, sn_oemdata_bufsize;
-
-/*
- * print_hook
- *
- * This function is the callback routine that SAL calls to log error
- * info for platform errors.  buf is appended to sn_oemdata, resizing as
- * required.
- * Note: this is a SAL to OS callback, running under the same rules as the SAL
- * code.  SAL calls are run with preempt disabled so this routine must not
- * sleep.  vmalloc can sleep so print_hook cannot resize the output buffer
- * itself, instead it must set the required size and return to let the caller
- * resize the buffer then redrive the SAL call.
- */
-static int print_hook(const char *fmt, ...)
-{
-	char buf[400];
-	int len;
-	va_list args;
-	va_start(args, fmt);
-	vsnprintf(buf, sizeof(buf), fmt, args);
-	va_end(args);
-	len = strlen(buf);
-	if (*sn_oemdata_size + len <= sn_oemdata_bufsize)
-		memcpy(*sn_oemdata + *sn_oemdata_size, buf, len);
-	*sn_oemdata_size += len;
-	return 0;
-}
-
-static void sn_cpei_handler(int irq, void *devid, struct pt_regs *regs)
-{
-	/*
-	 * this function's sole purpose is to call SAL when we receive
-	 * a CE interrupt from SHUB or when the timer routine decides
-	 * we need to call SAL to check for CEs.
-	 */
-
-	/* CALL SAL_LOG_CE */
-
-	ia64_sn_plat_cpei_handler();
-}
-
-static void sn_cpei_timer_handler(struct timer_list *unused)
-{
-	sn_cpei_handler(-1, NULL, NULL);
-	mod_timer(&sn_cpei_timer, jiffies + CPEI_INTERVAL);
-}
-
-void sn_init_cpei_timer(void)
-{
-	timer_setup(&sn_cpei_timer, sn_cpei_timer_handler, 0);
-	sn_cpei_timer.expires = jiffies + CPEI_INTERVAL;
-	add_timer(&sn_cpei_timer);
-}
-
-static int
-sn_platform_plat_specific_err_print(const u8 * sect_header, u8 ** oemdata,
-				    u64 * oemdata_size)
-{
-	mutex_lock(&sn_oemdata_mutex);
-	sn_oemdata = oemdata;
-	sn_oemdata_size = oemdata_size;
-	sn_oemdata_bufsize = 0;
-	*sn_oemdata_size = PAGE_SIZE;	/* first guess at how much data will be generated */
-	while (*sn_oemdata_size > sn_oemdata_bufsize) {
-		u8 *newbuf = vmalloc(*sn_oemdata_size);
-		if (!newbuf) {
-			mutex_unlock(&sn_oemdata_mutex);
-			printk(KERN_ERR "%s: unable to extend sn_oemdata\n",
-			       __func__);
-			return 1;
-		}
-		vfree(*sn_oemdata);
-		*sn_oemdata = newbuf;
-		sn_oemdata_bufsize = *sn_oemdata_size;
-		*sn_oemdata_size = 0;
-		ia64_sn_plat_specific_err_print(print_hook, (char *)sect_header);
-	}
-	mutex_unlock(&sn_oemdata_mutex);
-	return 0;
-}
-
-/* Callback when userspace salinfo wants to decode oem data via the platform
- * kernel and/or prom.
- */
-int sn_salinfo_platform_oemdata(const u8 *sect_header, u8 **oemdata, u64 *oemdata_size)
-{
-	efi_guid_t guid = *(efi_guid_t *)sect_header;
-	int valid = 0;
-	*oemdata_size = 0;
-	vfree(*oemdata);
-	*oemdata = NULL;
-	if (efi_guidcmp(guid, SAL_PLAT_SPECIFIC_ERR_SECT_GUID) == 0) {
-		sal_log_plat_specific_err_info_t *psei = (sal_log_plat_specific_err_info_t *)sect_header;
-		valid = psei->valid.oem_data;
-	} else if (efi_guidcmp(guid, SAL_PLAT_MEM_DEV_ERR_SECT_GUID) == 0) {
-		sal_log_mem_dev_err_info_t *mdei = (sal_log_mem_dev_err_info_t *)sect_header;
-		valid = mdei->valid.oem_data;
-	}
-	if (valid)
-		return sn_platform_plat_specific_err_print(sect_header, oemdata, oemdata_size);
-	else
-		return 0;
-}
-
-static int __init sn_salinfo_init(void)
-{
-	if (ia64_platform_is("sn2"))
-		salinfo_platform_oemdata = &sn_salinfo_platform_oemdata;
-	return 0;
-}
-device_initcall(sn_salinfo_init);
diff --git a/arch/ia64/sn/kernel/msi_sn.c b/arch/ia64/sn/kernel/msi_sn.c
deleted file mode 100644
index fb25065b22c6..000000000000
--- a/arch/ia64/sn/kernel/msi_sn.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#include <linux/types.h>
-#include <linux/irq.h>
-#include <linux/pci.h>
-#include <linux/cpumask.h>
-#include <linux/msi.h>
-#include <linux/slab.h>
-
-#include <asm/sn/addrs.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/nodepda.h>
-
-struct sn_msi_info {
-	u64 pci_addr;
-	struct sn_irq_info *sn_irq_info;
-};
-
-static struct sn_msi_info sn_msi_info[NR_IRQS];
-
-static struct irq_chip sn_msi_chip;
-
-void sn_teardown_msi_irq(unsigned int irq)
-{
-	nasid_t nasid;
-	int widget;
-	struct pci_dev *pdev;
-	struct pcidev_info *sn_pdev;
-	struct sn_irq_info *sn_irq_info;
-	struct pcibus_bussoft *bussoft;
-	struct sn_pcibus_provider *provider;
-
-	sn_irq_info = sn_msi_info[irq].sn_irq_info;
-	if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
-		return;
-
-	sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
-	pdev = sn_pdev->pdi_linux_pcidev;
-	provider = SN_PCIDEV_BUSPROVIDER(pdev);
-
-	(*provider->dma_unmap)(pdev,
-			       sn_msi_info[irq].pci_addr,
-			       PCI_DMA_FROMDEVICE);
-	sn_msi_info[irq].pci_addr = 0;
-
-	bussoft = SN_PCIDEV_BUSSOFT(pdev);
-	nasid = NASID_GET(bussoft->bs_base);
-	widget = (nasid & 1) ?
-			TIO_SWIN_WIDGETNUM(bussoft->bs_base) :
-			SWIN_WIDGETNUM(bussoft->bs_base);
-
-	sn_intr_free(nasid, widget, sn_irq_info);
-	sn_msi_info[irq].sn_irq_info = NULL;
-
-	destroy_irq(irq);
-}
-
-int sn_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *entry)
-{
-	struct msi_msg msg;
-	int widget;
-	int status;
-	nasid_t nasid;
-	u64 bus_addr;
-	struct sn_irq_info *sn_irq_info;
-	struct pcibus_bussoft *bussoft = SN_PCIDEV_BUSSOFT(pdev);
-	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
-	int irq;
-
-	if (!entry->msi_attrib.is_64)
-		return -EINVAL;
-
-	if (bussoft == NULL)
-		return -EINVAL;
-
-	if (provider == NULL || provider->dma_map_consistent == NULL)
-		return -EINVAL;
-
-	irq = create_irq();
-	if (irq < 0)
-		return irq;
-
-	/*
-	 * Set up the vector plumbing.  Let the prom (via sn_intr_alloc)
-	 * decide which cpu to direct this msi at by default.
-	 */
-
-	nasid = NASID_GET(bussoft->bs_base);
-	widget = (nasid & 1) ?
-			TIO_SWIN_WIDGETNUM(bussoft->bs_base) :
-			SWIN_WIDGETNUM(bussoft->bs_base);
-
-	sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
-	if (! sn_irq_info) {
-		destroy_irq(irq);
-		return -ENOMEM;
-	}
-
-	status = sn_intr_alloc(nasid, widget, sn_irq_info, irq, -1, -1);
-	if (status) {
-		kfree(sn_irq_info);
-		destroy_irq(irq);
-		return -ENOMEM;
-	}
-
-	sn_irq_info->irq_int_bit = -1;		/* mark this as an MSI irq */
-	sn_irq_fixup(pdev, sn_irq_info);
-
-	/* Prom probably should fill these in, but doesn't ... */
-	sn_irq_info->irq_bridge_type = bussoft->bs_asic_type;
-	sn_irq_info->irq_bridge = (void *)bussoft->bs_base;
-
-	/*
-	 * Map the xio address into bus space
-	 */
-	bus_addr = (*provider->dma_map_consistent)(pdev,
-					sn_irq_info->irq_xtalkaddr,
-					sizeof(sn_irq_info->irq_xtalkaddr),
-					SN_DMA_MSI|SN_DMA_ADDR_XIO);
-	if (! bus_addr) {
-		sn_intr_free(nasid, widget, sn_irq_info);
-		kfree(sn_irq_info);
-		destroy_irq(irq);
-		return -ENOMEM;
-	}
-
-	sn_msi_info[irq].sn_irq_info = sn_irq_info;
-	sn_msi_info[irq].pci_addr = bus_addr;
-
-	msg.address_hi = (u32)(bus_addr >> 32);
-	msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
-
-	/*
-	 * In the SN platform, bit 16 is a "send vector" bit which
-	 * must be present in order to move the vector through the system.
-	 */
-	msg.data = 0x100 + irq;
-
-	irq_set_msi_desc(irq, entry);
-	pci_write_msi_msg(irq, &msg);
-	irq_set_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq);
-
-	return 0;
-}
-
-#ifdef CONFIG_SMP
-static int sn_set_msi_irq_affinity(struct irq_data *data,
-				   const struct cpumask *cpu_mask, bool force)
-{
-	struct msi_msg msg;
-	int slice;
-	nasid_t nasid;
-	u64 bus_addr;
-	struct pci_dev *pdev;
-	struct pcidev_info *sn_pdev;
-	struct sn_irq_info *sn_irq_info;
-	struct sn_irq_info *new_irq_info;
-	struct sn_pcibus_provider *provider;
-	unsigned int cpu, irq = data->irq;
-
-	cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
-	sn_irq_info = sn_msi_info[irq].sn_irq_info;
-	if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
-		return -1;
-
-	/*
-	 * Release XIO resources for the old MSI PCI address
-	 */
-
-	__get_cached_msi_msg(irq_data_get_msi_desc(data), &msg);
-	sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
-	pdev = sn_pdev->pdi_linux_pcidev;
-	provider = SN_PCIDEV_BUSPROVIDER(pdev);
-
-	bus_addr = (u64)(msg.address_hi) << 32 | (u64)(msg.address_lo);
-	(*provider->dma_unmap)(pdev, bus_addr, PCI_DMA_FROMDEVICE);
-	sn_msi_info[irq].pci_addr = 0;
-
-	nasid = cpuid_to_nasid(cpu);
-	slice = cpuid_to_slice(cpu);
-
-	new_irq_info = sn_retarget_vector(sn_irq_info, nasid, slice);
-	sn_msi_info[irq].sn_irq_info = new_irq_info;
-	if (new_irq_info == NULL)
-		return -1;
-
-	/*
-	 * Map the xio address into bus space
-	 */
-
-	bus_addr = (*provider->dma_map_consistent)(pdev,
-					new_irq_info->irq_xtalkaddr,
-					sizeof(new_irq_info->irq_xtalkaddr),
-					SN_DMA_MSI|SN_DMA_ADDR_XIO);
-
-	sn_msi_info[irq].pci_addr = bus_addr;
-	msg.address_hi = (u32)(bus_addr >> 32);
-	msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
-
-	pci_write_msi_msg(irq, &msg);
-	cpumask_copy(irq_data_get_affinity_mask(data), cpu_mask);
-
-	return 0;
-}
-#endif /* CONFIG_SMP */
-
-static void sn_ack_msi_irq(struct irq_data *data)
-{
-	irq_move_irq(data);
-	ia64_eoi();
-}
-
-static int sn_msi_retrigger_irq(struct irq_data *data)
-{
-	unsigned int vector = data->irq;
-	ia64_resend_irq(vector);
-
-	return 1;
-}
-
-static struct irq_chip sn_msi_chip = {
-	.name			= "PCI-MSI",
-	.irq_mask		= pci_msi_mask_irq,
-	.irq_unmask		= pci_msi_unmask_irq,
-	.irq_ack		= sn_ack_msi_irq,
-#ifdef CONFIG_SMP
-	.irq_set_affinity	= sn_set_msi_irq_affinity,
-#endif
-	.irq_retrigger		= sn_msi_retrigger_irq,
-};
diff --git a/arch/ia64/sn/kernel/pio_phys.S b/arch/ia64/sn/kernel/pio_phys.S
deleted file mode 100644
index 3c7d48d6ecb8..000000000000
--- a/arch/ia64/sn/kernel/pio_phys.S
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
- *
- * This file contains macros used to access MMR registers via
- * uncached physical addresses.
- *      pio_phys_read_mmr  - read an MMR
- *      pio_phys_write_mmr - write an MMR
- *      pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
- *              Second MMR will be skipped if address is NULL
- *
- * Addresses passed to these routines should be uncached physical addresses
- * 	ie., 0x80000....
- */
-
-
-
-#include <asm/asmmacro.h>
-#include <asm/page.h>
-
-GLOBAL_ENTRY(pio_phys_read_mmr)
-	.prologue
-	.regstk 1,0,0,0
-	.body
-	mov r2=psr
-	rsm psr.i | psr.dt
-	;;
-	srlz.d
-	ld8.acq r8=[r32]
-	;;
-	mov psr.l=r2;;
-	srlz.d
-	br.ret.sptk.many rp
-END(pio_phys_read_mmr)
-
-GLOBAL_ENTRY(pio_phys_write_mmr)
-	.prologue
-	.regstk 2,0,0,0
-	.body
-	mov r2=psr
-	rsm psr.i | psr.dt
-	;;
-	srlz.d
-	st8.rel [r32]=r33
-	;;
-	mov psr.l=r2;;
-	srlz.d
-	br.ret.sptk.many rp
-END(pio_phys_write_mmr)
-
-GLOBAL_ENTRY(pio_atomic_phys_write_mmrs)
-	.prologue
-	.regstk 4,0,0,0
-	.body
-	mov r2=psr
-	cmp.ne p9,p0=r34,r0;
-	rsm psr.i | psr.dt | psr.ic
-	;;
-	srlz.d
-	st8.rel [r32]=r33
-(p9)	st8.rel [r34]=r35
-	;;
-	mov psr.l=r2;;
-	srlz.d
-	br.ret.sptk.many rp
-END(pio_atomic_phys_write_mmrs)
-
-
diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
deleted file mode 100644
index e6a5049ef503..000000000000
--- a/arch/ia64/sn/kernel/setup.c
+++ /dev/null
@@ -1,786 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/kdev_t.h>
-#include <linux/string.h>
-#include <linux/screen_info.h>
-#include <linux/console.h>
-#include <linux/timex.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/serial.h>
-#include <linux/irq.h>
-#include <linux/memblock.h>
-#include <linux/mmzone.h>
-#include <linux/interrupt.h>
-#include <linux/acpi.h>
-#include <linux/compiler.h>
-#include <linux/root_dev.h>
-#include <linux/nodemask.h>
-#include <linux/pm.h>
-#include <linux/efi.h>
-
-#include <asm/io.h>
-#include <asm/sal.h>
-#include <asm/machvec.h>
-#include <asm/processor.h>
-#include <asm/vga.h>
-#include <asm/setup.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/pda.h>
-#include <asm/sn/nodepda.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/simulator.h>
-#include <asm/sn/leds.h>
-#include <asm/sn/bte.h>
-#include <asm/sn/shub_mmr.h>
-#include <asm/sn/clksupport.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/geo.h>
-#include <asm/sn/sn_feature_sets.h>
-#include "xtalk/xwidgetdev.h"
-#include "xtalk/hubdev.h"
-#include <asm/sn/klconfig.h>
-
-
-DEFINE_PER_CPU(struct pda_s, pda_percpu);
-
-#define MAX_PHYS_MEMORY		(1UL << IA64_MAX_PHYS_BITS)	/* Max physical address supported */
-
-extern void bte_init_node(nodepda_t *, cnodeid_t);
-
-extern void sn_timer_init(void);
-extern unsigned long last_time_offset;
-extern void (*ia64_mark_idle) (int);
-extern void snidle(int);
-
-unsigned long sn_rtc_cycles_per_second;
-EXPORT_SYMBOL(sn_rtc_cycles_per_second);
-
-DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
-EXPORT_PER_CPU_SYMBOL(__sn_hub_info);
-
-DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
-EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid);
-
-DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda);
-EXPORT_PER_CPU_SYMBOL(__sn_nodepda);
-
-char sn_system_serial_number_string[128];
-EXPORT_SYMBOL(sn_system_serial_number_string);
-u64 sn_partition_serial_number;
-EXPORT_SYMBOL(sn_partition_serial_number);
-u8 sn_partition_id;
-EXPORT_SYMBOL(sn_partition_id);
-u8 sn_system_size;
-EXPORT_SYMBOL(sn_system_size);
-u8 sn_sharing_domain_size;
-EXPORT_SYMBOL(sn_sharing_domain_size);
-u8 sn_coherency_id;
-EXPORT_SYMBOL(sn_coherency_id);
-u8 sn_region_size;
-EXPORT_SYMBOL(sn_region_size);
-int sn_prom_type;	/* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
-
-short physical_node_map[MAX_NUMALINK_NODES];
-static unsigned long sn_prom_features[MAX_PROM_FEATURE_SETS];
-
-EXPORT_SYMBOL(physical_node_map);
-
-int num_cnodes;
-
-static void sn_init_pdas(char **);
-static void build_cnode_tables(void);
-
-static nodepda_t *nodepdaindr[MAX_COMPACT_NODES];
-
-/*
- * The format of "screen_info" is strange, and due to early i386-setup
- * code. This is just enough to make the console code think we're on a
- * VGA color display.
- */
-struct screen_info sn_screen_info = {
-	.orig_x = 0,
-	.orig_y = 0,
-	.orig_video_mode = 3,
-	.orig_video_cols = 80,
-	.orig_video_ega_bx = 3,
-	.orig_video_lines = 25,
-	.orig_video_isVGA = 1,
-	.orig_video_points = 16
-};
-
-/*
- * This routine can only be used during init, since
- * smp_boot_data is an init data structure.
- * We have to use smp_boot_data.cpu_phys_id to find
- * the physical id of the processor because the normal
- * cpu_physical_id() relies on data structures that
- * may not be initialized yet.
- */
-
-static int __init pxm_to_nasid(int pxm)
-{
-	int i;
-	int nid;
-
-	nid = pxm_to_node(pxm);
-	for (i = 0; i < num_node_memblks; i++) {
-		if (node_memblk[i].nid == nid) {
-			return NASID_GET(node_memblk[i].start_paddr);
-		}
-	}
-	return -1;
-}
-
-/**
- * early_sn_setup - early setup routine for SN platforms
- *
- * Sets up an initial console to aid debugging.  Intended primarily
- * for bringup.  See start_kernel() in init/main.c.
- */
-
-void __init early_sn_setup(void)
-{
-	efi_system_table_t *efi_systab;
-	efi_config_table_t *config_tables;
-	struct ia64_sal_systab *sal_systab;
-	struct ia64_sal_desc_entry_point *ep;
-	char *p;
-	int i, j;
-
-	/*
-	 * Parse enough of the SAL tables to locate the SAL entry point. Since, console
-	 * IO on SN2 is done via SAL calls, early_printk won't work without this.
-	 *
-	 * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c.
-	 * Any changes to those file may have to be made here as well.
-	 */
-	efi_systab = (efi_system_table_t *) __va(ia64_boot_param->efi_systab);
-	config_tables = __va(efi_systab->tables);
-	for (i = 0; i < efi_systab->nr_tables; i++) {
-		if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) ==
-		    0) {
-			sal_systab = __va(config_tables[i].table);
-			p = (char *)(sal_systab + 1);
-			for (j = 0; j < sal_systab->entry_count; j++) {
-				if (*p == SAL_DESC_ENTRY_POINT) {
-					ep = (struct ia64_sal_desc_entry_point
-					      *)p;
-					ia64_sal_handler_init(__va
-							      (ep->sal_proc),
-							      __va(ep->gp));
-					return;
-				}
-				p += SAL_DESC_SIZE(*p);
-			}
-		}
-	}
-	/* Uh-oh, SAL not available?? */
-	printk(KERN_ERR "failed to find SAL entry point\n");
-}
-
-extern int platform_intr_list[];
-static int shub_1_1_found;
-
-/*
- * sn_check_for_wars
- *
- * Set flag for enabling shub specific wars
- */
-
-static inline int is_shub_1_1(int nasid)
-{
-	unsigned long id;
-	int rev;
-
-	if (is_shub2())
-		return 0;
-	id = REMOTE_HUB_L(nasid, SH1_SHUB_ID);
-	rev = (id & SH1_SHUB_ID_REVISION_MASK) >> SH1_SHUB_ID_REVISION_SHFT;
-	return rev <= 2;
-}
-
-static void sn_check_for_wars(void)
-{
-	int cnode;
-
-	if (is_shub2()) {
-		/* none yet */
-	} else {
-		for_each_online_node(cnode) {
-			if (is_shub_1_1(cnodeid_to_nasid(cnode)))
-				shub_1_1_found = 1;
-		}
-	}
-}
-
-/*
- * Scan the EFI PCDP table (if it exists) for an acceptable VGA console
- * output device.  If one exists, pick it and set sn_legacy_{io,mem} to
- * reflect the bus offsets needed to address it.
- *
- * Since pcdp support in SN is not supported in the 2.4 kernel (or at least
- * the one lbs is based on) just declare the needed structs here.
- *
- * Reference spec http://www.dig64.org/specifications/DIG64_PCDPv20.pdf
- *
- * Returns 0 if no acceptable vga is found, !0 otherwise.
- *
- * Note:  This stuff is duped here because Altix requires the PCDP to
- * locate a usable VGA device due to lack of proper ACPI support.  Structures
- * could be used from drivers/firmware/pcdp.h, but it was decided that moving
- * this file to a more public location just for Altix use was undesirable.
- */
-
-struct hcdp_uart_desc {
-	u8	pad[45];
-};
-
-struct pcdp {
-	u8	signature[4];	/* should be 'HCDP' */
-	u32	length;
-	u8	rev;		/* should be >=3 for pcdp, <3 for hcdp */
-	u8	sum;
-	u8	oem_id[6];
-	u64	oem_tableid;
-	u32	oem_rev;
-	u32	creator_id;
-	u32	creator_rev;
-	u32	num_type0;
-	struct hcdp_uart_desc uart[0];	/* num_type0 of these */
-	/* pcdp descriptors follow */
-}  __attribute__((packed));
-
-struct pcdp_device_desc {
-	u8	type;
-	u8	primary;
-	u16	length;
-	u16	index;
-	/* interconnect specific structure follows */
-	/* device specific structure follows that */
-}  __attribute__((packed));
-
-struct pcdp_interface_pci {
-	u8	type;		/* 1 == pci */
-	u8	reserved;
-	u16	length;
-	u8	segment;
-	u8	bus;
-	u8 	dev;
-	u8	fun;
-	u16	devid;
-	u16	vendid;
-	u32	acpi_interrupt;
-	u64	mmio_tra;
-	u64	ioport_tra;
-	u8	flags;
-	u8	translation;
-}  __attribute__((packed));
-
-struct pcdp_vga_device {
-	u8	num_eas_desc;
-	/* ACPI Extended Address Space Desc follows */
-}  __attribute__((packed));
-
-/* from pcdp_device_desc.primary */
-#define PCDP_PRIMARY_CONSOLE	0x01
-
-/* from pcdp_device_desc.type */
-#define PCDP_CONSOLE_INOUT	0x0
-#define PCDP_CONSOLE_DEBUG	0x1
-#define PCDP_CONSOLE_OUT	0x2
-#define PCDP_CONSOLE_IN		0x3
-#define PCDP_CONSOLE_TYPE_VGA	0x8
-
-#define PCDP_CONSOLE_VGA	(PCDP_CONSOLE_TYPE_VGA | PCDP_CONSOLE_OUT)
-
-/* from pcdp_interface_pci.type */
-#define PCDP_IF_PCI		1
-
-/* from pcdp_interface_pci.translation */
-#define PCDP_PCI_TRANS_IOPORT	0x02
-#define PCDP_PCI_TRANS_MMIO	0x01
-
-#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
-static void
-sn_scan_pcdp(void)
-{
-	u8 *bp;
-	struct pcdp *pcdp;
-	struct pcdp_device_desc device;
-	struct pcdp_interface_pci if_pci;
-	extern struct efi efi;
-
-	if (efi.hcdp == EFI_INVALID_TABLE_ADDR)
-		return;		/* no hcdp/pcdp table */
-
-	pcdp = __va(efi.hcdp);
-
-	if (pcdp->rev < 3)
-		return;		/* only support PCDP (rev >= 3) */
-
-	for (bp = (u8 *)&pcdp->uart[pcdp->num_type0];
-	     bp < (u8 *)pcdp + pcdp->length;
-	     bp += device.length) {
-		memcpy(&device, bp, sizeof(device));
-		if (! (device.primary & PCDP_PRIMARY_CONSOLE))
-			continue;	/* not primary console */
-
-		if (device.type != PCDP_CONSOLE_VGA)
-			continue;	/* not VGA descriptor */
-
-		memcpy(&if_pci, bp+sizeof(device), sizeof(if_pci));
-		if (if_pci.type != PCDP_IF_PCI)
-			continue;	/* not PCI interconnect */
-
-		if (if_pci.translation & PCDP_PCI_TRANS_IOPORT)
-			vga_console_iobase = if_pci.ioport_tra;
-
-		if (if_pci.translation & PCDP_PCI_TRANS_MMIO)
-			vga_console_membase =
-				if_pci.mmio_tra | __IA64_UNCACHED_OFFSET;
-
-		break; /* once we find the primary, we're done */
-	}
-}
-#endif
-
-static unsigned long sn2_rtc_initial;
-
-/**
- * sn_setup - SN platform setup routine
- * @cmdline_p: kernel command line
- *
- * Handles platform setup for SN machines.  This includes determining
- * the RTC frequency (via a SAL call), initializing secondary CPUs, and
- * setting up per-node data areas.  The console is also initialized here.
- */
-void __init sn_setup(char **cmdline_p)
-{
-	long status, ticks_per_sec, drift;
-	u32 version = sn_sal_rev();
-	extern void sn_cpu_init(void);
-
-	sn2_rtc_initial = rtc_time();
-	ia64_sn_plat_set_error_handling_features();	// obsolete
-	ia64_sn_set_os_feature(OSF_MCA_SLV_TO_OS_INIT_SLV);
-	ia64_sn_set_os_feature(OSF_FEAT_LOG_SBES);
-	/*
-	 * Note: The calls to notify the PROM of ACPI and PCI Segment
-	 *	 support must be done prior to acpi_load_tables(), as
-	 *	 an ACPI capable PROM will rebuild the DSDT as result
-	 *	 of the call.
-	 */
-	ia64_sn_set_os_feature(OSF_PCISEGMENT_ENABLE);
-	ia64_sn_set_os_feature(OSF_ACPI_ENABLE);
-
-	/* Load the new DSDT and SSDT tables into the global table list. */
-	acpi_table_init();
-
-#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
-	/*
-	 * Handle SN vga console.
-	 *
-	 * SN systems do not have enough ACPI table information
-	 * being passed from prom to identify VGA adapters and the legacy
-	 * addresses to access them.  Until that is done, SN systems rely
-	 * on the PCDP table to identify the primary VGA console if one
-	 * exists.
-	 *
-	 * However, kernel PCDP support is optional, and even if it is built
-	 * into the kernel, it will not be used if the boot cmdline contains
-	 * console= directives.
-	 *
-	 * So, to work around this mess, we duplicate some of the PCDP code
-	 * here so that the primary VGA console (as defined by PCDP) will
-	 * work on SN systems even if a different console (e.g. serial) is
-	 * selected on the boot line (or CONFIG_EFI_PCDP is off).
-	 */
-
-	if (! vga_console_membase)
-		sn_scan_pcdp();
-
-	/*
-	 *	Setup legacy IO space.
-	 *	vga_console_iobase maps to PCI IO Space address 0 on the
-	 * 	bus containing the VGA console.
-	 */
-	if (vga_console_iobase) {
-		io_space[0].mmio_base =
-			(unsigned long) ioremap(vga_console_iobase, 0);
-		io_space[0].sparse = 0;
-	}
-
-	if (vga_console_membase) {
-		/* usable vga ... make tty0 the preferred default console */
-		if (!strstr(*cmdline_p, "console="))
-			add_preferred_console("tty", 0, NULL);
-	} else {
-		printk(KERN_DEBUG "SGI: Disabling VGA console\n");
-		if (!strstr(*cmdline_p, "console="))
-			add_preferred_console("ttySG", 0, NULL);
-#ifdef CONFIG_DUMMY_CONSOLE
-		conswitchp = &dummy_con;
-#else
-		conswitchp = NULL;
-#endif				/* CONFIG_DUMMY_CONSOLE */
-	}
-#endif				/* def(CONFIG_VT) && def(CONFIG_VGA_CONSOLE) */
-
-	MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY;
-
-	/*
-	 * Build the tables for managing cnodes.
-	 */
-	build_cnode_tables();
-
-	status =
-	    ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
-			       &drift);
-	if (status != 0 || ticks_per_sec < 100000) {
-		printk(KERN_WARNING
-		       "unable to determine platform RTC clock frequency, guessing.\n");
-		/* PROM gives wrong value for clock freq. so guess */
-		sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
-	} else
-		sn_rtc_cycles_per_second = ticks_per_sec;
-
-	platform_intr_list[ACPI_INTERRUPT_CPEI] = IA64_CPE_VECTOR;
-
-	printk("SGI SAL version %x.%02x\n", version >> 8, version & 0x00FF);
-
-	/*
-	 * we set the default root device to /dev/hda
-	 * to make simulation easy
-	 */
-	ROOT_DEV = Root_HDA1;
-
-	/*
-	 * Create the PDAs and NODEPDAs for all the cpus.
-	 */
-	sn_init_pdas(cmdline_p);
-
-	ia64_mark_idle = &snidle;
-
-	/*
-	 * For the bootcpu, we do this here. All other cpus will make the
-	 * call as part of cpu_init in slave cpu initialization.
-	 */
-	sn_cpu_init();
-
-#ifdef CONFIG_SMP
-	init_smp_config();
-#endif
-	screen_info = sn_screen_info;
-
-	sn_timer_init();
-
-	/*
-	 * set pm_power_off to a SAL call to allow
-	 * sn machines to power off. The SAL call can be replaced
-	 * by an ACPI interface call when ACPI is fully implemented
-	 * for sn.
-	 */
-	pm_power_off = ia64_sn_power_down;
-	current->thread.flags |= IA64_THREAD_MIGRATION;
-}
-
-/**
- * sn_init_pdas - setup node data areas
- *
- * One time setup for Node Data Area.  Called by sn_setup().
- */
-static void __init sn_init_pdas(char **cmdline_p)
-{
-	cnodeid_t cnode;
-
-	/*
-	 * Allocate & initialize the nodepda for each node.
-	 */
-	for_each_online_node(cnode) {
-		nodepdaindr[cnode] =
-		    memblock_alloc_node(sizeof(nodepda_t), SMP_CACHE_BYTES,
-					cnode);
-		if (!nodepdaindr[cnode])
-			panic("%s: Failed to allocate %lu bytes align=0x%x nid=%d\n",
-			      __func__, sizeof(nodepda_t), SMP_CACHE_BYTES,
-			      cnode);
-		memset(nodepdaindr[cnode]->phys_cpuid, -1,
-		    sizeof(nodepdaindr[cnode]->phys_cpuid));
-		spin_lock_init(&nodepdaindr[cnode]->ptc_lock);
-	}
-
-	/*
-	 * Allocate & initialize nodepda for TIOs.  For now, put them on node 0.
-	 */
-	for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++) {
-		nodepdaindr[cnode] =
-		    memblock_alloc_node(sizeof(nodepda_t), SMP_CACHE_BYTES, 0);
-		if (!nodepdaindr[cnode])
-			panic("%s: Failed to allocate %lu bytes align=0x%x nid=%d\n",
-			      __func__, sizeof(nodepda_t), SMP_CACHE_BYTES,
-			      cnode);
-	}
-
-
-	/*
-	 * Now copy the array of nodepda pointers to each nodepda.
-	 */
-	for (cnode = 0; cnode < num_cnodes; cnode++)
-		memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr,
-		       sizeof(nodepdaindr));
-
-	/*
-	 * Set up IO related platform-dependent nodepda fields.
-	 * The following routine actually sets up the hubinfo struct
-	 * in nodepda.
-	 */
-	for_each_online_node(cnode) {
-		bte_init_node(nodepdaindr[cnode], cnode);
-	}
-
-	/*
-	 * Initialize the per node hubdev.  This includes IO Nodes and
-	 * headless/memless nodes.
-	 */
-	for (cnode = 0; cnode < num_cnodes; cnode++) {
-		hubdev_init_node(nodepdaindr[cnode], cnode);
-	}
-}
-
-/**
- * sn_cpu_init - initialize per-cpu data areas
- * @cpuid: cpuid of the caller
- *
- * Called during cpu initialization on each cpu as it starts.
- * Currently, initializes the per-cpu data area for SNIA.
- * Also sets up a few fields in the nodepda.  Also known as
- * platform_cpu_init() by the ia64 machvec code.
- */
-void sn_cpu_init(void)
-{
-	int cpuid;
-	int cpuphyid;
-	int nasid;
-	int subnode;
-	int slice;
-	int cnode;
-	int i;
-	static int wars_have_been_checked, set_cpu0_number;
-
-	cpuid = smp_processor_id();
-	if (cpuid == 0 && IS_MEDUSA()) {
-		if (ia64_sn_is_fake_prom())
-			sn_prom_type = 2;
-		else
-			sn_prom_type = 1;
-		printk(KERN_INFO "Running on medusa with %s PROM\n",
-		       (sn_prom_type == 1) ? "real" : "fake");
-	}
-
-	memset(pda, 0, sizeof(*pda));
-	if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2,
-				&sn_hub_info->nasid_bitmask,
-				&sn_hub_info->nasid_shift,
-				&sn_system_size, &sn_sharing_domain_size,
-				&sn_partition_id, &sn_coherency_id,
-				&sn_region_size))
-		BUG();
-	sn_hub_info->as_shift = sn_hub_info->nasid_shift - 2;
-
-	/*
-	 * Don't check status. The SAL call is not supported on all PROMs
-	 * but a failure is harmless.
-	 * Architecturally, cpu_init is always called twice on cpu 0. We
-	 * should set cpu_number on cpu 0 once.
-	 */
-	if (cpuid == 0) {
-		if (!set_cpu0_number) {
-			(void) ia64_sn_set_cpu_number(cpuid);
-			set_cpu0_number = 1;
-		}
-	} else
-		(void) ia64_sn_set_cpu_number(cpuid);
-
-	/*
-	 * The boot cpu makes this call again after platform initialization is
-	 * complete.
-	 */
-	if (nodepdaindr[0] == NULL)
-		return;
-
-	for (i = 0; i < MAX_PROM_FEATURE_SETS; i++)
-		if (ia64_sn_get_prom_feature_set(i, &sn_prom_features[i]) != 0)
-			break;
-
-	cpuphyid = get_sapicid();
-
-	if (ia64_sn_get_sapic_info(cpuphyid, &nasid, &subnode, &slice))
-		BUG();
-
-	for (i=0; i < MAX_NUMNODES; i++) {
-		if (nodepdaindr[i]) {
-			nodepdaindr[i]->phys_cpuid[cpuid].nasid = nasid;
-			nodepdaindr[i]->phys_cpuid[cpuid].slice = slice;
-			nodepdaindr[i]->phys_cpuid[cpuid].subnode = subnode;
-		}
-	}
-
-	cnode = nasid_to_cnodeid(nasid);
-
-	__this_cpu_write(__sn_nodepda, nodepdaindr[cnode]);
-
-	pda->led_address =
-	    (typeof(pda->led_address)) (LED0 + (slice << LED_CPU_SHIFT));
-	pda->led_state = LED_ALWAYS_SET;
-	pda->hb_count = HZ / 2;
-	pda->hb_state = 0;
-	pda->idle_flag = 0;
-
-	if (cpuid != 0) {
-		/* copy cpu 0's sn_cnodeid_to_nasid table to this cpu's */
-		memcpy(sn_cnodeid_to_nasid,
-		       (&per_cpu(__sn_cnodeid_to_nasid, 0)),
-		       sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid)));
-	}
-
-	/*
-	 * Check for WARs.
-	 * Only needs to be done once, on BSP.
-	 * Has to be done after loop above, because it uses this cpu's
-	 * sn_cnodeid_to_nasid table which was just initialized if this
-	 * isn't cpu 0.
-	 * Has to be done before assignment below.
-	 */
-	if (!wars_have_been_checked) {
-		sn_check_for_wars();
-		wars_have_been_checked = 1;
-	}
-	sn_hub_info->shub_1_1_found = shub_1_1_found;
-
-	/*
-	 * Set up addresses of PIO/MEM write status registers.
-	 */
-	{
-		u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0};
-		u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_2,
-			SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3};
-		u64 *pio;
-		pio = is_shub1() ? pio1 : pio2;
-		pda->pio_write_status_addr =
-		   (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]);
-		pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0;
-	}
-
-	/*
-	 * WAR addresses for SHUB 1.x.
-	 */
-	if (local_node_data->active_cpu_count++ == 0 && is_shub1()) {
-		int buddy_nasid;
-		buddy_nasid =
-		    cnodeid_to_nasid(numa_node_id() ==
-				     num_online_nodes() - 1 ? 0 : numa_node_id() + 1);
-		pda->pio_shub_war_cam_addr =
-		    (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid,
-							      SH1_PI_CAM_CONTROL);
-	}
-}
-
-/*
- * Build tables for converting between NASIDs and cnodes.
- */
-static inline int __init board_needs_cnode(int type)
-{
-	return (type == KLTYPE_SNIA || type == KLTYPE_TIO);
-}
-
-void __init build_cnode_tables(void)
-{
-	int nasid;
-	int node;
-	lboard_t *brd;
-
-	memset(physical_node_map, -1, sizeof(physical_node_map));
-	memset(sn_cnodeid_to_nasid, -1,
-			sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid)));
-
-	/*
-	 * First populate the tables with C/M bricks. This ensures that
-	 * cnode == node for all C & M bricks.
-	 */
-	for_each_online_node(node) {
-		nasid = pxm_to_nasid(node_to_pxm(node));
-		sn_cnodeid_to_nasid[node] = nasid;
-		physical_node_map[nasid] = node;
-	}
-
-	/*
-	 * num_cnodes is total number of C/M/TIO bricks. Because of the 256 node
-	 * limit on the number of nodes, we can't use the generic node numbers 
-	 * for this. Note that num_cnodes is incremented below as TIOs or
-	 * headless/memoryless nodes are discovered.
-	 */
-	num_cnodes = num_online_nodes();
-
-	/* fakeprom does not support klgraph */
-	if (IS_RUNNING_ON_FAKE_PROM())
-		return;
-
-	/* Find TIOs & headless/memoryless nodes and add them to the tables */
-	for_each_online_node(node) {
-		kl_config_hdr_t *klgraph_header;
-		nasid = cnodeid_to_nasid(node);
-		klgraph_header = ia64_sn_get_klconfig_addr(nasid);
-		BUG_ON(klgraph_header == NULL);
-		brd = NODE_OFFSET_TO_LBOARD(nasid, klgraph_header->ch_board_info);
-		while (brd) {
-			if (board_needs_cnode(brd->brd_type) && physical_node_map[brd->brd_nasid] < 0) {
-				sn_cnodeid_to_nasid[num_cnodes] = brd->brd_nasid;
-				physical_node_map[brd->brd_nasid] = num_cnodes++;
-			}
-			brd = find_lboard_next(brd);
-		}
-	}
-}
-
-int
-nasid_slice_to_cpuid(int nasid, int slice)
-{
-	long cpu;
-
-	for (cpu = 0; cpu < nr_cpu_ids; cpu++)
-		if (cpuid_to_nasid(cpu) == nasid &&
-					cpuid_to_slice(cpu) == slice)
-			return cpu;
-
-	return -1;
-}
-
-int sn_prom_feature_available(int id)
-{
-	if (id >= BITS_PER_LONG * MAX_PROM_FEATURE_SETS)
-		return 0;
-	return test_bit(id, sn_prom_features);
-}
-
-void
-sn_kernel_launch_event(void)
-{
-	/* ignore status until we understand possible failure, if any*/
-	if (ia64_sn_kernel_launch_event())
-		printk(KERN_ERR "KEXEC is not supported in this PROM, Please update the PROM.\n");
-}
-EXPORT_SYMBOL(sn_prom_feature_available);
-
diff --git a/arch/ia64/sn/kernel/sn2/Makefile b/arch/ia64/sn/kernel/sn2/Makefile
deleted file mode 100644
index 170bde4549da..000000000000
--- a/arch/ia64/sn/kernel/sn2/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# arch/ia64/sn/kernel/sn2/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved.
-#
-# sn2 specific kernel files
-#
-
-obj-y += cache.o io.o ptc_deadlock.o sn2_smp.o sn_proc_fs.o \
-	 prominfo_proc.o timer.o timer_interrupt.o sn_hwperf.o
diff --git a/arch/ia64/sn/kernel/sn2/cache.c b/arch/ia64/sn/kernel/sn2/cache.c
deleted file mode 100644
index 2862cb33026d..000000000000
--- a/arch/ia64/sn/kernel/sn2/cache.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- * 
- * Copyright (C) 2001-2003, 2006 Silicon Graphics, Inc. All rights reserved.
- *
- */
-#include <linux/module.h>
-#include <asm/pgalloc.h>
-#include <asm/sn/arch.h>
-
-/**
- * sn_flush_all_caches - flush a range of address from all caches (incl. L4)
- * @flush_addr: identity mapped region 7 address to start flushing
- * @bytes: number of bytes to flush
- *
- * Flush a range of addresses from all caches including L4. 
- * All addresses fully or partially contained within 
- * @flush_addr to @flush_addr + @bytes are flushed
- * from all caches.
- */
-void
-sn_flush_all_caches(long flush_addr, long bytes)
-{
-	unsigned long addr = flush_addr;
-
-	/* SHub1 requires a cached address */
-	if (is_shub1() && (addr & RGN_BITS) == RGN_BASE(RGN_UNCACHED))
-		addr = (addr - RGN_BASE(RGN_UNCACHED)) + RGN_BASE(RGN_KERNEL);
-
-	flush_icache_range(addr, addr + bytes);
-	/*
-	 * The last call may have returned before the caches
-	 * were actually flushed, so we call it again to make
-	 * sure.
-	 */
-	flush_icache_range(addr, addr + bytes);
-	mb();
-}
-EXPORT_SYMBOL(sn_flush_all_caches);
diff --git a/arch/ia64/sn/kernel/sn2/io.c b/arch/ia64/sn/kernel/sn2/io.c
deleted file mode 100644
index a12c0586de38..000000000000
--- a/arch/ia64/sn/kernel/sn2/io.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 Silicon Graphics, Inc. All rights reserved.
- *
- * The generic kernel requires function pointers to these routines, so
- * we wrap the inlines from asm/ia64/sn/sn2/io.h here.
- */
-
-#include <asm/sn/io.h>
-
-#ifdef CONFIG_IA64_GENERIC
-
-#undef __sn_inb
-#undef __sn_inw
-#undef __sn_inl
-#undef __sn_outb
-#undef __sn_outw
-#undef __sn_outl
-#undef __sn_readb
-#undef __sn_readw
-#undef __sn_readl
-#undef __sn_readq
-#undef __sn_readb_relaxed
-#undef __sn_readw_relaxed
-#undef __sn_readl_relaxed
-#undef __sn_readq_relaxed
-
-unsigned int __sn_inb(unsigned long port)
-{
-	return ___sn_inb(port);
-}
-
-unsigned int __sn_inw(unsigned long port)
-{
-	return ___sn_inw(port);
-}
-
-unsigned int __sn_inl(unsigned long port)
-{
-	return ___sn_inl(port);
-}
-
-void __sn_outb(unsigned char val, unsigned long port)
-{
-	___sn_outb(val, port);
-}
-
-void __sn_outw(unsigned short val, unsigned long port)
-{
-	___sn_outw(val, port);
-}
-
-void __sn_outl(unsigned int val, unsigned long port)
-{
-	___sn_outl(val, port);
-}
-
-unsigned char __sn_readb(void __iomem *addr)
-{
-	return ___sn_readb(addr);
-}
-
-unsigned short __sn_readw(void __iomem *addr)
-{
-	return ___sn_readw(addr);
-}
-
-unsigned int __sn_readl(void __iomem *addr)
-{
-	return ___sn_readl(addr);
-}
-
-unsigned long __sn_readq(void __iomem *addr)
-{
-	return ___sn_readq(addr);
-}
-
-unsigned char __sn_readb_relaxed(void __iomem *addr)
-{
-	return ___sn_readb_relaxed(addr);
-}
-
-unsigned short __sn_readw_relaxed(void __iomem *addr)
-{
-	return ___sn_readw_relaxed(addr);
-}
-
-unsigned int __sn_readl_relaxed(void __iomem *addr)
-{
-	return ___sn_readl_relaxed(addr);
-}
-
-unsigned long __sn_readq_relaxed(void __iomem *addr)
-{
-	return ___sn_readq_relaxed(addr);
-}
-
-#endif
diff --git a/arch/ia64/sn/kernel/sn2/prominfo_proc.c b/arch/ia64/sn/kernel/sn2/prominfo_proc.c
deleted file mode 100644
index e15457bf21ac..000000000000
--- a/arch/ia64/sn/kernel/sn2/prominfo_proc.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999,2001-2004, 2006 Silicon Graphics, Inc.  All Rights Reserved.
- *
- * Module to export the system's Firmware Interface Tables, including
- * PROM revision numbers and banners, in /proc
- */
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/nodemask.h>
-#include <asm/io.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/addrs.h>
-
-MODULE_DESCRIPTION("PROM version reporting for /proc");
-MODULE_AUTHOR("Chad Talbott");
-MODULE_LICENSE("GPL");
-
-/* Standard Intel FIT entry types */
-#define FIT_ENTRY_FIT_HEADER	0x00	/* FIT header entry */
-#define FIT_ENTRY_PAL_B		0x01	/* PAL_B entry */
-/* Entries 0x02 through 0x0D reserved by Intel */
-#define FIT_ENTRY_PAL_A_PROC	0x0E	/* Processor-specific PAL_A entry */
-#define FIT_ENTRY_PAL_A		0x0F	/* PAL_A entry, same as... */
-#define FIT_ENTRY_PAL_A_GEN	0x0F	/* ...Generic PAL_A entry */
-#define FIT_ENTRY_UNUSED	0x7F	/* Unused (reserved by Intel?) */
-/* OEM-defined entries range from 0x10 to 0x7E. */
-#define FIT_ENTRY_SAL_A		0x10	/* SAL_A entry */
-#define FIT_ENTRY_SAL_B		0x11	/* SAL_B entry */
-#define FIT_ENTRY_SALRUNTIME	0x12	/* SAL runtime entry */
-#define FIT_ENTRY_EFI		0x1F	/* EFI entry */
-#define FIT_ENTRY_FPSWA		0x20	/* embedded fpswa entry */
-#define FIT_ENTRY_VMLINUX	0x21	/* embedded vmlinux entry */
-
-#define FIT_MAJOR_SHIFT	(32 + 8)
-#define FIT_MAJOR_MASK	((1 << 8) - 1)
-#define FIT_MINOR_SHIFT	32
-#define FIT_MINOR_MASK	((1 << 8) - 1)
-
-#define FIT_MAJOR(q)	\
-	((unsigned) ((q) >> FIT_MAJOR_SHIFT) & FIT_MAJOR_MASK)
-#define FIT_MINOR(q)	\
-	((unsigned) ((q) >> FIT_MINOR_SHIFT) & FIT_MINOR_MASK)
-
-#define FIT_TYPE_SHIFT	(32 + 16)
-#define FIT_TYPE_MASK	((1 << 7) - 1)
-
-#define FIT_TYPE(q)	\
-	((unsigned) ((q) >> FIT_TYPE_SHIFT) & FIT_TYPE_MASK)
-
-struct fit_type_map_t {
-	unsigned char type;
-	const char *name;
-};
-
-static const struct fit_type_map_t fit_entry_types[] = {
-	{FIT_ENTRY_FIT_HEADER, "FIT Header"},
-	{FIT_ENTRY_PAL_A_GEN, "Generic PAL_A"},
-	{FIT_ENTRY_PAL_A_PROC, "Processor-specific PAL_A"},
-	{FIT_ENTRY_PAL_A, "PAL_A"},
-	{FIT_ENTRY_PAL_B, "PAL_B"},
-	{FIT_ENTRY_SAL_A, "SAL_A"},
-	{FIT_ENTRY_SAL_B, "SAL_B"},
-	{FIT_ENTRY_SALRUNTIME, "SAL runtime"},
-	{FIT_ENTRY_EFI, "EFI"},
-	{FIT_ENTRY_VMLINUX, "Embedded Linux"},
-	{FIT_ENTRY_FPSWA, "Embedded FPSWA"},
-	{FIT_ENTRY_UNUSED, "Unused"},
-	{0xff, "Error"},
-};
-
-static const char *fit_type_name(unsigned char type)
-{
-	struct fit_type_map_t const *mapp;
-
-	for (mapp = fit_entry_types; mapp->type != 0xff; mapp++)
-		if (type == mapp->type)
-			return mapp->name;
-
-	if ((type > FIT_ENTRY_PAL_A) && (type < FIT_ENTRY_UNUSED))
-		return "OEM type";
-	if ((type > FIT_ENTRY_PAL_B) && (type < FIT_ENTRY_PAL_A))
-		return "Reserved";
-
-	return "Unknown type";
-}
-
-static int
-get_fit_entry(unsigned long nasid, int index, unsigned long *fentry,
-	      char *banner, int banlen)
-{
-	return ia64_sn_get_fit_compt(nasid, index, fentry, banner, banlen);
-}
-
-
-/*
- * These two routines display the FIT table for each node.
- */
-static void dump_fit_entry(struct seq_file *m, unsigned long *fentry)
-{
-	unsigned type;
-
-	type = FIT_TYPE(fentry[1]);
-	seq_printf(m, "%02x %-25s %x.%02x %016lx %u\n",
-		   type,
-		   fit_type_name(type),
-		   FIT_MAJOR(fentry[1]), FIT_MINOR(fentry[1]),
-		   fentry[0],
-		   /* mult by sixteen to get size in bytes */
-		   (unsigned)(fentry[1] & 0xffffff) * 16);
-}
-
-
-/*
- * We assume that the fit table will be small enough that we can print
- * the whole thing into one page.  (This is true for our default 16kB
- * pages -- each entry is about 60 chars wide when printed.)  I read
- * somewhere that the maximum size of the FIT is 128 entries, so we're
- * OK except for 4kB pages (and no one is going to do that on SN
- * anyway).
- */
-static int proc_fit_show(struct seq_file *m, void *v)
-{
-	unsigned long nasid = (unsigned long)m->private;
-	unsigned long fentry[2];
-	int index;
-
-	for (index=0;;index++) {
-		BUG_ON(index * 60 > PAGE_SIZE);
-		if (get_fit_entry(nasid, index, fentry, NULL, 0))
-			break;
-		dump_fit_entry(m, fentry);
-	}
-	return 0;
-}
-
-static int proc_version_show(struct seq_file *m, void *v)
-{
-	unsigned long nasid = (unsigned long)m->private;
-	unsigned long fentry[2];
-	char banner[128];
-	int index;
-
-	for (index = 0; ; index++) {
-		if (get_fit_entry(nasid, index, fentry, banner,
-				  sizeof(banner)))
-			return 0;
-		if (FIT_TYPE(fentry[1]) == FIT_ENTRY_SAL_A)
-			break;
-	}
-
-	seq_printf(m, "%x.%02x\n", FIT_MAJOR(fentry[1]), FIT_MINOR(fentry[1]));
-
-	if (banner[0])
-		seq_printf(m, "%s\n", banner);
-	return 0;
-}
-
-/* module entry points */
-int __init prominfo_init(void);
-void __exit prominfo_exit(void);
-
-module_init(prominfo_init);
-module_exit(prominfo_exit);
-
-#define NODE_NAME_LEN 11
-
-int __init prominfo_init(void)
-{
-	struct proc_dir_entry *sgi_prominfo_entry;
-	cnodeid_t cnodeid;
-
-	if (!ia64_platform_is("sn2"))
-		return 0;
-
-	sgi_prominfo_entry = proc_mkdir("sgi_prominfo", NULL);
-	if (!sgi_prominfo_entry)
-		return -ENOMEM;
-
-	for_each_online_node(cnodeid) {
-		struct proc_dir_entry *dir;
-		unsigned long nasid;
-		char name[NODE_NAME_LEN];
-
-		sprintf(name, "node%d", cnodeid);
-		dir = proc_mkdir(name, sgi_prominfo_entry);
-		if (!dir)
-			continue;
-		nasid = cnodeid_to_nasid(cnodeid);
-		proc_create_single_data("fit", 0, dir, proc_fit_show, 
-				(void *)nasid);
-		proc_create_single_data("version", 0, dir, proc_version_show,
-				(void *)nasid);
-	}
-	return 0;
-}
-
-void __exit prominfo_exit(void)
-{
-	remove_proc_subtree("sgi_prominfo", NULL);
-}
diff --git a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
deleted file mode 100644
index bebbcc4f8dd4..000000000000
--- a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <asm/types.h>
-#include <asm/sn/shub_mmr.h>
-
-#define DEADLOCKBIT	SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
-#define WRITECOUNTMASK	SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK
-#define ALIAS_OFFSET	8
-
-
-	.global	sn2_ptc_deadlock_recovery_core
-	.proc  	sn2_ptc_deadlock_recovery_core
-
-sn2_ptc_deadlock_recovery_core:
-	.regstk 6,0,0,0
-
-	ptc0  	 = in0
-	data0 	 = in1
-	ptc1  	 = in2
-	data1 	 = in3
-	piowc 	 = in4
-	zeroval  = in5
-	piowcphy = r30
-	psrsave  = r2
-	scr1	 = r16
-	scr2	 = r17
-	mask	 = r18
-
-
-	extr.u	piowcphy=piowc,0,61;;	// Convert piowc to uncached physical address
-	dep	piowcphy=-1,piowcphy,63,1
-	movl	mask=WRITECOUNTMASK
-	mov	r8=r0
-
-1:
-	cmp.ne  p8,p9=r0,ptc1		// Test for shub type (ptc1 non-null on shub1)
-					// p8 = 1 if shub1, p9 = 1 if shub2
-
-	add	scr2=ALIAS_OFFSET,piowc	// Address of WRITE_STATUS alias register 
-	mov	scr1=7;;		// Clear DEADLOCK, WRITE_ERROR, MULTI_WRITE_ERROR
-(p8)	st8.rel	[scr2]=scr1;;
-(p9)	ld8.acq	scr1=[scr2];;
-
-5:	ld8.acq	scr1=[piowc];;		// Wait for PIOs to complete.
-	hint	@pause
-	and	scr2=scr1,mask;;	// mask of writecount bits
-	cmp.ne	p6,p0=zeroval,scr2
-(p6)	br.cond.sptk 5b
-	
-
-
-	////////////// BEGIN PHYSICAL MODE ////////////////////
-	mov psrsave=psr			// Disable IC (no PMIs)
-	rsm psr.i | psr.dt | psr.ic;;
-	srlz.i;;
-
-	st8.rel [ptc0]=data0		// Write PTC0 & wait for completion.
-
-5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.
-	hint	@pause
-	and	scr2=scr1,mask;;	// mask of writecount bits
-	cmp.ne	p6,p0=zeroval,scr2
-(p6)	br.cond.sptk 5b;;
-
-	tbit.nz	p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK
-(p7)	cmp.ne p7,p0=r0,ptc1;;		// Test for non-null ptc1
-	
-(p7)	st8.rel [ptc1]=data1;;		// Now write PTC1.
-
-5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.
-	hint	@pause
-	and	scr2=scr1,mask;;	// mask of writecount bits
-	cmp.ne	p6,p0=zeroval,scr2
-(p6)	br.cond.sptk 5b
-	
-	tbit.nz	p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK
-
-	mov psr.l=psrsave;;		// Reenable IC
-	srlz.i;;
-	////////////// END   PHYSICAL MODE ////////////////////
-
-(p8)	add	r8=1,r8
-(p8)	br.cond.spnt 1b;;		// Repeat if DEADLOCK occurred.
-
-	br.ret.sptk	rp
-	.endp sn2_ptc_deadlock_recovery_core
diff --git a/arch/ia64/sn/kernel/sn2/sn2_smp.c b/arch/ia64/sn/kernel/sn2/sn2_smp.c
deleted file mode 100644
index b510f4f17fd4..000000000000
--- a/arch/ia64/sn/kernel/sn2/sn2_smp.c
+++ /dev/null
@@ -1,577 +0,0 @@
-/*
- * SN2 Platform specific SMP Support
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/threads.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/mmzone.h>
-#include <linux/module.h>
-#include <linux/bitops.h>
-#include <linux/nodemask.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-#include <asm/processor.h>
-#include <asm/irq.h>
-#include <asm/sal.h>
-#include <asm/delay.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <asm/tlb.h>
-#include <asm/numa.h>
-#include <asm/hw_irq.h>
-#include <asm/current.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/shub_mmr.h>
-#include <asm/sn/nodepda.h>
-#include <asm/sn/rw_mmr.h>
-#include <asm/sn/sn_feature_sets.h>
-
-DEFINE_PER_CPU(struct ptc_stats, ptcstats);
-DECLARE_PER_CPU(struct ptc_stats, ptcstats);
-
-static  __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
-
-/* 0 = old algorithm (no IPI flushes), 1 = ipi deadlock flush, 2 = ipi instead of SHUB ptc, >2 = always ipi */
-static int sn2_flush_opt = 0;
-
-extern unsigned long
-sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
-			       volatile unsigned long *, unsigned long,
-			       volatile unsigned long *, unsigned long);
-void
-sn2_ptc_deadlock_recovery(nodemask_t, short, short, int,
-			  volatile unsigned long *, unsigned long,
-			  volatile unsigned long *, unsigned long);
-
-/*
- * Note: some is the following is captured here to make degugging easier
- * (the macros make more sense if you see the debug patch - not posted)
- */
-#define sn2_ptctest	0
-#define local_node_uses_ptc_ga(sh1)	((sh1) ? 1 : 0)
-#define max_active_pio(sh1)		((sh1) ? 32 : 7)
-#define reset_max_active_on_deadlock()	1
-#define PTC_LOCK(sh1)			((sh1) ? &sn2_global_ptc_lock : &sn_nodepda->ptc_lock)
-
-struct ptc_stats {
-	unsigned long ptc_l;
-	unsigned long change_rid;
-	unsigned long shub_ptc_flushes;
-	unsigned long nodes_flushed;
-	unsigned long deadlocks;
-	unsigned long deadlocks2;
-	unsigned long lock_itc_clocks;
-	unsigned long shub_itc_clocks;
-	unsigned long shub_itc_clocks_max;
-	unsigned long shub_ptc_flushes_not_my_mm;
-	unsigned long shub_ipi_flushes;
-	unsigned long shub_ipi_flushes_itc_clocks;
-};
-
-#define sn2_ptctest	0
-
-static inline unsigned long wait_piowc(void)
-{
-	volatile unsigned long *piows;
-	unsigned long zeroval, ws;
-
-	piows = pda->pio_write_status_addr;
-	zeroval = pda->pio_write_status_val;
-	do {
-		cpu_relax();
-	} while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
-	return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
-}
-
-/**
- * sn_migrate - SN-specific task migration actions
- * @task: Task being migrated to new CPU
- *
- * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
- * Context switching user threads which have memory-mapped MMIO may cause
- * PIOs to issue from separate CPUs, thus the PIO writes must be drained
- * from the previous CPU's Shub before execution resumes on the new CPU.
- */
-void sn_migrate(struct task_struct *task)
-{
-	pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
-	volatile unsigned long *adr = last_pda->pio_write_status_addr;
-	unsigned long val = last_pda->pio_write_status_val;
-
-	/* Drain PIO writes from old CPU's Shub */
-	while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
-			!= val))
-		cpu_relax();
-}
-
-static void
-sn2_ipi_flush_all_tlb(struct mm_struct *mm)
-{
-	unsigned long itc;
-
-	itc = ia64_get_itc();
-	smp_flush_tlb_cpumask(*mm_cpumask(mm));
-	itc = ia64_get_itc() - itc;
-	__this_cpu_add(ptcstats.shub_ipi_flushes_itc_clocks, itc);
-	__this_cpu_inc(ptcstats.shub_ipi_flushes);
-}
-
-/**
- * sn2_global_tlb_purge - globally purge translation cache of virtual address range
- * @mm: mm_struct containing virtual address range
- * @start: start of virtual address range
- * @end: end of virtual address range
- * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
- *
- * Purges the translation caches of all processors of the given virtual address
- * range.
- *
- * Note:
- * 	- cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
- * 	- cpu_vm_mask is converted into a nodemask of the nodes containing the
- * 	  cpus in cpu_vm_mask.
- *	- if only one bit is set in cpu_vm_mask & it is the current cpu & the
- *	  process is purging its own virtual address range, then only the
- *	  local TLB needs to be flushed. This flushing can be done using
- *	  ptc.l. This is the common case & avoids the global spinlock.
- *	- if multiple cpus have loaded the context, then flushing has to be
- *	  done with ptc.g/MMRs under protection of the global ptc_lock.
- */
-
-void
-sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
-		     unsigned long end, unsigned long nbits)
-{
-	int i, ibegin, shub1, cnode, mynasid, cpu, lcpu = 0, nasid;
-	int mymm = (mm == current->active_mm && mm == current->mm);
-	int use_cpu_ptcga;
-	volatile unsigned long *ptc0, *ptc1;
-	unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value, old_rr = 0;
-	short nix;
-	nodemask_t nodes_flushed;
-	int active, max_active, deadlock, flush_opt = sn2_flush_opt;
-
-	if (flush_opt > 2) {
-		sn2_ipi_flush_all_tlb(mm);
-		return;
-	}
-
-	nodes_clear(nodes_flushed);
-	i = 0;
-
-	for_each_cpu(cpu, mm_cpumask(mm)) {
-		cnode = cpu_to_node(cpu);
-		node_set(cnode, nodes_flushed);
-		lcpu = cpu;
-		i++;
-	}
-
-	if (i == 0)
-		return;
-
-	preempt_disable();
-
-	if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
-		do {
-			ia64_ptcl(start, nbits << 2);
-			start += (1UL << nbits);
-		} while (start < end);
-		ia64_srlz_i();
-		__this_cpu_inc(ptcstats.ptc_l);
-		preempt_enable();
-		return;
-	}
-
-	if (atomic_read(&mm->mm_users) == 1 && mymm) {
-		flush_tlb_mm(mm);
-		__this_cpu_inc(ptcstats.change_rid);
-		preempt_enable();
-		return;
-	}
-
-	if (flush_opt == 2) {
-		sn2_ipi_flush_all_tlb(mm);
-		preempt_enable();
-		return;
-	}
-
-	itc = ia64_get_itc();
-	nix = nodes_weight(nodes_flushed);
-
-	rr_value = (mm->context << 3) | REGION_NUMBER(start);
-
-	shub1 = is_shub1();
-	if (shub1) {
-		data0 = (1UL << SH1_PTC_0_A_SHFT) |
-		    	(nbits << SH1_PTC_0_PS_SHFT) |
-			(rr_value << SH1_PTC_0_RID_SHFT) |
-		    	(1UL << SH1_PTC_0_START_SHFT);
-		ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
-		ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
-	} else {
-		data0 = (1UL << SH2_PTC_A_SHFT) |
-			(nbits << SH2_PTC_PS_SHFT) |
-		    	(1UL << SH2_PTC_START_SHFT);
-		ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC + 
-			(rr_value << SH2_PTC_RID_SHFT));
-		ptc1 = NULL;
-	}
-	
-
-	mynasid = get_nasid();
-	use_cpu_ptcga = local_node_uses_ptc_ga(shub1);
-	max_active = max_active_pio(shub1);
-
-	itc = ia64_get_itc();
-	spin_lock_irqsave(PTC_LOCK(shub1), flags);
-	itc2 = ia64_get_itc();
-
-	__this_cpu_add(ptcstats.lock_itc_clocks, itc2 - itc);
-	__this_cpu_inc(ptcstats.shub_ptc_flushes);
-	__this_cpu_add(ptcstats.nodes_flushed, nix);
-	if (!mymm)
-		 __this_cpu_inc(ptcstats.shub_ptc_flushes_not_my_mm);
-
-	if (use_cpu_ptcga && !mymm) {
-		old_rr = ia64_get_rr(start);
-		ia64_set_rr(start, (old_rr & 0xff) | (rr_value << 8));
-		ia64_srlz_d();
-	}
-
-	wait_piowc();
-	do {
-		if (shub1)
-			data1 = start | (1UL << SH1_PTC_1_START_SHFT);
-		else
-			data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
-		deadlock = 0;
-		active = 0;
-		ibegin = 0;
-		i = 0;
-		for_each_node_mask(cnode, nodes_flushed) {
-			nasid = cnodeid_to_nasid(cnode);
-			if (use_cpu_ptcga && unlikely(nasid == mynasid)) {
-				ia64_ptcga(start, nbits << 2);
-				ia64_srlz_i();
-			} else {
-				ptc0 = CHANGE_NASID(nasid, ptc0);
-				if (ptc1)
-					ptc1 = CHANGE_NASID(nasid, ptc1);
-				pio_atomic_phys_write_mmrs(ptc0, data0, ptc1, data1);
-				active++;
-			}
-			if (active >= max_active || i == (nix - 1)) {
-				if ((deadlock = wait_piowc())) {
-					if (flush_opt == 1)
-						goto done;
-					sn2_ptc_deadlock_recovery(nodes_flushed, ibegin, i, mynasid, ptc0, data0, ptc1, data1);
-					if (reset_max_active_on_deadlock())
-						max_active = 1;
-				}
-				active = 0;
-				ibegin = i + 1;
-			}
-			i++;
-		}
-		start += (1UL << nbits);
-	} while (start < end);
-
-done:
-	itc2 = ia64_get_itc() - itc2;
-	__this_cpu_add(ptcstats.shub_itc_clocks, itc2);
-	if (itc2 > __this_cpu_read(ptcstats.shub_itc_clocks_max))
-		__this_cpu_write(ptcstats.shub_itc_clocks_max, itc2);
-
-	if (old_rr) {
-		ia64_set_rr(start, old_rr);
-		ia64_srlz_d();
-	}
-
-	spin_unlock_irqrestore(PTC_LOCK(shub1), flags);
-
-	if (flush_opt == 1 && deadlock) {
-		__this_cpu_inc(ptcstats.deadlocks);
-		sn2_ipi_flush_all_tlb(mm);
-	}
-
-	preempt_enable();
-}
-
-/*
- * sn2_ptc_deadlock_recovery
- *
- * Recover from PTC deadlocks conditions. Recovery requires stepping thru each 
- * TLB flush transaction.  The recovery sequence is somewhat tricky & is
- * coded in assembly language.
- */
-
-void
-sn2_ptc_deadlock_recovery(nodemask_t nodes, short ib, short ie, int mynasid,
-			  volatile unsigned long *ptc0, unsigned long data0,
-			  volatile unsigned long *ptc1, unsigned long data1)
-{
-	short nasid, i;
-	int cnode;
-	unsigned long *piows, zeroval, n;
-
-	__this_cpu_inc(ptcstats.deadlocks);
-
-	piows = (unsigned long *) pda->pio_write_status_addr;
-	zeroval = pda->pio_write_status_val;
-
-	i = 0;
-	for_each_node_mask(cnode, nodes) {
-		if (i < ib)
-			goto next;
-
-		if (i > ie)
-			break;
-
-		nasid = cnodeid_to_nasid(cnode);
-		if (local_node_uses_ptc_ga(is_shub1()) && nasid == mynasid)
-			goto next;
-
-		ptc0 = CHANGE_NASID(nasid, ptc0);
-		if (ptc1)
-			ptc1 = CHANGE_NASID(nasid, ptc1);
-
-		n = sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
-		__this_cpu_add(ptcstats.deadlocks2, n);
-next:
-		i++;
-	}
-
-}
-
-/**
- * sn_send_IPI_phys - send an IPI to a Nasid and slice
- * @nasid: nasid to receive the interrupt (may be outside partition)
- * @physid: physical cpuid to receive the interrupt.
- * @vector: command to send
- * @delivery_mode: delivery mechanism
- *
- * Sends an IPI (interprocessor interrupt) to the processor specified by
- * @physid
- *
- * @delivery_mode can be one of the following
- *
- * %IA64_IPI_DM_INT - pend an interrupt
- * %IA64_IPI_DM_PMI - pend a PMI
- * %IA64_IPI_DM_NMI - pend an NMI
- * %IA64_IPI_DM_INIT - pend an INIT interrupt
- */
-void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
-{
-	long val;
-	unsigned long flags = 0;
-	volatile long *p;
-
-	p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
-	val = (1UL << SH_IPI_INT_SEND_SHFT) |
-	    (physid << SH_IPI_INT_PID_SHFT) |
-	    ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
-	    ((long)vector << SH_IPI_INT_IDX_SHFT) |
-	    (0x000feeUL << SH_IPI_INT_BASE_SHFT);
-
-	mb();
-	if (enable_shub_wars_1_1()) {
-		spin_lock_irqsave(&sn2_global_ptc_lock, flags);
-	}
-	pio_phys_write_mmr(p, val);
-	if (enable_shub_wars_1_1()) {
-		wait_piowc();
-		spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
-	}
-
-}
-
-EXPORT_SYMBOL(sn_send_IPI_phys);
-
-/**
- * sn2_send_IPI - send an IPI to a processor
- * @cpuid: target of the IPI
- * @vector: command to send
- * @delivery_mode: delivery mechanism
- * @redirect: redirect the IPI?
- *
- * Sends an IPI (InterProcessor Interrupt) to the processor specified by
- * @cpuid.  @vector specifies the command to send, while @delivery_mode can 
- * be one of the following
- *
- * %IA64_IPI_DM_INT - pend an interrupt
- * %IA64_IPI_DM_PMI - pend a PMI
- * %IA64_IPI_DM_NMI - pend an NMI
- * %IA64_IPI_DM_INIT - pend an INIT interrupt
- */
-void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
-{
-	long physid;
-	int nasid;
-
-	physid = cpu_physical_id(cpuid);
-	nasid = cpuid_to_nasid(cpuid);
-
-	/* the following is used only when starting cpus at boot time */
-	if (unlikely(nasid == -1))
-		ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
-
-	sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-/**
- * sn_cpu_disable_allowed - Determine if a CPU can be disabled.
- * @cpu - CPU that is requested to be disabled.
- *
- * CPU disable is only allowed on SHub2 systems running with a PROM
- * that supports CPU disable. It is not permitted to disable the boot processor.
- */
-bool sn_cpu_disable_allowed(int cpu)
-{
-	if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT)) {
-		if (cpu != 0)
-			return true;
-		else
-			printk(KERN_WARNING
-			      "Disabling the boot processor is not allowed.\n");
-
-	} else
-		printk(KERN_WARNING
-		       "CPU disable is not supported on this system.\n");
-
-	return false;
-}
-#endif /* CONFIG_HOTPLUG_CPU */
-
-#ifdef CONFIG_PROC_FS
-
-#define PTC_BASENAME	"sgi_sn/ptc_statistics"
-
-static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
-{
-	if (*offset < nr_cpu_ids)
-		return offset;
-	return NULL;
-}
-
-static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
-{
-	(*offset)++;
-	if (*offset < nr_cpu_ids)
-		return offset;
-	return NULL;
-}
-
-static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
-{
-}
-
-static int sn2_ptc_seq_show(struct seq_file *file, void *data)
-{
-	struct ptc_stats *stat;
-	int cpu;
-
-	cpu = *(loff_t *) data;
-
-	if (!cpu) {
-		seq_printf(file,
-			   "# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2 ipi_fluches ipi_nsec\n");
-		seq_printf(file, "# ptctest %d, flushopt %d\n", sn2_ptctest, sn2_flush_opt);
-	}
-
-	if (cpu < nr_cpu_ids && cpu_online(cpu)) {
-		stat = &per_cpu(ptcstats, cpu);
-		seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
-				stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
-				stat->deadlocks,
-				1000 * stat->lock_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
-				1000 * stat->shub_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
-				1000 * stat->shub_itc_clocks_max / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
-				stat->shub_ptc_flushes_not_my_mm,
-				stat->deadlocks2,
-				stat->shub_ipi_flushes,
-				1000 * stat->shub_ipi_flushes_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec);
-	}
-	return 0;
-}
-
-static ssize_t sn2_ptc_proc_write(struct file *file, const char __user *user, size_t count, loff_t *data)
-{
-	int cpu;
-	char optstr[64];
-
-	if (count == 0 || count > sizeof(optstr))
-		return -EINVAL;
-	if (copy_from_user(optstr, user, count))
-		return -EFAULT;
-	optstr[count - 1] = '\0';
-	sn2_flush_opt = simple_strtoul(optstr, NULL, 0);
-
-	for_each_online_cpu(cpu)
-		memset(&per_cpu(ptcstats, cpu), 0, sizeof(struct ptc_stats));
-
-	return count;
-}
-
-static const struct seq_operations sn2_ptc_seq_ops = {
-	.start = sn2_ptc_seq_start,
-	.next = sn2_ptc_seq_next,
-	.stop = sn2_ptc_seq_stop,
-	.show = sn2_ptc_seq_show
-};
-
-static int sn2_ptc_proc_open(struct inode *inode, struct file *file)
-{
-	return seq_open(file, &sn2_ptc_seq_ops);
-}
-
-static const struct file_operations proc_sn2_ptc_operations = {
-	.open = sn2_ptc_proc_open,
-	.read = seq_read,
-	.write = sn2_ptc_proc_write,
-	.llseek = seq_lseek,
-	.release = seq_release,
-};
-
-static struct proc_dir_entry *proc_sn2_ptc;
-
-static int __init sn2_ptc_init(void)
-{
-	if (!ia64_platform_is("sn2"))
-		return 0;
-
-	proc_sn2_ptc = proc_create(PTC_BASENAME, 0444,
-				   NULL, &proc_sn2_ptc_operations);
-	if (!proc_sn2_ptc) {
-		printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
-		return -EINVAL;
-	}
-	spin_lock_init(&sn2_global_ptc_lock);
-	return 0;
-}
-
-static void __exit sn2_ptc_exit(void)
-{
-	remove_proc_entry(PTC_BASENAME, NULL);
-}
-
-module_init(sn2_ptc_init);
-module_exit(sn2_ptc_exit);
-#endif /* CONFIG_PROC_FS */
-
diff --git a/arch/ia64/sn/kernel/sn2/sn_hwperf.c b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
deleted file mode 100644
index 55febd65911a..000000000000
--- a/arch/ia64/sn/kernel/sn2/sn_hwperf.c
+++ /dev/null
@@ -1,1004 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004-2006 Silicon Graphics, Inc. All rights reserved.
- *
- * SGI Altix topology and hardware performance monitoring API.
- * Mark Goodwin <markgw@sgi.com>. 
- *
- * Creates /proc/sgi_sn/sn_topology (read-only) to export
- * info about Altix nodes, routers, CPUs and NumaLink
- * interconnection/topology.
- *
- * Also creates a dynamic misc device named "sn_hwperf"
- * that supports an ioctl interface to call down into SAL
- * to discover hw objects, topology and to read/write
- * memory mapped registers, e.g. for performance monitoring.
- * The "sn_hwperf" device is registered only after the procfs
- * file is first opened, i.e. only if/when it's needed. 
- *
- * This API is used by SGI Performance Co-Pilot and other
- * tools, see http://oss.sgi.com/projects/pcp
- */
-
-#include <linux/fs.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-#include <linux/vmalloc.h>
-#include <linux/seq_file.h>
-#include <linux/miscdevice.h>
-#include <linux/utsname.h>
-#include <linux/cpumask.h>
-#include <linux/nodemask.h>
-#include <linux/smp.h>
-#include <linux/mutex.h>
-
-#include <asm/processor.h>
-#include <asm/topology.h>
-#include <linux/uaccess.h>
-#include <asm/sal.h>
-#include <asm/sn/io.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/module.h>
-#include <asm/sn/geo.h>
-#include <asm/sn/sn2/sn_hwperf.h>
-#include <asm/sn/addrs.h>
-
-static void *sn_hwperf_salheap = NULL;
-static int sn_hwperf_obj_cnt = 0;
-static nasid_t sn_hwperf_master_nasid = INVALID_NASID;
-static int sn_hwperf_init(void);
-static DEFINE_MUTEX(sn_hwperf_init_mutex);
-
-#define cnode_possible(n)	((n) < num_cnodes)
-
-static int sn_hwperf_enum_objects(int *nobj, struct sn_hwperf_object_info **ret)
-{
-	int e;
-	u64 sz;
-	struct sn_hwperf_object_info *objbuf = NULL;
-
-	if ((e = sn_hwperf_init()) < 0) {
-		printk(KERN_ERR "sn_hwperf_init failed: err %d\n", e);
-		goto out;
-	}
-
-	sz = sn_hwperf_obj_cnt * sizeof(struct sn_hwperf_object_info);
-	objbuf = vmalloc(sz);
-	if (objbuf == NULL) {
-		printk("sn_hwperf_enum_objects: vmalloc(%d) failed\n", (int)sz);
-		e = -ENOMEM;
-		goto out;
-	}
-
-	e = ia64_sn_hwperf_op(sn_hwperf_master_nasid, SN_HWPERF_ENUM_OBJECTS,
-		0, sz, (u64) objbuf, 0, 0, NULL);
-	if (e != SN_HWPERF_OP_OK) {
-		e = -EINVAL;
-		vfree(objbuf);
-	}
-
-out:
-	*nobj = sn_hwperf_obj_cnt;
-	*ret = objbuf;
-	return e;
-}
-
-static int sn_hwperf_location_to_bpos(char *location,
-	int *rack, int *bay, int *slot, int *slab)
-{
-	char type;
-
-	/* first scan for an old style geoid string */
-	if (sscanf(location, "%03d%c%02d#%d",
-		rack, &type, bay, slab) == 4)
-		*slot = 0; 
-	else /* scan for a new bladed geoid string */
-	if (sscanf(location, "%03d%c%02d^%02d#%d",
-		rack, &type, bay, slot, slab) != 5)
-		return -1; 
-	/* success */
-	return 0;
-}
-
-static int sn_hwperf_geoid_to_cnode(char *location)
-{
-	int cnode;
-	geoid_t geoid;
-	moduleid_t module_id;
-	int rack, bay, slot, slab;
-	int this_rack, this_bay, this_slot, this_slab;
-
-	if (sn_hwperf_location_to_bpos(location, &rack, &bay, &slot, &slab))
-		return -1;
-
-	/*
-	 * FIXME: replace with cleaner for_each_XXX macro which addresses
-	 * both compute and IO nodes once ACPI3.0 is available.
-	 */
-	for (cnode = 0; cnode < num_cnodes; cnode++) {
-		geoid = cnodeid_get_geoid(cnode);
-		module_id = geo_module(geoid);
-		this_rack = MODULE_GET_RACK(module_id);
-		this_bay = MODULE_GET_BPOS(module_id);
-		this_slot = geo_slot(geoid);
-		this_slab = geo_slab(geoid);
-		if (rack == this_rack && bay == this_bay &&
-			slot == this_slot && slab == this_slab) {
-			break;
-		}
-	}
-
-	return cnode_possible(cnode) ? cnode : -1;
-}
-
-static int sn_hwperf_obj_to_cnode(struct sn_hwperf_object_info * obj)
-{
-	if (!SN_HWPERF_IS_NODE(obj) && !SN_HWPERF_IS_IONODE(obj))
-		BUG();
-	if (SN_HWPERF_FOREIGN(obj))
-		return -1;
-	return sn_hwperf_geoid_to_cnode(obj->location);
-}
-
-static int sn_hwperf_generic_ordinal(struct sn_hwperf_object_info *obj,
-				struct sn_hwperf_object_info *objs)
-{
-	int ordinal;
-	struct sn_hwperf_object_info *p;
-
-	for (ordinal=0, p=objs; p != obj; p++) {
-		if (SN_HWPERF_FOREIGN(p))
-			continue;
-		if (SN_HWPERF_SAME_OBJTYPE(p, obj))
-			ordinal++;
-	}
-
-	return ordinal;
-}
-
-static const char *slabname_node =	"node"; /* SHub asic */
-static const char *slabname_ionode =	"ionode"; /* TIO asic */
-static const char *slabname_router =	"router"; /* NL3R or NL4R */
-static const char *slabname_other =	"other"; /* unknown asic */
-
-static const char *sn_hwperf_get_slabname(struct sn_hwperf_object_info *obj,
-			struct sn_hwperf_object_info *objs, int *ordinal)
-{
-	int isnode;
-	const char *slabname = slabname_other;
-
-	if ((isnode = SN_HWPERF_IS_NODE(obj)) || SN_HWPERF_IS_IONODE(obj)) {
-	    	slabname = isnode ? slabname_node : slabname_ionode;
-		*ordinal = sn_hwperf_obj_to_cnode(obj);
-	}
-	else {
-		*ordinal = sn_hwperf_generic_ordinal(obj, objs);
-		if (SN_HWPERF_IS_ROUTER(obj))
-			slabname = slabname_router;
-	}
-
-	return slabname;
-}
-
-static void print_pci_topology(struct seq_file *s)
-{
-	char *p;
-	size_t sz;
-	int e;
-
-	for (sz = PAGE_SIZE; sz < 16 * PAGE_SIZE; sz += PAGE_SIZE) {
-		if (!(p = kmalloc(sz, GFP_KERNEL)))
-			break;
-		e = ia64_sn_ioif_get_pci_topology(__pa(p), sz);
-		if (e == SALRET_OK)
-			seq_puts(s, p);
-		kfree(p);
-		if (e == SALRET_OK || e == SALRET_NOT_IMPLEMENTED)
-			break;
-	}
-}
-
-static inline int sn_hwperf_has_cpus(cnodeid_t node)
-{
-	return node < MAX_NUMNODES && node_online(node) && nr_cpus_node(node);
-}
-
-static inline int sn_hwperf_has_mem(cnodeid_t node)
-{
-	return node < MAX_NUMNODES && node_online(node) && NODE_DATA(node)->node_present_pages;
-}
-
-static struct sn_hwperf_object_info *
-sn_hwperf_findobj_id(struct sn_hwperf_object_info *objbuf,
-	int nobj, int id)
-{
-	int i;
-	struct sn_hwperf_object_info *p = objbuf;
-
-	for (i=0; i < nobj; i++, p++) {
-		if (p->id == id)
-			return p;
-	}
-
-	return NULL;
-
-}
-
-static int sn_hwperf_get_nearest_node_objdata(struct sn_hwperf_object_info *objbuf,
-	int nobj, cnodeid_t node, cnodeid_t *near_mem_node, cnodeid_t *near_cpu_node)
-{
-	int e;
-	struct sn_hwperf_object_info *nodeobj = NULL;
-	struct sn_hwperf_object_info *op;
-	struct sn_hwperf_object_info *dest;
-	struct sn_hwperf_object_info *router;
-	struct sn_hwperf_port_info ptdata[16];
-	int sz, i, j;
-	cnodeid_t c;
-	int found_mem = 0;
-	int found_cpu = 0;
-
-	if (!cnode_possible(node))
-		return -EINVAL;
-
-	if (sn_hwperf_has_cpus(node)) {
-		if (near_cpu_node)
-			*near_cpu_node = node;
-		found_cpu++;
-	}
-
-	if (sn_hwperf_has_mem(node)) {
-		if (near_mem_node)
-			*near_mem_node = node;
-		found_mem++;
-	}
-
-	if (found_cpu && found_mem)
-		return 0; /* trivially successful */
-
-	/* find the argument node object */
-	for (i=0, op=objbuf; i < nobj; i++, op++) {
-		if (!SN_HWPERF_IS_NODE(op) && !SN_HWPERF_IS_IONODE(op))
-			continue;
-		if (node == sn_hwperf_obj_to_cnode(op)) {
-			nodeobj = op;
-			break;
-		}
-	}
-	if (!nodeobj) {
-		e = -ENOENT;
-		goto err;
-	}
-
-	/* get it's interconnect topology */
-	sz = op->ports * sizeof(struct sn_hwperf_port_info);
-	BUG_ON(sz > sizeof(ptdata));
-	e = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
-			      SN_HWPERF_ENUM_PORTS, nodeobj->id, sz,
-			      (u64)&ptdata, 0, 0, NULL);
-	if (e != SN_HWPERF_OP_OK) {
-		e = -EINVAL;
-		goto err;
-	}
-
-	/* find nearest node with cpus and nearest memory */
-	for (router=NULL, j=0; j < op->ports; j++) {
-		dest = sn_hwperf_findobj_id(objbuf, nobj, ptdata[j].conn_id);
-		if (dest && SN_HWPERF_IS_ROUTER(dest))
-			router = dest;
-		if (!dest || SN_HWPERF_FOREIGN(dest) ||
-		    !SN_HWPERF_IS_NODE(dest) || SN_HWPERF_IS_IONODE(dest)) {
-			continue;
-		}
-		c = sn_hwperf_obj_to_cnode(dest);
-		if (!found_cpu && sn_hwperf_has_cpus(c)) {
-			if (near_cpu_node)
-				*near_cpu_node = c;
-			found_cpu++;
-		}
-		if (!found_mem && sn_hwperf_has_mem(c)) {
-			if (near_mem_node)
-				*near_mem_node = c;
-			found_mem++;
-		}
-	}
-
-	if (router && (!found_cpu || !found_mem)) {
-		/* search for a node connected to the same router */
-		sz = router->ports * sizeof(struct sn_hwperf_port_info);
-		BUG_ON(sz > sizeof(ptdata));
-		e = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
-				      SN_HWPERF_ENUM_PORTS, router->id, sz,
-				      (u64)&ptdata, 0, 0, NULL);
-		if (e != SN_HWPERF_OP_OK) {
-			e = -EINVAL;
-			goto err;
-		}
-		for (j=0; j < router->ports; j++) {
-			dest = sn_hwperf_findobj_id(objbuf, nobj,
-				ptdata[j].conn_id);
-			if (!dest || dest->id == node ||
-			    SN_HWPERF_FOREIGN(dest) ||
-			    !SN_HWPERF_IS_NODE(dest) ||
-			    SN_HWPERF_IS_IONODE(dest)) {
-				continue;
-			}
-			c = sn_hwperf_obj_to_cnode(dest);
-			if (!found_cpu && sn_hwperf_has_cpus(c)) {
-				if (near_cpu_node)
-					*near_cpu_node = c;
-				found_cpu++;
-			}
-			if (!found_mem && sn_hwperf_has_mem(c)) {
-				if (near_mem_node)
-					*near_mem_node = c;
-				found_mem++;
-			}
-			if (found_cpu && found_mem)
-				break;
-		}
-	}
-
-	if (!found_cpu || !found_mem) {
-		/* resort to _any_ node with CPUs and memory */
-		for (i=0, op=objbuf; i < nobj; i++, op++) {
-			if (SN_HWPERF_FOREIGN(op) ||
-			    SN_HWPERF_IS_IONODE(op) ||
-			    !SN_HWPERF_IS_NODE(op)) {
-				continue;
-			}
-			c = sn_hwperf_obj_to_cnode(op);
-			if (!found_cpu && sn_hwperf_has_cpus(c)) {
-				if (near_cpu_node)
-					*near_cpu_node = c;
-				found_cpu++;
-			}
-			if (!found_mem && sn_hwperf_has_mem(c)) {
-				if (near_mem_node)
-					*near_mem_node = c;
-				found_mem++;
-			}
-			if (found_cpu && found_mem)
-				break;
-		}
-	}
-
-	if (!found_cpu || !found_mem)
-		e = -ENODATA;
-
-err:
-	return e;
-}
-
-
-static int sn_topology_show(struct seq_file *s, void *d)
-{
-	int sz;
-	int pt;
-	int e = 0;
-	int i;
-	int j;
-	const char *slabname;
-	int ordinal;
-	char slice;
-	struct cpuinfo_ia64 *c;
-	struct sn_hwperf_port_info *ptdata;
-	struct sn_hwperf_object_info *p;
-	struct sn_hwperf_object_info *obj = d;	/* this object */
-	struct sn_hwperf_object_info *objs = s->private; /* all objects */
-	u8 shubtype;
-	u8 system_size;
-	u8 sharing_size;
-	u8 partid;
-	u8 coher;
-	u8 nasid_shift;
-	u8 region_size;
-	u16 nasid_mask;
-	int nasid_msb;
-
-	if (obj == objs) {
-		seq_printf(s, "# sn_topology version 2\n");
-		seq_printf(s, "# objtype ordinal location partition"
-			" [attribute value [, ...]]\n");
-
-		if (ia64_sn_get_sn_info(0,
-			&shubtype, &nasid_mask, &nasid_shift, &system_size,
-			&sharing_size, &partid, &coher, &region_size))
-			BUG();
-		for (nasid_msb=63; nasid_msb > 0; nasid_msb--) {
-			if (((u64)nasid_mask << nasid_shift) & (1ULL << nasid_msb))
-				break;
-		}
-		seq_printf(s, "partition %u %s local "
-			"shubtype %s, "
-			"nasid_mask 0x%016llx, "
-			"nasid_bits %d:%d, "
-			"system_size %d, "
-			"sharing_size %d, "
-			"coherency_domain %d, "
-			"region_size %d\n",
-
-			partid, utsname()->nodename,
-			shubtype ? "shub2" : "shub1", 
-			(u64)nasid_mask << nasid_shift, nasid_msb, nasid_shift,
-			system_size, sharing_size, coher, region_size);
-
-		print_pci_topology(s);
-	}
-
-	if (SN_HWPERF_FOREIGN(obj)) {
-		/* private in another partition: not interesting */
-		return 0;
-	}
-
-	for (i = 0; i < SN_HWPERF_MAXSTRING && obj->name[i]; i++) {
-		if (obj->name[i] == ' ')
-			obj->name[i] = '_';
-	}
-
-	slabname = sn_hwperf_get_slabname(obj, objs, &ordinal);
-	seq_printf(s, "%s %d %s %s asic %s", slabname, ordinal, obj->location,
-		obj->sn_hwp_this_part ? "local" : "shared", obj->name);
-
-	if (ordinal < 0 || (!SN_HWPERF_IS_NODE(obj) && !SN_HWPERF_IS_IONODE(obj)))
-		seq_putc(s, '\n');
-	else {
-		cnodeid_t near_mem = -1;
-		cnodeid_t near_cpu = -1;
-
-		seq_printf(s, ", nasid 0x%x", cnodeid_to_nasid(ordinal));
-
-		if (sn_hwperf_get_nearest_node_objdata(objs, sn_hwperf_obj_cnt,
-			ordinal, &near_mem, &near_cpu) == 0) {
-			seq_printf(s, ", near_mem_nodeid %d, near_cpu_nodeid %d",
-				near_mem, near_cpu);
-		}
-
-		if (!SN_HWPERF_IS_IONODE(obj)) {
-			for_each_online_node(i) {
-				seq_printf(s, i ? ":%d" : ", dist %d",
-					node_distance(ordinal, i));
-			}
-		}
-
-		seq_putc(s, '\n');
-
-		/*
-		 * CPUs on this node, if any
-		 */
-		if (!SN_HWPERF_IS_IONODE(obj)) {
-			for_each_cpu_and(i, cpu_online_mask,
-					 cpumask_of_node(ordinal)) {
-				slice = 'a' + cpuid_to_slice(i);
-				c = cpu_data(i);
-				seq_printf(s, "cpu %d %s%c local"
-					   " freq %luMHz, arch ia64",
-					   i, obj->location, slice,
-					   c->proc_freq / 1000000);
-				for_each_online_cpu(j) {
-					seq_printf(s, j ? ":%d" : ", dist %d",
-						   node_distance(
-						    	cpu_to_node(i),
-						    	cpu_to_node(j)));
-				}
-				seq_putc(s, '\n');
-			}
-		}
-	}
-
-	if (obj->ports) {
-		/*
-		 * numalink ports
-		 */
-		sz = obj->ports * sizeof(struct sn_hwperf_port_info);
-		if ((ptdata = kmalloc(sz, GFP_KERNEL)) == NULL)
-			return -ENOMEM;
-		e = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
-				      SN_HWPERF_ENUM_PORTS, obj->id, sz,
-				      (u64) ptdata, 0, 0, NULL);
-		if (e != SN_HWPERF_OP_OK)
-			return -EINVAL;
-		for (ordinal=0, p=objs; p != obj; p++) {
-			if (!SN_HWPERF_FOREIGN(p))
-				ordinal += p->ports;
-		}
-		for (pt = 0; pt < obj->ports; pt++) {
-			for (p = objs, i = 0; i < sn_hwperf_obj_cnt; i++, p++) {
-				if (ptdata[pt].conn_id == p->id) {
-					break;
-				}
-			}
-			seq_printf(s, "numalink %d %s-%d",
-			    ordinal+pt, obj->location, ptdata[pt].port);
-
-			if (i >= sn_hwperf_obj_cnt) {
-				/* no connection */
-				seq_puts(s, " local endpoint disconnected"
-					    ", protocol unknown\n");
-				continue;
-			}
-
-			if (obj->sn_hwp_this_part && p->sn_hwp_this_part)
-				/* both ends local to this partition */
-				seq_puts(s, " local");
-			else if (SN_HWPERF_FOREIGN(p))
-				/* both ends of the link in foreign partition */
-				seq_puts(s, " foreign");
-			else
-				/* link straddles a partition */
-				seq_puts(s, " shared");
-
-			/*
-			 * Unlikely, but strictly should query the LLP config
-			 * registers because an NL4R can be configured to run
-			 * NL3 protocol, even when not talking to an NL3 router.
-			 * Ditto for node-node.
-			 */
-			seq_printf(s, " endpoint %s-%d, protocol %s\n",
-				p->location, ptdata[pt].conn_port,
-				(SN_HWPERF_IS_NL3ROUTER(obj) ||
-				SN_HWPERF_IS_NL3ROUTER(p)) ?  "LLP3" : "LLP4");
-		}
-		kfree(ptdata);
-	}
-
-	return 0;
-}
-
-static void *sn_topology_start(struct seq_file *s, loff_t * pos)
-{
-	struct sn_hwperf_object_info *objs = s->private;
-
-	if (*pos < sn_hwperf_obj_cnt)
-		return (void *)(objs + *pos);
-
-	return NULL;
-}
-
-static void *sn_topology_next(struct seq_file *s, void *v, loff_t * pos)
-{
-	++*pos;
-	return sn_topology_start(s, pos);
-}
-
-static void sn_topology_stop(struct seq_file *m, void *v)
-{
-	return;
-}
-
-/*
- * /proc/sgi_sn/sn_topology, read-only using seq_file
- */
-static const struct seq_operations sn_topology_seq_ops = {
-	.start = sn_topology_start,
-	.next = sn_topology_next,
-	.stop = sn_topology_stop,
-	.show = sn_topology_show
-};
-
-struct sn_hwperf_op_info {
-	u64 op;
-	struct sn_hwperf_ioctl_args *a;
-	void *p;
-	int *v0;
-	int ret;
-};
-
-static void sn_hwperf_call_sal(void *info)
-{
-	struct sn_hwperf_op_info *op_info = info;
-	int r;
-
-	r = ia64_sn_hwperf_op(sn_hwperf_master_nasid, op_info->op,
-		      op_info->a->arg, op_info->a->sz,
-		      (u64) op_info->p, 0, 0, op_info->v0);
-	op_info->ret = r;
-}
-
-static long sn_hwperf_call_sal_work(void *info)
-{
-	sn_hwperf_call_sal(info);
-	return 0;
-}
-
-static int sn_hwperf_op_cpu(struct sn_hwperf_op_info *op_info)
-{
-	u32 cpu;
-	u32 use_ipi;
-	int r = 0;
-	
-	cpu = (op_info->a->arg & SN_HWPERF_ARG_CPU_MASK) >> 32;
-	use_ipi = op_info->a->arg & SN_HWPERF_ARG_USE_IPI_MASK;
-	op_info->a->arg &= SN_HWPERF_ARG_OBJID_MASK;
-
-	if (cpu != SN_HWPERF_ARG_ANY_CPU) {
-		if (cpu >= nr_cpu_ids || !cpu_online(cpu)) {
-			r = -EINVAL;
-			goto out;
-		}
-	}
-
-	if (cpu == SN_HWPERF_ARG_ANY_CPU) {
-		/* don't care which cpu */
-		sn_hwperf_call_sal(op_info);
-	} else if (cpu == get_cpu()) {
-		/* already on correct cpu */
-		sn_hwperf_call_sal(op_info);
-		put_cpu();
-	} else {
-		put_cpu();
-		if (use_ipi) {
-			/* use an interprocessor interrupt to call SAL */
-			smp_call_function_single(cpu, sn_hwperf_call_sal,
-				op_info, 1);
-		} else {
-			/* Call on the target CPU */
-			work_on_cpu_safe(cpu, sn_hwperf_call_sal_work, op_info);
-		}
-	}
-	r = op_info->ret;
-
-out:
-	return r;
-}
-
-/* map SAL hwperf error code to system error code */
-static int sn_hwperf_map_err(int hwperf_err)
-{
-	int e;
-
-	switch(hwperf_err) {
-	case SN_HWPERF_OP_OK:
-		e = 0;
-		break;
-
-	case SN_HWPERF_OP_NOMEM:
-		e = -ENOMEM;
-		break;
-
-	case SN_HWPERF_OP_NO_PERM:
-		e = -EPERM;
-		break;
-
-	case SN_HWPERF_OP_IO_ERROR:
-		e = -EIO;
-		break;
-
-	case SN_HWPERF_OP_BUSY:
-		e = -EBUSY;
-		break;
-
-	case SN_HWPERF_OP_RECONFIGURE:
-		e = -EAGAIN;
-		break;
-
-	case SN_HWPERF_OP_INVAL:
-	default:
-		e = -EINVAL;
-		break;
-	}
-
-	return e;
-}
-
-/*
- * ioctl for "sn_hwperf" misc device
- */
-static long sn_hwperf_ioctl(struct file *fp, u32 op, unsigned long arg)
-{
-	struct sn_hwperf_ioctl_args a;
-	struct cpuinfo_ia64 *cdata;
-	struct sn_hwperf_object_info *objs;
-	struct sn_hwperf_object_info *cpuobj;
-	struct sn_hwperf_op_info op_info;
-	void *p = NULL;
-	int nobj;
-	char slice;
-	int node;
-	int r;
-	int v0;
-	int i;
-	int j;
-
-	/* only user requests are allowed here */
-	if ((op & SN_HWPERF_OP_MASK) < 10) {
-		r = -EINVAL;
-		goto error;
-	}
-	r = copy_from_user(&a, (const void __user *)arg,
-		sizeof(struct sn_hwperf_ioctl_args));
-	if (r != 0) {
-		r = -EFAULT;
-		goto error;
-	}
-
-	/*
-	 * Allocate memory to hold a kernel copy of the user buffer. The
-	 * buffer contents are either copied in or out (or both) of user
-	 * space depending on the flags encoded in the requested operation.
-	 */
-	if (a.ptr) {
-		p = vmalloc(a.sz);
-		if (!p) {
-			r = -ENOMEM;
-			goto error;
-		}
-	}
-
-	if (op & SN_HWPERF_OP_MEM_COPYIN) {
-		r = copy_from_user(p, (const void __user *)a.ptr, a.sz);
-		if (r != 0) {
-			r = -EFAULT;
-			goto error;
-		}
-	}
-
-	switch (op) {
-	case SN_HWPERF_GET_CPU_INFO:
-		if (a.sz == sizeof(u64)) {
-			/* special case to get size needed */
-			*(u64 *) p = (u64) num_online_cpus() *
-				sizeof(struct sn_hwperf_object_info);
-		} else
-		if (a.sz < num_online_cpus() * sizeof(struct sn_hwperf_object_info)) {
-			r = -ENOMEM;
-			goto error;
-		} else
-		if ((r = sn_hwperf_enum_objects(&nobj, &objs)) == 0) {
-			int cpuobj_index = 0;
-
-			memset(p, 0, a.sz);
-			for (i = 0; i < nobj; i++) {
-				if (!SN_HWPERF_IS_NODE(objs + i))
-					continue;
-				node = sn_hwperf_obj_to_cnode(objs + i);
-				for_each_online_cpu(j) {
-					if (node != cpu_to_node(j))
-						continue;
-					cpuobj = (struct sn_hwperf_object_info *) p + cpuobj_index++;
-					slice = 'a' + cpuid_to_slice(j);
-					cdata = cpu_data(j);
-					cpuobj->id = j;
-					snprintf(cpuobj->name,
-						 sizeof(cpuobj->name),
-						 "CPU %luMHz %s",
-						 cdata->proc_freq / 1000000,
-						 cdata->vendor);
-					snprintf(cpuobj->location,
-						 sizeof(cpuobj->location),
-						 "%s%c", objs[i].location,
-						 slice);
-				}
-			}
-
-			vfree(objs);
-		}
-		break;
-
-	case SN_HWPERF_GET_NODE_NASID:
-		if (a.sz != sizeof(u64) ||
-		   (node = a.arg) < 0 || !cnode_possible(node)) {
-			r = -EINVAL;
-			goto error;
-		}
-		*(u64 *)p = (u64)cnodeid_to_nasid(node);
-		break;
-
-	case SN_HWPERF_GET_OBJ_NODE:
-		i = a.arg;
-		if (a.sz != sizeof(u64) || i < 0) {
-			r = -EINVAL;
-			goto error;
-		}
-		if ((r = sn_hwperf_enum_objects(&nobj, &objs)) == 0) {
-			if (i >= nobj) {
-				r = -EINVAL;
-				vfree(objs);
-				goto error;
-			}
-			if (objs[i].id != a.arg) {
-				for (i = 0; i < nobj; i++) {
-					if (objs[i].id == a.arg)
-						break;
-				}
-			}
-			if (i == nobj) {
-				r = -EINVAL;
-				vfree(objs);
-				goto error;
-			}
-
-			if (!SN_HWPERF_IS_NODE(objs + i) &&
-			    !SN_HWPERF_IS_IONODE(objs + i)) {
-			    	r = -ENOENT;
-				vfree(objs);
-				goto error;
-			}
-
-			*(u64 *)p = (u64)sn_hwperf_obj_to_cnode(objs + i);
-			vfree(objs);
-		}
-		break;
-
-	case SN_HWPERF_GET_MMRS:
-	case SN_HWPERF_SET_MMRS:
-	case SN_HWPERF_OBJECT_DISTANCE:
-		op_info.p = p;
-		op_info.a = &a;
-		op_info.v0 = &v0;
-		op_info.op = op;
-		r = sn_hwperf_op_cpu(&op_info);
-		if (r) {
-			r = sn_hwperf_map_err(r);
-			a.v0 = v0;
-			goto error;
-		}
-		break;
-
-	default:
-		/* all other ops are a direct SAL call */
-		r = ia64_sn_hwperf_op(sn_hwperf_master_nasid, op,
-			      a.arg, a.sz, (u64) p, 0, 0, &v0);
-		if (r) {
-			r = sn_hwperf_map_err(r);
-			goto error;
-		}
-		a.v0 = v0;
-		break;
-	}
-
-	if (op & SN_HWPERF_OP_MEM_COPYOUT) {
-		r = copy_to_user((void __user *)a.ptr, p, a.sz);
-		if (r != 0) {
-			r = -EFAULT;
-			goto error;
-		}
-	}
-
-error:
-	vfree(p);
-
-	return r;
-}
-
-static const struct file_operations sn_hwperf_fops = {
-	.unlocked_ioctl = sn_hwperf_ioctl,
-	.llseek = noop_llseek,
-};
-
-static struct miscdevice sn_hwperf_dev = {
-	MISC_DYNAMIC_MINOR,
-	"sn_hwperf",
-	&sn_hwperf_fops
-};
-
-static int sn_hwperf_init(void)
-{
-	u64 v;
-	int salr;
-	int e = 0;
-
-	/* single threaded, once-only initialization */
-	mutex_lock(&sn_hwperf_init_mutex);
-
-	if (sn_hwperf_salheap) {
-		mutex_unlock(&sn_hwperf_init_mutex);
-		return e;
-	}
-
-	/*
-	 * The PROM code needs a fixed reference node. For convenience the
-	 * same node as the console I/O is used.
-	 */
-	sn_hwperf_master_nasid = (nasid_t) ia64_sn_get_console_nasid();
-
-	/*
-	 * Request the needed size and install the PROM scratch area.
-	 * The PROM keeps various tracking bits in this memory area.
-	 */
-	salr = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
-				 (u64) SN_HWPERF_GET_HEAPSIZE, 0,
-				 (u64) sizeof(u64), (u64) &v, 0, 0, NULL);
-	if (salr != SN_HWPERF_OP_OK) {
-		e = -EINVAL;
-		goto out;
-	}
-
-	if ((sn_hwperf_salheap = vmalloc(v)) == NULL) {
-		e = -ENOMEM;
-		goto out;
-	}
-	salr = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
-				 SN_HWPERF_INSTALL_HEAP, 0, v,
-				 (u64) sn_hwperf_salheap, 0, 0, NULL);
-	if (salr != SN_HWPERF_OP_OK) {
-		e = -EINVAL;
-		goto out;
-	}
-
-	salr = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
-				 SN_HWPERF_OBJECT_COUNT, 0,
-				 sizeof(u64), (u64) &v, 0, 0, NULL);
-	if (salr != SN_HWPERF_OP_OK) {
-		e = -EINVAL;
-		goto out;
-	}
-	sn_hwperf_obj_cnt = (int)v;
-
-out:
-	if (e < 0 && sn_hwperf_salheap) {
-		vfree(sn_hwperf_salheap);
-		sn_hwperf_salheap = NULL;
-		sn_hwperf_obj_cnt = 0;
-	}
-	mutex_unlock(&sn_hwperf_init_mutex);
-	return e;
-}
-
-int sn_topology_open(struct inode *inode, struct file *file)
-{
-	int e;
-	struct seq_file *seq;
-	struct sn_hwperf_object_info *objbuf;
-	int nobj;
-
-	if ((e = sn_hwperf_enum_objects(&nobj, &objbuf)) == 0) {
-		e = seq_open(file, &sn_topology_seq_ops);
-		seq = file->private_data;
-		seq->private = objbuf;
-	}
-
-	return e;
-}
-
-int sn_topology_release(struct inode *inode, struct file *file)
-{
-	struct seq_file *seq = file->private_data;
-
-	vfree(seq->private);
-	return seq_release(inode, file);
-}
-
-int sn_hwperf_get_nearest_node(cnodeid_t node,
-	cnodeid_t *near_mem_node, cnodeid_t *near_cpu_node)
-{
-	int e;
-	int nobj;
-	struct sn_hwperf_object_info *objbuf;
-
-	if ((e = sn_hwperf_enum_objects(&nobj, &objbuf)) == 0) {
-		e = sn_hwperf_get_nearest_node_objdata(objbuf, nobj,
-			node, near_mem_node, near_cpu_node);
-		vfree(objbuf);
-	}
-
-	return e;
-}
-
-static int sn_hwperf_misc_register_init(void)
-{
-	int e;
-
-	if (!ia64_platform_is("sn2"))
-		return 0;
-
-	sn_hwperf_init();
-
-	/*
-	 * Register a dynamic misc device for hwperf ioctls. Platforms
-	 * supporting hotplug will create /dev/sn_hwperf, else user
-	 * can to look up the minor number in /proc/misc.
-	 */
-	if ((e = misc_register(&sn_hwperf_dev)) != 0) {
-		printk(KERN_ERR "sn_hwperf_misc_register_init: failed to "
-		"register misc device for \"%s\"\n", sn_hwperf_dev.name);
-	}
-
-	return e;
-}
-
-device_initcall(sn_hwperf_misc_register_init); /* after misc_init() */
-EXPORT_SYMBOL(sn_hwperf_get_nearest_node);
diff --git a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c
deleted file mode 100644
index c2a4d84297b0..000000000000
--- a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifdef CONFIG_PROC_FS
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/uaccess.h>
-#include <asm/sn/sn_sal.h>
-
-static int partition_id_show(struct seq_file *s, void *p)
-{
-	seq_printf(s, "%d\n", sn_partition_id);
-	return 0;
-}
-
-static int system_serial_number_show(struct seq_file *s, void *p)
-{
-	seq_printf(s, "%s\n", sn_system_serial_number());
-	return 0;
-}
-
-static int licenseID_show(struct seq_file *s, void *p)
-{
-	seq_printf(s, "0x%llx\n", sn_partition_serial_number_val());
-	return 0;
-}
-
-static int coherence_id_show(struct seq_file *s, void *p)
-{
-	seq_printf(s, "%d\n", partition_coherence_id());
-
-	return 0;
-}
-
-/* /proc/sgi_sn/sn_topology uses seq_file, see sn_hwperf.c */
-extern int sn_topology_open(struct inode *, struct file *);
-extern int sn_topology_release(struct inode *, struct file *);
-
-static const struct file_operations proc_sn_topo_fops = {
-	.open		= sn_topology_open,
-	.read		= seq_read,
-	.llseek		= seq_lseek,
-	.release	= sn_topology_release,
-};
-
-void register_sn_procfs(void)
-{
-	static struct proc_dir_entry *sgi_proc_dir = NULL;
-
-	BUG_ON(sgi_proc_dir != NULL);
-	if (!(sgi_proc_dir = proc_mkdir("sgi_sn", NULL)))
-		return;
-
-	proc_create_single("partition_id", 0444, sgi_proc_dir,
-			partition_id_show);
-	proc_create_single("system_serial_number", 0444, sgi_proc_dir,
-			system_serial_number_show);
-	proc_create_single("licenseID", 0444, sgi_proc_dir, licenseID_show);
-	proc_create_single("coherence_id", 0444, sgi_proc_dir,
-			coherence_id_show);
-	proc_create("sn_topology", 0444, sgi_proc_dir, &proc_sn_topo_fops);
-}
-
-#endif /* CONFIG_PROC_FS */
diff --git a/arch/ia64/sn/kernel/sn2/timer.c b/arch/ia64/sn/kernel/sn2/timer.c
deleted file mode 100644
index 3009d9d86f29..000000000000
--- a/arch/ia64/sn/kernel/sn2/timer.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/ia64/sn/kernel/sn2/timer.c
- *
- * Copyright (C) 2003 Silicon Graphics, Inc.
- * Copyright (C) 2003 Hewlett-Packard Co
- *	David Mosberger <davidm@hpl.hp.com>: updated for new timer-interpolation infrastructure
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/clocksource.h>
-
-#include <asm/hw_irq.h>
-#include <asm/timex.h>
-
-#include <asm/sn/leds.h>
-#include <asm/sn/shub_mmr.h>
-#include <asm/sn/clksupport.h>
-
-extern unsigned long sn_rtc_cycles_per_second;
-
-static u64 read_sn2(struct clocksource *cs)
-{
-	return (u64)readq(RTC_COUNTER_ADDR);
-}
-
-static struct clocksource clocksource_sn2 = {
-        .name           = "sn2_rtc",
-        .rating         = 450,
-        .read           = read_sn2,
-        .mask           = (1LL << 55) - 1,
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-/*
- * sn udelay uses the RTC instead of the ITC because the ITC is not
- * synchronized across all CPUs, and the thread may migrate to another CPU
- * if preemption is enabled.
- */
-static void
-ia64_sn_udelay (unsigned long usecs)
-{
-	unsigned long start = rtc_time();
-	unsigned long end = start +
-			usecs * sn_rtc_cycles_per_second / 1000000;
-
-	while (time_before((unsigned long)rtc_time(), end))
-		cpu_relax();
-}
-
-void __init sn_timer_init(void)
-{
-	clocksource_sn2.archdata.fsys_mmio = RTC_COUNTER_ADDR;
-	clocksource_register_hz(&clocksource_sn2, sn_rtc_cycles_per_second);
-
-	ia64_udelay = &ia64_sn_udelay;
-}
diff --git a/arch/ia64/sn/kernel/sn2/timer_interrupt.c b/arch/ia64/sn/kernel/sn2/timer_interrupt.c
deleted file mode 100644
index 103d6ea8e94b..000000000000
--- a/arch/ia64/sn/kernel/sn2/timer_interrupt.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *
- *
- * Copyright (c) 2005, 2006 Silicon Graphics, Inc.  All Rights Reserved.
- * 
- * This program is free software; you can redistribute it and/or modify it 
- * under the terms of version 2 of the GNU General Public License 
- * as published by the Free Software Foundation.
- * 
- * This program is distributed in the hope that it would be useful, but 
- * WITHOUT ANY WARRANTY; without even the implied warranty of 
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
- * 
- * Further, this software is distributed without any warranty that it is 
- * free of the rightful claim of any third person regarding infringement 
- * or the like.  Any license provided herein, whether implied or 
- * otherwise, applies only to this software file.  Patent licenses, if 
- * any, provided herein do not apply to combinations of this program with 
- * other software, or any other product whatsoever.
- * 
- * You should have received a copy of the GNU General Public 
- * License along with this program; if not, write the Free Software 
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- * 
- * For further information regarding this notice, see: 
- * 
- * http://oss.sgi.com/projects/GenInfo/NoticeExplan
- */
-
-#include <linux/interrupt.h>
-#include <asm/sn/pda.h>
-#include <asm/sn/leds.h>
-
-extern void sn_lb_int_war_check(void);
-extern irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs);
-
-#define SN_LB_INT_WAR_INTERVAL 100
-
-void sn_timer_interrupt(int irq, void *dev_id)
-{
-	/* LED blinking */
-	if (!pda->hb_count--) {
-		pda->hb_count = HZ / 2;
-		set_led_bits(pda->hb_state ^=
-			     LED_CPU_HEARTBEAT, LED_CPU_HEARTBEAT);
-	}
-
-	if (is_shub1()) {
-		if (enable_shub_wars_1_1()) {
-			/* Bugfix code for SHUB 1.1 */
-			if (pda->pio_shub_war_cam_addr)
-				*pda->pio_shub_war_cam_addr = 0x8000000000000010UL;
-		}
-		if (pda->sn_lb_int_war_ticks == 0)
-			sn_lb_int_war_check();
-		pda->sn_lb_int_war_ticks++;
-		if (pda->sn_lb_int_war_ticks >= SN_LB_INT_WAR_INTERVAL)
-			pda->sn_lb_int_war_ticks = 0;
-	}
-}
diff --git a/arch/ia64/sn/kernel/tiocx.c b/arch/ia64/sn/kernel/tiocx.c
deleted file mode 100644
index 32d0380eb72e..000000000000
--- a/arch/ia64/sn/kernel/tiocx.c
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2005 Silicon Graphics, Inc.  All rights reserved.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/proc_fs.h>
-#include <linux/capability.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/io.h>
-#include <asm/sn/types.h>
-#include <asm/sn/shubio.h>
-#include <asm/sn/tiocx.h>
-#include <asm/sn/l1.h>
-#include <asm/sn/module.h>
-#include "tio.h"
-#include "xtalk/xwidgetdev.h"
-#include "xtalk/hubdev.h"
-
-#define CX_DEV_NONE 0
-#define DEVICE_NAME "tiocx"
-#define WIDGET_ID 0
-#define TIOCX_DEBUG 0
-
-#if TIOCX_DEBUG
-#define DBG(fmt...)    printk(KERN_ALERT fmt)
-#else
-#define DBG(fmt...)
-#endif
-
-struct device_attribute dev_attr_cxdev_control;
-
-/**
- * tiocx_match - Try to match driver id list with device.
- * @dev: device pointer
- * @drv: driver pointer
- *
- * Returns 1 if match, 0 otherwise.
- */
-static int tiocx_match(struct device *dev, struct device_driver *drv)
-{
-	struct cx_dev *cx_dev = to_cx_dev(dev);
-	struct cx_drv *cx_drv = to_cx_driver(drv);
-	const struct cx_device_id *ids = cx_drv->id_table;
-
-	if (!ids)
-		return 0;
-
-	while (ids->part_num) {
-		if (ids->part_num == cx_dev->cx_id.part_num)
-			return 1;
-		ids++;
-	}
-	return 0;
-
-}
-
-static int tiocx_uevent(struct device *dev, struct kobj_uevent_env *env)
-{
-	return -ENODEV;
-}
-
-static void tiocx_bus_release(struct device *dev)
-{
-	kfree(to_cx_dev(dev));
-}
-
-/**
- * cx_device_match - Find cx_device in the id table.
- * @ids: id table from driver
- * @cx_device: part/mfg id for the device
- *
- */
-static const struct cx_device_id *cx_device_match(const struct cx_device_id
-						  *ids,
-						  struct cx_dev *cx_device)
-{
-	/*
-	 * NOTES: We may want to check for CX_ANY_ID too.
-	 *        Do we want to match against nasid too?
-	 *        CX_DEV_NONE == 0, if the driver tries to register for
-	 *        part/mfg == 0 we should return no-match (NULL) here.
-	 */
-	while (ids->part_num && ids->mfg_num) {
-		if (ids->part_num == cx_device->cx_id.part_num &&
-		    ids->mfg_num == cx_device->cx_id.mfg_num)
-			return ids;
-		ids++;
-	}
-
-	return NULL;
-}
-
-/**
- * cx_device_probe - Look for matching device.
- *			Call driver probe routine if found.
- * @cx_driver: driver table (cx_drv struct) from driver
- * @cx_device: part/mfg id for the device
- */
-static int cx_device_probe(struct device *dev)
-{
-	const struct cx_device_id *id;
-	struct cx_drv *cx_drv = to_cx_driver(dev->driver);
-	struct cx_dev *cx_dev = to_cx_dev(dev);
-	int error = 0;
-
-	if (!cx_dev->driver && cx_drv->probe) {
-		id = cx_device_match(cx_drv->id_table, cx_dev);
-		if (id) {
-			if ((error = cx_drv->probe(cx_dev, id)) < 0)
-				return error;
-			else
-				cx_dev->driver = cx_drv;
-		}
-	}
-
-	return error;
-}
-
-/**
- * cx_driver_remove - Remove driver from device struct.
- * @dev: device
- */
-static int cx_driver_remove(struct device *dev)
-{
-	struct cx_dev *cx_dev = to_cx_dev(dev);
-	struct cx_drv *cx_drv = cx_dev->driver;
-	if (cx_drv->remove)
-		cx_drv->remove(cx_dev);
-	cx_dev->driver = NULL;
-	return 0;
-}
-
-struct bus_type tiocx_bus_type = {
-	.name = "tiocx",
-	.match = tiocx_match,
-	.uevent = tiocx_uevent,
-	.probe = cx_device_probe,
-	.remove = cx_driver_remove,
-};
-
-/**
- * cx_driver_register - Register the driver.
- * @cx_driver: driver table (cx_drv struct) from driver
- * 
- * Called from the driver init routine to register a driver.
- * The cx_drv struct contains the driver name, a pointer to
- * a table of part/mfg numbers and a pointer to the driver's
- * probe/attach routine.
- */
-int cx_driver_register(struct cx_drv *cx_driver)
-{
-	cx_driver->driver.name = cx_driver->name;
-	cx_driver->driver.bus = &tiocx_bus_type;
-
-	return driver_register(&cx_driver->driver);
-}
-
-/**
- * cx_driver_unregister - Unregister the driver.
- * @cx_driver: driver table (cx_drv struct) from driver
- */
-int cx_driver_unregister(struct cx_drv *cx_driver)
-{
-	driver_unregister(&cx_driver->driver);
-	return 0;
-}
-
-/**
- * cx_device_register - Register a device.
- * @nasid: device's nasid
- * @part_num: device's part number
- * @mfg_num: device's manufacturer number
- * @hubdev: hub info associated with this device
- * @bt: board type of the device
- *
- */
-int
-cx_device_register(nasid_t nasid, int part_num, int mfg_num,
-		   struct hubdev_info *hubdev, int bt)
-{
-	struct cx_dev *cx_dev;
-	int r;
-
-	cx_dev = kzalloc(sizeof(struct cx_dev), GFP_KERNEL);
-	DBG("cx_dev= 0x%p\n", cx_dev);
-	if (cx_dev == NULL)
-		return -ENOMEM;
-
-	cx_dev->cx_id.part_num = part_num;
-	cx_dev->cx_id.mfg_num = mfg_num;
-	cx_dev->cx_id.nasid = nasid;
-	cx_dev->hubdev = hubdev;
-	cx_dev->bt = bt;
-
-	cx_dev->dev.parent = NULL;
-	cx_dev->dev.bus = &tiocx_bus_type;
-	cx_dev->dev.release = tiocx_bus_release;
-	dev_set_name(&cx_dev->dev, "%d", cx_dev->cx_id.nasid);
-	r = device_register(&cx_dev->dev);
-	if (r) {
-		kfree(cx_dev);
-		return r;
-	}
-	get_device(&cx_dev->dev);
-
-	device_create_file(&cx_dev->dev, &dev_attr_cxdev_control);
-
-	return 0;
-}
-
-/**
- * cx_device_unregister - Unregister a device.
- * @cx_dev: part/mfg id for the device
- */
-int cx_device_unregister(struct cx_dev *cx_dev)
-{
-	put_device(&cx_dev->dev);
-	device_unregister(&cx_dev->dev);
-	return 0;
-}
-
-/**
- * cx_device_reload - Reload the device.
- * @nasid: device's nasid
- * @part_num: device's part number
- * @mfg_num: device's manufacturer number
- *
- * Remove the device associated with 'nasid' from device list and then
- * call device-register with the given part/mfg numbers.
- */
-static int cx_device_reload(struct cx_dev *cx_dev)
-{
-	cx_device_unregister(cx_dev);
-	return cx_device_register(cx_dev->cx_id.nasid, cx_dev->cx_id.part_num,
-				  cx_dev->cx_id.mfg_num, cx_dev->hubdev,
-				  cx_dev->bt);
-}
-
-static inline u64 tiocx_intr_alloc(nasid_t nasid, int widget,
-					u64 sn_irq_info,
-					int req_irq, nasid_t req_nasid,
-					int req_slice)
-{
-	struct ia64_sal_retval rv;
-	rv.status = 0;
-	rv.v0 = 0;
-
-	ia64_sal_oemcall_nolock(&rv, SN_SAL_IOIF_INTERRUPT,
-				SAL_INTR_ALLOC, nasid,
-				widget, sn_irq_info, req_irq,
-				req_nasid, req_slice);
-	return rv.status;
-}
-
-static inline void tiocx_intr_free(nasid_t nasid, int widget,
-				   struct sn_irq_info *sn_irq_info)
-{
-	struct ia64_sal_retval rv;
-	rv.status = 0;
-	rv.v0 = 0;
-
-	ia64_sal_oemcall_nolock(&rv, SN_SAL_IOIF_INTERRUPT,
-				SAL_INTR_FREE, nasid,
-				widget, sn_irq_info->irq_irq,
-				sn_irq_info->irq_cookie, 0, 0);
-}
-
-struct sn_irq_info *tiocx_irq_alloc(nasid_t nasid, int widget, int irq,
-				    nasid_t req_nasid, int slice)
-{
-	struct sn_irq_info *sn_irq_info;
-	int status;
-	int sn_irq_size = sizeof(struct sn_irq_info);
-
-	if ((nasid & 1) == 0)
-		return NULL;
-
-	sn_irq_info = kzalloc(sn_irq_size, GFP_KERNEL);
-	if (sn_irq_info == NULL)
-		return NULL;
-
-	status = tiocx_intr_alloc(nasid, widget, __pa(sn_irq_info), irq,
-				  req_nasid, slice);
-	if (status) {
-		kfree(sn_irq_info);
-		return NULL;
-	} else {
-		return sn_irq_info;
-	}
-}
-
-void tiocx_irq_free(struct sn_irq_info *sn_irq_info)
-{
-	u64 bridge = (u64) sn_irq_info->irq_bridge;
-	nasid_t nasid = NASID_GET(bridge);
-	int widget;
-
-	if (nasid & 1) {
-		widget = TIO_SWIN_WIDGETNUM(bridge);
-		tiocx_intr_free(nasid, widget, sn_irq_info);
-		kfree(sn_irq_info);
-	}
-}
-
-u64 tiocx_dma_addr(u64 addr)
-{
-	return PHYS_TO_TIODMA(addr);
-}
-
-u64 tiocx_swin_base(int nasid)
-{
-	return TIO_SWIN_BASE(nasid, TIOCX_CORELET);
-}
-
-EXPORT_SYMBOL(cx_driver_register);
-EXPORT_SYMBOL(cx_driver_unregister);
-EXPORT_SYMBOL(cx_device_register);
-EXPORT_SYMBOL(cx_device_unregister);
-EXPORT_SYMBOL(tiocx_irq_alloc);
-EXPORT_SYMBOL(tiocx_irq_free);
-EXPORT_SYMBOL(tiocx_bus_type);
-EXPORT_SYMBOL(tiocx_dma_addr);
-EXPORT_SYMBOL(tiocx_swin_base);
-
-static void tio_conveyor_set(nasid_t nasid, int enable_flag)
-{
-	u64 ice_frz;
-	u64 disable_cb = (1ull << 61);
-
-	if (!(nasid & 1))
-		return;
-
-	ice_frz = REMOTE_HUB_L(nasid, TIO_ICE_FRZ_CFG);
-	if (enable_flag) {
-		if (!(ice_frz & disable_cb))	/* already enabled */
-			return;
-		ice_frz &= ~disable_cb;
-	} else {
-		if (ice_frz & disable_cb)	/* already disabled */
-			return;
-		ice_frz |= disable_cb;
-	}
-	DBG(KERN_ALERT "TIO_ICE_FRZ_CFG= 0x%lx\n", ice_frz);
-	REMOTE_HUB_S(nasid, TIO_ICE_FRZ_CFG, ice_frz);
-}
-
-#define tio_conveyor_enable(nasid) tio_conveyor_set(nasid, 1)
-#define tio_conveyor_disable(nasid) tio_conveyor_set(nasid, 0)
-
-static void tio_corelet_reset(nasid_t nasid, int corelet)
-{
-	if (!(nasid & 1))
-		return;
-
-	REMOTE_HUB_S(nasid, TIO_ICE_PMI_TX_CFG, 1 << corelet);
-	udelay(2000);
-	REMOTE_HUB_S(nasid, TIO_ICE_PMI_TX_CFG, 0);
-	udelay(2000);
-}
-
-static int is_fpga_tio(int nasid, int *bt)
-{
-	u16 uninitialized_var(ioboard_type);	/* GCC be quiet */
-	long rc;
-
-	rc = ia64_sn_sysctl_ioboard_get(nasid, &ioboard_type);
-	if (rc) {
-		printk(KERN_WARNING "ia64_sn_sysctl_ioboard_get failed: %ld\n",
-		       rc);
-		return 0;
-	}
-
-	switch (ioboard_type) {
-	case L1_BRICKTYPE_SA:
-	case L1_BRICKTYPE_ATHENA:
-	case L1_BOARDTYPE_DAYTONA:
-		*bt = ioboard_type;
-		return 1;
-	}
-
-	return 0;
-}
-
-static int bitstream_loaded(nasid_t nasid)
-{
-	u64 cx_credits;
-
-	cx_credits = REMOTE_HUB_L(nasid, TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3);
-	cx_credits &= TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK;
-	DBG("cx_credits= 0x%lx\n", cx_credits);
-
-	return (cx_credits == 0xf) ? 1 : 0;
-}
-
-static int tiocx_reload(struct cx_dev *cx_dev)
-{
-	int part_num = CX_DEV_NONE;
-	int mfg_num = CX_DEV_NONE;
-	nasid_t nasid = cx_dev->cx_id.nasid;
-
-	if (bitstream_loaded(nasid)) {
-		u64 cx_id;
-		int rv;
-
-		rv = ia64_sn_sysctl_tio_clock_reset(nasid);
-		if (rv) {
-			printk(KERN_ALERT "CX port JTAG reset failed.\n");
-		} else {
-			cx_id = *(volatile u64 *)
-				(TIO_SWIN_BASE(nasid, TIOCX_CORELET) +
-					  WIDGET_ID);
-			part_num = XWIDGET_PART_NUM(cx_id);
-			mfg_num = XWIDGET_MFG_NUM(cx_id);
-			DBG("part= 0x%x, mfg= 0x%x\n", part_num, mfg_num);
-			/* just ignore it if it's a CE */
-			if (part_num == TIO_CE_ASIC_PARTNUM)
-				return 0;
-		}
-	}
-
-	cx_dev->cx_id.part_num = part_num;
-	cx_dev->cx_id.mfg_num = mfg_num;
-
-	/*
-	 * Delete old device and register the new one.  It's ok if
-	 * part_num/mfg_num == CX_DEV_NONE.  We want to register
-	 * devices in the table even if a bitstream isn't loaded.
-	 * That allows use to see that a bitstream isn't loaded via
-	 * TIOCX_IOCTL_DEV_LIST.
-	 */
-	return cx_device_reload(cx_dev);
-}
-
-static ssize_t show_cxdev_control(struct device *dev, struct device_attribute *attr, char *buf)
-{
-	struct cx_dev *cx_dev = to_cx_dev(dev);
-
-	return sprintf(buf, "0x%x 0x%x 0x%x 0x%x\n",
-		       cx_dev->cx_id.nasid,
-		       cx_dev->cx_id.part_num, cx_dev->cx_id.mfg_num,
-		       cx_dev->bt);
-}
-
-static ssize_t store_cxdev_control(struct device *dev, struct device_attribute *attr, const char *buf,
-				   size_t count)
-{
-	int n;
-	struct cx_dev *cx_dev = to_cx_dev(dev);
-
-	if (!capable(CAP_SYS_ADMIN))
-		return -EPERM;
-
-	if (count <= 0)
-		return 0;
-
-	n = simple_strtoul(buf, NULL, 0);
-
-	switch (n) {
-	case 1:
-		tio_corelet_reset(cx_dev->cx_id.nasid, TIOCX_CORELET);
-		tiocx_reload(cx_dev);
-		break;
-	case 2:
-		tiocx_reload(cx_dev);
-		break;
-	case 3:
-		tio_corelet_reset(cx_dev->cx_id.nasid, TIOCX_CORELET);
-		break;
-	default:
-		break;
-	}
-
-	return count;
-}
-
-DEVICE_ATTR(cxdev_control, 0644, show_cxdev_control, store_cxdev_control);
-
-static int __init tiocx_init(void)
-{
-	cnodeid_t cnodeid;
-	int found_tiocx_device = 0;
-	int err;
-
-	if (!ia64_platform_is("sn2"))
-		return 0;
-
-	err = bus_register(&tiocx_bus_type);
-	if (err)
-		return err;
-
-	for (cnodeid = 0; cnodeid < num_cnodes; cnodeid++) {
-		nasid_t nasid;
-		int bt;
-
-		nasid = cnodeid_to_nasid(cnodeid);
-
-		if ((nasid & 0x1) && is_fpga_tio(nasid, &bt)) {
-			struct hubdev_info *hubdev;
-			struct xwidget_info *widgetp;
-
-			DBG("Found TIO at nasid 0x%x\n", nasid);
-
-			hubdev =
-			    (struct hubdev_info *)(NODEPDA(cnodeid)->pdinfo);
-
-			widgetp = &hubdev->hdi_xwidget_info[TIOCX_CORELET];
-
-			/* The CE hangs off of the CX port but is not an FPGA */
-			if (widgetp->xwi_hwid.part_num == TIO_CE_ASIC_PARTNUM)
-				continue;
-
-			tio_corelet_reset(nasid, TIOCX_CORELET);
-			tio_conveyor_enable(nasid);
-
-			if (cx_device_register
-			    (nasid, widgetp->xwi_hwid.part_num,
-			     widgetp->xwi_hwid.mfg_num, hubdev, bt) < 0)
-				return -ENXIO;
-			else
-				found_tiocx_device++;
-		}
-	}
-
-	/* It's ok if we find zero devices. */
-	DBG("found_tiocx_device= %d\n", found_tiocx_device);
-
-	return 0;
-}
-
-static int cx_remove_device(struct device * dev, void * data)
-{
-	struct cx_dev *cx_dev = to_cx_dev(dev);
-	device_remove_file(dev, &dev_attr_cxdev_control);
-	cx_device_unregister(cx_dev);
-	return 0;
-}
-
-static void __exit tiocx_exit(void)
-{
-	DBG("tiocx_exit\n");
-
-	/*
-	 * Unregister devices.
-	 */
-	bus_for_each_dev(&tiocx_bus_type, NULL, NULL, cx_remove_device);
-	bus_unregister(&tiocx_bus_type);
-}
-
-fs_initcall(tiocx_init);
-module_exit(tiocx_exit);
-
-/************************************************************************
- * Module licensing and description
- ************************************************************************/
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Bruce Losure <blosure@sgi.com>");
-MODULE_DESCRIPTION("TIOCX module");
-MODULE_SUPPORTED_DEVICE(DEVICE_NAME);
diff --git a/arch/ia64/sn/pci/Makefile b/arch/ia64/sn/pci/Makefile
deleted file mode 100644
index 321576b1b425..000000000000
--- a/arch/ia64/sn/pci/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2000-2004 Silicon Graphics, Inc.  All Rights Reserved.
-#
-# Makefile for the sn pci general routines.
-
-obj-y := pci_dma.o tioca_provider.o tioce_provider.o pcibr/
diff --git a/arch/ia64/sn/pci/pci_dma.c b/arch/ia64/sn/pci/pci_dma.c
deleted file mode 100644
index b7d42e4edc1f..000000000000
--- a/arch/ia64/sn/pci/pci_dma.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
- *
- * Routines for PCI DMA mapping.  See Documentation/DMA-API.txt for
- * a description of how these routines should be used.
- */
-
-#include <linux/gfp.h>
-#include <linux/module.h>
-#include <linux/dma-mapping.h>
-#include <asm/dma.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/sn_sal.h>
-
-#define SG_ENT_VIRT_ADDRESS(sg)	(sg_virt((sg)))
-#define SG_ENT_PHYS_ADDRESS(SG)	virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
-
-/**
- * sn_dma_supported - test a DMA mask
- * @dev: device to test
- * @mask: DMA mask to test
- *
- * Return whether the given PCI device DMA address mask can be supported
- * properly.  For example, if your device can only drive the low 24-bits
- * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
- * this function.  Of course, SN only supports devices that have 32 or more
- * address bits when using the PMU.
- */
-static int sn_dma_supported(struct device *dev, u64 mask)
-{
-	BUG_ON(!dev_is_pci(dev));
-
-	if (mask < 0x7fffffff)
-		return 0;
-	return 1;
-}
-
-/**
- * sn_dma_set_mask - set the DMA mask
- * @dev: device to set
- * @dma_mask: new mask
- *
- * Set @dev's DMA mask if the hw supports it.
- */
-int sn_dma_set_mask(struct device *dev, u64 dma_mask)
-{
-	BUG_ON(!dev_is_pci(dev));
-
-	if (!sn_dma_supported(dev, dma_mask))
-		return 0;
-
-	*dev->dma_mask = dma_mask;
-	return 1;
-}
-EXPORT_SYMBOL(sn_dma_set_mask);
-
-/**
- * sn_dma_alloc_coherent - allocate memory for coherent DMA
- * @dev: device to allocate for
- * @size: size of the region
- * @dma_handle: DMA (bus) address
- * @flags: memory allocation flags
- *
- * dma_alloc_coherent() returns a pointer to a memory region suitable for
- * coherent DMA traffic to/from a PCI device.  On SN platforms, this means
- * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
- *
- * This interface is usually used for "command" streams (e.g. the command
- * queue for a SCSI controller).  See Documentation/DMA-API.txt for
- * more information.
- */
-static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
-				   dma_addr_t * dma_handle, gfp_t flags,
-				   unsigned long attrs)
-{
-	void *cpuaddr;
-	unsigned long phys_addr;
-	int node;
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
-
-	BUG_ON(!dev_is_pci(dev));
-
-	/*
-	 * Allocate the memory.
-	 */
-	node = pcibus_to_node(pdev->bus);
-	if (likely(node >=0)) {
-		struct page *p = __alloc_pages_node(node,
-						flags, get_order(size));
-
-		if (likely(p))
-			cpuaddr = page_address(p);
-		else
-			return NULL;
-	} else
-		cpuaddr = (void *)__get_free_pages(flags, get_order(size));
-
-	if (unlikely(!cpuaddr))
-		return NULL;
-
-	memset(cpuaddr, 0x0, size);
-
-	/* physical addr. of the memory we just got */
-	phys_addr = __pa(cpuaddr);
-
-	/*
-	 * 64 bit address translations should never fail.
-	 * 32 bit translations can fail if there are insufficient mapping
-	 * resources.
-	 */
-
-	*dma_handle = provider->dma_map_consistent(pdev, phys_addr, size,
-						   SN_DMA_ADDR_PHYS);
-	if (!*dma_handle) {
-		printk(KERN_ERR "%s: out of ATEs\n", __func__);
-		free_pages((unsigned long)cpuaddr, get_order(size));
-		return NULL;
-	}
-
-	return cpuaddr;
-}
-
-/**
- * sn_pci_free_coherent - free memory associated with coherent DMAable region
- * @dev: device to free for
- * @size: size to free
- * @cpu_addr: kernel virtual address to free
- * @dma_handle: DMA address associated with this region
- *
- * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
- * any associated IOMMU mappings.
- */
-static void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
-				 dma_addr_t dma_handle, unsigned long attrs)
-{
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
-
-	BUG_ON(!dev_is_pci(dev));
-
-	provider->dma_unmap(pdev, dma_handle, 0);
-	free_pages((unsigned long)cpu_addr, get_order(size));
-}
-
-/**
- * sn_dma_map_single_attrs - map a single page for DMA
- * @dev: device to map for
- * @cpu_addr: kernel virtual address of the region to map
- * @size: size of the region
- * @direction: DMA direction
- * @attrs: optional dma attributes
- *
- * Map the region pointed to by @cpu_addr for DMA and return the
- * DMA address.
- *
- * We map this to the one step pcibr_dmamap_trans interface rather than
- * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
- * no way of saving the dmamap handle from the alloc to later free
- * (which is pretty much unacceptable).
- *
- * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
- * dma_map_consistent() so that writes force a flush of pending DMA.
- * (See "SGI Altix Architecture Considerations for Linux Device Drivers",
- * Document Number: 007-4763-001)
- *
- * TODO: simplify our interface;
- *       figure out how to save dmamap handle so can use two step.
- */
-static dma_addr_t sn_dma_map_page(struct device *dev, struct page *page,
-				  unsigned long offset, size_t size,
-				  enum dma_data_direction dir,
-				  unsigned long attrs)
-{
-	void *cpu_addr = page_address(page) + offset;
-	dma_addr_t dma_addr;
-	unsigned long phys_addr;
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
-
-	BUG_ON(!dev_is_pci(dev));
-
-	phys_addr = __pa(cpu_addr);
-	if (attrs & DMA_ATTR_WRITE_BARRIER)
-		dma_addr = provider->dma_map_consistent(pdev, phys_addr,
-							size, SN_DMA_ADDR_PHYS);
-	else
-		dma_addr = provider->dma_map(pdev, phys_addr, size,
-					     SN_DMA_ADDR_PHYS);
-
-	if (!dma_addr) {
-		printk(KERN_ERR "%s: out of ATEs\n", __func__);
-		return DMA_MAPPING_ERROR;
-	}
-	return dma_addr;
-}
-
-/**
- * sn_dma_unmap_single_attrs - unamp a DMA mapped page
- * @dev: device to sync
- * @dma_addr: DMA address to sync
- * @size: size of region
- * @direction: DMA direction
- * @attrs: optional dma attributes
- *
- * This routine is supposed to sync the DMA region specified
- * by @dma_handle into the coherence domain.  On SN, we're always cache
- * coherent, so we just need to free any ATEs associated with this mapping.
- */
-static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
-			      size_t size, enum dma_data_direction dir,
-			      unsigned long attrs)
-{
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
-
-	BUG_ON(!dev_is_pci(dev));
-
-	provider->dma_unmap(pdev, dma_addr, dir);
-}
-
-/**
- * sn_dma_unmap_sg - unmap a DMA scatterlist
- * @dev: device to unmap
- * @sg: scatterlist to unmap
- * @nhwentries: number of scatterlist entries
- * @direction: DMA direction
- * @attrs: optional dma attributes
- *
- * Unmap a set of streaming mode DMA translations.
- */
-static void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
-			    int nhwentries, enum dma_data_direction dir,
-			    unsigned long attrs)
-{
-	int i;
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
-	struct scatterlist *sg;
-
-	BUG_ON(!dev_is_pci(dev));
-
-	for_each_sg(sgl, sg, nhwentries, i) {
-		provider->dma_unmap(pdev, sg->dma_address, dir);
-		sg->dma_address = (dma_addr_t) NULL;
-		sg->dma_length = 0;
-	}
-}
-
-/**
- * sn_dma_map_sg - map a scatterlist for DMA
- * @dev: device to map for
- * @sg: scatterlist to map
- * @nhwentries: number of entries
- * @direction: direction of the DMA transaction
- * @attrs: optional dma attributes
- *
- * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
- * dma_map_consistent() so that writes force a flush of pending DMA.
- * (See "SGI Altix Architecture Considerations for Linux Device Drivers",
- * Document Number: 007-4763-001)
- *
- * Maps each entry of @sg for DMA.
- */
-static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl,
-			 int nhwentries, enum dma_data_direction dir,
-			 unsigned long attrs)
-{
-	unsigned long phys_addr;
-	struct scatterlist *saved_sg = sgl, *sg;
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
-	int i;
-
-	BUG_ON(!dev_is_pci(dev));
-
-	/*
-	 * Setup a DMA address for each entry in the scatterlist.
-	 */
-	for_each_sg(sgl, sg, nhwentries, i) {
-		dma_addr_t dma_addr;
-		phys_addr = SG_ENT_PHYS_ADDRESS(sg);
-		if (attrs & DMA_ATTR_WRITE_BARRIER)
-			dma_addr = provider->dma_map_consistent(pdev,
-								phys_addr,
-								sg->length,
-								SN_DMA_ADDR_PHYS);
-		else
-			dma_addr = provider->dma_map(pdev, phys_addr,
-						     sg->length,
-						     SN_DMA_ADDR_PHYS);
-
-		sg->dma_address = dma_addr;
-		if (!sg->dma_address) {
-			printk(KERN_ERR "%s: out of ATEs\n", __func__);
-
-			/*
-			 * Free any successfully allocated entries.
-			 */
-			if (i > 0)
-				sn_dma_unmap_sg(dev, saved_sg, i, dir, attrs);
-			return 0;
-		}
-
-		sg->dma_length = sg->length;
-	}
-
-	return nhwentries;
-}
-
-static u64 sn_dma_get_required_mask(struct device *dev)
-{
-	return DMA_BIT_MASK(64);
-}
-
-char *sn_pci_get_legacy_mem(struct pci_bus *bus)
-{
-	if (!SN_PCIBUS_BUSSOFT(bus))
-		return ERR_PTR(-ENODEV);
-
-	return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
-}
-
-int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
-{
-	unsigned long addr;
-	int ret;
-	struct ia64_sal_retval isrv;
-
-	/*
-	 * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
-	 * around hw issues at the pci bus level.  SGI proms older than
-	 * 4.10 don't implement this.
-	 */
-
-	SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
-		 pci_domain_nr(bus), bus->number,
-		 0, /* io */
-		 0, /* read */
-		 port, size, __pa(val));
-
-	if (isrv.status == 0)
-		return size;
-
-	/*
-	 * If the above failed, retry using the SAL_PROBE call which should
-	 * be present in all proms (but which cannot work round PCI chipset
-	 * bugs).  This code is retained for compatibility with old
-	 * pre-4.10 proms, and should be removed at some point in the future.
-	 */
-
-	if (!SN_PCIBUS_BUSSOFT(bus))
-		return -ENODEV;
-
-	addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
-	addr += port;
-
-	ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
-
-	if (ret == 2)
-		return -EINVAL;
-
-	if (ret == 1)
-		*val = -1;
-
-	return size;
-}
-
-int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
-{
-	int ret = size;
-	unsigned long paddr;
-	unsigned long *addr;
-	struct ia64_sal_retval isrv;
-
-	/*
-	 * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
-	 * around hw issues at the pci bus level.  SGI proms older than
-	 * 4.10 don't implement this.
-	 */
-
-	SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
-		 pci_domain_nr(bus), bus->number,
-		 0, /* io */
-		 1, /* write */
-		 port, size, __pa(&val));
-
-	if (isrv.status == 0)
-		return size;
-
-	/*
-	 * If the above failed, retry using the SAL_PROBE call which should
-	 * be present in all proms (but which cannot work round PCI chipset
-	 * bugs).  This code is retained for compatibility with old
-	 * pre-4.10 proms, and should be removed at some point in the future.
-	 */
-
-	if (!SN_PCIBUS_BUSSOFT(bus)) {
-		ret = -ENODEV;
-		goto out;
-	}
-
-	/* Put the phys addr in uncached space */
-	paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
-	paddr += port;
-	addr = (unsigned long *)paddr;
-
-	switch (size) {
-	case 1:
-		*(volatile u8 *)(addr) = (u8)(val);
-		break;
-	case 2:
-		*(volatile u16 *)(addr) = (u16)(val);
-		break;
-	case 4:
-		*(volatile u32 *)(addr) = (u32)(val);
-		break;
-	default:
-		ret = -EINVAL;
-		break;
-	}
- out:
-	return ret;
-}
-
-static struct dma_map_ops sn_dma_ops = {
-	.alloc			= sn_dma_alloc_coherent,
-	.free			= sn_dma_free_coherent,
-	.map_page		= sn_dma_map_page,
-	.unmap_page		= sn_dma_unmap_page,
-	.map_sg			= sn_dma_map_sg,
-	.unmap_sg		= sn_dma_unmap_sg,
-	.dma_supported		= sn_dma_supported,
-	.get_required_mask	= sn_dma_get_required_mask,
-};
-
-void sn_dma_init(void)
-{
-	dma_ops = &sn_dma_ops;
-}
diff --git a/arch/ia64/sn/pci/pcibr/Makefile b/arch/ia64/sn/pci/pcibr/Makefile
deleted file mode 100644
index 712f6af7c6e0..000000000000
--- a/arch/ia64/sn/pci/pcibr/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2002-2004 Silicon Graphics, Inc.  All Rights Reserved.
-#
-# Makefile for the sn2 io routines.
-
-ccflags-y := -I $(srctree)/arch/ia64/sn/include
-
-obj-y				+=  pcibr_dma.o pcibr_reg.o \
-				    pcibr_ate.o pcibr_provider.o
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_ate.c b/arch/ia64/sn/pci/pcibr/pcibr_ate.c
deleted file mode 100644
index b67bb4cb73ff..000000000000
--- a/arch/ia64/sn/pci/pcibr/pcibr_ate.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001-2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/types.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/pcibr_provider.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-
-int pcibr_invalidate_ate;	/* by default don't invalidate ATE on free */
-
-/*
- * mark_ate: Mark the ate as either free or inuse.
- */
-static void mark_ate(struct ate_resource *ate_resource, int start, int number,
-		     u64 value)
-{
-	u64 *ate = ate_resource->ate;
-	int index;
-	int length = 0;
-
-	for (index = start; length < number; index++, length++)
-		ate[index] = value;
-}
-
-/*
- * find_free_ate:  Find the first free ate index starting from the given
- *		   index for the desired consecutive count.
- */
-static int find_free_ate(struct ate_resource *ate_resource, int start,
-			 int count)
-{
-	u64 *ate = ate_resource->ate;
-	int index;
-	int start_free;
-
-	for (index = start; index < ate_resource->num_ate;) {
-		if (!ate[index]) {
-			int i;
-			int free;
-			free = 0;
-			start_free = index;	/* Found start free ate */
-			for (i = start_free; i < ate_resource->num_ate; i++) {
-				if (!ate[i]) {	/* This is free */
-					if (++free == count)
-						return start_free;
-				} else {
-					index = i + 1;
-					break;
-				}
-			}
-			if (i >= ate_resource->num_ate)
-				return -1;
-		} else
-			index++;	/* Try next ate */
-	}
-
-	return -1;
-}
-
-/*
- * free_ate_resource:  Free the requested number of ATEs.
- */
-static inline void free_ate_resource(struct ate_resource *ate_resource,
-				     int start)
-{
-	mark_ate(ate_resource, start, ate_resource->ate[start], 0);
-	if ((ate_resource->lowest_free_index > start) ||
-	    (ate_resource->lowest_free_index < 0))
-		ate_resource->lowest_free_index = start;
-}
-
-/*
- * alloc_ate_resource:  Allocate the requested number of ATEs.
- */
-static inline int alloc_ate_resource(struct ate_resource *ate_resource,
-				     int ate_needed)
-{
-	int start_index;
-
-	/*
-	 * Check for ate exhaustion.
-	 */
-	if (ate_resource->lowest_free_index < 0)
-		return -1;
-
-	/*
-	 * Find the required number of free consecutive ates.
-	 */
-	start_index =
-	    find_free_ate(ate_resource, ate_resource->lowest_free_index,
-			  ate_needed);
-	if (start_index >= 0)
-		mark_ate(ate_resource, start_index, ate_needed, ate_needed);
-
-	ate_resource->lowest_free_index =
-	    find_free_ate(ate_resource, ate_resource->lowest_free_index, 1);
-
-	return start_index;
-}
-
-/*
- * Allocate "count" contiguous Bridge Address Translation Entries
- * on the specified bridge to be used for PCI to XTALK mappings.
- * Indices in rm map range from 1..num_entries.  Indices returned
- * to caller range from 0..num_entries-1.
- *
- * Return the start index on success, -1 on failure.
- */
-int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count)
-{
-	int status;
-	unsigned long flags;
-
-	spin_lock_irqsave(&pcibus_info->pbi_lock, flags);
-	status = alloc_ate_resource(&pcibus_info->pbi_int_ate_resource, count);
-	spin_unlock_irqrestore(&pcibus_info->pbi_lock, flags);
-
-	return status;
-}
-
-/*
- * Setup an Address Translation Entry as specified.  Use either the Bridge
- * internal maps or the external map RAM, as appropriate.
- */
-static inline u64 __iomem *pcibr_ate_addr(struct pcibus_info *pcibus_info,
-				       int ate_index)
-{
-	if (ate_index < pcibus_info->pbi_int_ate_size) {
-		return pcireg_int_ate_addr(pcibus_info, ate_index);
-	}
-	panic("pcibr_ate_addr: invalid ate_index 0x%x", ate_index);
-}
-
-/*
- * Update the ate.
- */
-inline void
-ate_write(struct pcibus_info *pcibus_info, int ate_index, int count,
-	  volatile u64 ate)
-{
-	while (count-- > 0) {
-		if (ate_index < pcibus_info->pbi_int_ate_size) {
-			pcireg_int_ate_set(pcibus_info, ate_index, ate);
-		} else {
-			panic("ate_write: invalid ate_index 0x%x", ate_index);
-		}
-		ate_index++;
-		ate += IOPGSIZE;
-	}
-
-	pcireg_tflush_get(pcibus_info);	/* wait until Bridge PIO complete */
-}
-
-void pcibr_ate_free(struct pcibus_info *pcibus_info, int index)
-{
-
-	volatile u64 ate;
-	int count;
-	unsigned long flags;
-
-	if (pcibr_invalidate_ate) {
-		/* For debugging purposes, clear the valid bit in the ATE */
-		ate = *pcibr_ate_addr(pcibus_info, index);
-		count = pcibus_info->pbi_int_ate_resource.ate[index];
-		ate_write(pcibus_info, index, count, (ate & ~PCI32_ATE_V));
-	}
-
-	spin_lock_irqsave(&pcibus_info->pbi_lock, flags);
-	free_ate_resource(&pcibus_info->pbi_int_ate_resource, index);
-	spin_unlock_irqrestore(&pcibus_info->pbi_lock, flags);
-}
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
deleted file mode 100644
index 1e863b277ac9..000000000000
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/export.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/geo.h>
-#include <asm/sn/pcibr_provider.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/pic.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/tiocp.h>
-#include "tio.h"
-#include "xtalk/xwidgetdev.h"
-#include "xtalk/hubdev.h"
-
-extern int sn_ioif_inited;
-
-/* =====================================================================
- *    DMA MANAGEMENT
- *
- *      The Bridge ASIC provides three methods of doing DMA: via a "direct map"
- *      register available in 32-bit PCI space (which selects a contiguous 2G
- *	address space on some other widget), via "direct" addressing via 64-bit
- *      PCI space (all destination information comes from the PCI address,
- *      including transfer attributes), and via a "mapped" region that allows 
- *      a bunch of different small mappings to be established with the PMU.
- *
- *      For efficiency, we most prefer to use the 32bit direct mapping facility,
- *      since it requires no resource allocations. The advantage of using the
- *      PMU over the 64-bit direct is that single-cycle PCI addressing can be
- *      used; the advantage of using 64-bit direct over PMU addressing is that
- *      we do not have to allocate entries in the PMU.
- */
-
-static dma_addr_t
-pcibr_dmamap_ate32(struct pcidev_info *info,
-		   u64 paddr, size_t req_size, u64 flags, int dma_flags)
-{
-
-	struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
-	struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
-	    pdi_pcibus_info;
-	u8 internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info->
-					    pdi_linux_pcidev->devfn)) - 1;
-	int ate_count;
-	int ate_index;
-	u64 ate_flags = flags | PCI32_ATE_V;
-	u64 ate;
-	u64 pci_addr;
-	u64 xio_addr;
-	u64 offset;
-
-	/* PIC in PCI-X mode does not supports 32bit PageMap mode */
-	if (IS_PIC_SOFT(pcibus_info) && IS_PCIX(pcibus_info)) {
-		return 0;
-	}
-
-	/* Calculate the number of ATEs needed. */
-	if (!(MINIMAL_ATE_FLAG(paddr, req_size))) {
-		ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
-				 +req_size	/* max mapping bytes */
-				 - 1) + 1;	/* round UP */
-	} else {		/* assume requested target is page aligned */
-		ate_count = IOPG(req_size	/* max mapping bytes */
-				 - 1) + 1;	/* round UP */
-	}
-
-	/* Get the number of ATEs required. */
-	ate_index = pcibr_ate_alloc(pcibus_info, ate_count);
-	if (ate_index < 0)
-		return 0;
-
-	/* In PCI-X mode, Prefetch not supported */
-	if (IS_PCIX(pcibus_info))
-		ate_flags &= ~(PCI32_ATE_PREF);
-
-	if (SN_DMA_ADDRTYPE(dma_flags == SN_DMA_ADDR_PHYS))
-		xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
-	    					      PHYS_TO_TIODMA(paddr);
-	else
-		xio_addr = paddr;
-
-	offset = IOPGOFF(xio_addr);
-	ate = ate_flags | (xio_addr - offset);
-
-	/* If PIC, put the targetid in the ATE */
-	if (IS_PIC_SOFT(pcibus_info)) {
-		ate |= (pcibus_info->pbi_hub_xid << PIC_ATE_TARGETID_SHFT);
-	}
-
-	/*
-	 * If we're mapping for MSI, set the MSI bit in the ATE.  If it's a
-	 * TIOCP based pci bus, we also need to set the PIO bit in the ATE.
-	 */
-	if (dma_flags & SN_DMA_MSI) {
-		ate |= PCI32_ATE_MSI;
-		if (IS_TIOCP_SOFT(pcibus_info))
-			ate |= PCI32_ATE_PIO;
-	}
-
-	ate_write(pcibus_info, ate_index, ate_count, ate);
-
-	/*
-	 * Set up the DMA mapped Address.
-	 */
-	pci_addr = PCI32_MAPPED_BASE + offset + IOPGSIZE * ate_index;
-
-	/*
-	 * If swap was set in device in pcibr_endian_set()
-	 * we need to turn swapping on.
-	 */
-	if (pcibus_info->pbi_devreg[internal_device] & PCIBR_DEV_SWAP_DIR)
-		ATE_SWAP_ON(pci_addr);
-
-
-	return pci_addr;
-}
-
-static dma_addr_t
-pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
-			u64 dma_attributes, int dma_flags)
-{
-	struct pcibus_info *pcibus_info = (struct pcibus_info *)
-	    ((info->pdi_host_pcidev_info)->pdi_pcibus_info);
-	u64 pci_addr;
-
-	/* Translate to Crosstalk View of Physical Address */
-	if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
-		pci_addr = IS_PIC_SOFT(pcibus_info) ?
-				PHYS_TO_DMA(paddr) :
-				PHYS_TO_TIODMA(paddr);
-	else
-		pci_addr = paddr;
-	pci_addr |= dma_attributes;
-
-	/* Handle Bus mode */
-	if (IS_PCIX(pcibus_info))
-		pci_addr &= ~PCI64_ATTR_PREF;
-
-	/* Handle Bridge Chipset differences */
-	if (IS_PIC_SOFT(pcibus_info)) {
-		pci_addr |=
-		    ((u64) pcibus_info->
-		     pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT);
-	} else
-		pci_addr |= (dma_flags & SN_DMA_MSI) ?
-				TIOCP_PCI64_CMDTYPE_MSI :
-				TIOCP_PCI64_CMDTYPE_MEM;
-
-	/* If PCI mode, func zero uses VCHAN0, every other func uses VCHAN1 */
-	if (!IS_PCIX(pcibus_info) && PCI_FUNC(info->pdi_linux_pcidev->devfn))
-		pci_addr |= PCI64_ATTR_VIRTUAL;
-
-	return pci_addr;
-}
-
-static dma_addr_t
-pcibr_dmatrans_direct32(struct pcidev_info * info,
-			u64 paddr, size_t req_size, u64 flags, int dma_flags)
-{
-	struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
-	struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
-	    pdi_pcibus_info;
-	u64 xio_addr;
-
-	u64 xio_base;
-	u64 offset;
-	u64 endoff;
-
-	if (IS_PCIX(pcibus_info)) {
-		return 0;
-	}
-
-	if (dma_flags & SN_DMA_MSI)
-		return 0;
-
-	if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
-		xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
-	    					      PHYS_TO_TIODMA(paddr);
-	else
-		xio_addr = paddr;
-
-	xio_base = pcibus_info->pbi_dir_xbase;
-	offset = xio_addr - xio_base;
-	endoff = req_size + offset;
-	if ((req_size > (1ULL << 31)) ||	/* Too Big */
-	    (xio_addr < xio_base) ||	/* Out of range for mappings */
-	    (endoff > (1ULL << 31))) {	/* Too Big */
-		return 0;
-	}
-
-	return PCI32_DIRECT_BASE | offset;
-}
-
-/*
- * Wrapper routine for freeing DMA maps
- * DMA mappings for Direct 64 and 32 do not have any DMA maps.
- */
-void
-pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction)
-{
-	struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
-	struct pcibus_info *pcibus_info =
-	    (struct pcibus_info *)pcidev_info->pdi_pcibus_info;
-
-	if (IS_PCI32_MAPPED(dma_handle)) {
-		int ate_index;
-
-		ate_index =
-		    IOPG((ATE_SWAP_OFF(dma_handle) - PCI32_MAPPED_BASE));
-		pcibr_ate_free(pcibus_info, ate_index);
-	}
-}
-
-/*
- * On SN systems there is a race condition between a PIO read response and 
- * DMA's.  In rare cases, the read response may beat the DMA, causing the
- * driver to think that data in memory is complete and meaningful.  This code
- * eliminates that race.  This routine is called by the PIO read routines
- * after doing the read.  For PIC this routine then forces a fake interrupt
- * on another line, which is logically associated with the slot that the PIO
- * is addressed to.  It then spins while watching the memory location that
- * the interrupt is targeted to.  When the interrupt response arrives, we 
- * are sure that the DMA has landed in memory and it is safe for the driver
- * to proceed.	For TIOCP use the Device(x) Write Request Buffer Flush 
- * Bridge register since it ensures the data has entered the coherence domain,
- * unlike the PIC Device(x) Write Request Buffer Flush register.
- */
-
-void sn_dma_flush(u64 addr)
-{
-	nasid_t nasid;
-	int is_tio;
-	int wid_num;
-	int i, j;
-	unsigned long flags;
-	u64 itte;
-	struct hubdev_info *hubinfo;
-	struct sn_flush_device_kernel *p;
-	struct sn_flush_device_common *common;
-	struct sn_flush_nasid_entry *flush_nasid_list;
-
-	if (!sn_ioif_inited)
-		return;
-
-	nasid = NASID_GET(addr);
-	if (-1 == nasid_to_cnodeid(nasid))
-		return;
-
-	hubinfo = (NODEPDA(nasid_to_cnodeid(nasid)))->pdinfo;
-
-	BUG_ON(!hubinfo);
-
-	flush_nasid_list = &hubinfo->hdi_flush_nasid_list;
-	if (flush_nasid_list->widget_p == NULL)
-		return;
-
-	is_tio = (nasid & 1);
-	if (is_tio) {
-		int itte_index;
-
-		if (TIO_HWIN(addr))
-			itte_index = 0;
-		else if (TIO_BWIN_WINDOWNUM(addr))
-			itte_index = TIO_BWIN_WINDOWNUM(addr);
-		else
-			itte_index = -1;
-
-		if (itte_index >= 0) {
-			itte = flush_nasid_list->iio_itte[itte_index];
-			if (! TIO_ITTE_VALID(itte))
-				return;
-			wid_num = TIO_ITTE_WIDGET(itte);
-		} else
-			wid_num = TIO_SWIN_WIDGETNUM(addr);
-	} else {
-		if (BWIN_WINDOWNUM(addr)) {
-			itte = flush_nasid_list->iio_itte[BWIN_WINDOWNUM(addr)];
-			wid_num = IIO_ITTE_WIDGET(itte);
-		} else
-			wid_num = SWIN_WIDGETNUM(addr);
-	}
-	if (flush_nasid_list->widget_p[wid_num] == NULL)
-		return;
-	p = &flush_nasid_list->widget_p[wid_num][0];
-
-	/* find a matching BAR */
-	for (i = 0; i < DEV_PER_WIDGET; i++,p++) {
-		common = p->common;
-		for (j = 0; j < PCI_ROM_RESOURCE; j++) {
-			if (common->sfdl_bar_list[j].start == 0)
-				break;
-			if (addr >= common->sfdl_bar_list[j].start
-			    && addr <= common->sfdl_bar_list[j].end)
-				break;
-		}
-		if (j < PCI_ROM_RESOURCE && common->sfdl_bar_list[j].start != 0)
-			break;
-	}
-
-	/* if no matching BAR, return without doing anything. */
-	if (i == DEV_PER_WIDGET)
-		return;
-
-	/*
-	 * For TIOCP use the Device(x) Write Request Buffer Flush Bridge
-	 * register since it ensures the data has entered the coherence
-	 * domain, unlike PIC.
-	 */
-	if (is_tio) {
-		/*
-	 	 * Note:  devices behind TIOCE should never be matched in the
-		 * above code, and so the following code is PIC/CP centric.
-		 * If CE ever needs the sn_dma_flush mechanism, we will have
-		 * to account for that here and in tioce_bus_fixup().
-	 	 */
-		u32 tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID));
-		u32 revnum = XWIDGET_PART_REV_NUM(tio_id);
-
-		/* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */
-		if ((1 << XWIDGET_PART_REV_NUM_REV(revnum)) & PV907516) {
-			return;
-		} else {
-			pcireg_wrb_flush_get(common->sfdl_pcibus_info,
-					     (common->sfdl_slot - 1));
-		}
-	} else {
-		spin_lock_irqsave(&p->sfdl_flush_lock, flags);
-		*common->sfdl_flush_addr = 0;
-
-		/* force an interrupt. */
-		*(volatile u32 *)(common->sfdl_force_int_addr) = 1;
-
-		/* wait for the interrupt to come back. */
-		while (*(common->sfdl_flush_addr) != 0x10f)
-			cpu_relax();
-
-		/* okay, everything is synched up. */
-		spin_unlock_irqrestore(&p->sfdl_flush_lock, flags);
-	}
-	return;
-}
-
-/*
- * DMA interfaces.  Called from pci_dma.c routines.
- */
-
-dma_addr_t
-pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size, int dma_flags)
-{
-	dma_addr_t dma_handle;
-	struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
-
-	/* SN cannot support DMA addresses smaller than 32 bits. */
-	if (hwdev->dma_mask < 0x7fffffff) {
-		return 0;
-	}
-
-	if (hwdev->dma_mask == ~0UL) {
-		/*
-		 * Handle the most common case: 64 bit cards.  This
-		 * call should always succeed.
-		 */
-
-		dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr,
-						     PCI64_ATTR_PREF, dma_flags);
-	} else {
-		/* Handle 32-63 bit cards via direct mapping */
-		dma_handle = pcibr_dmatrans_direct32(pcidev_info, phys_addr,
-						     size, 0, dma_flags);
-		if (!dma_handle) {
-			/*
-			 * It is a 32 bit card and we cannot do direct mapping,
-			 * so we use an ATE.
-			 */
-
-			dma_handle = pcibr_dmamap_ate32(pcidev_info, phys_addr,
-							size, PCI32_ATE_PREF,
-							dma_flags);
-		}
-	}
-
-	return dma_handle;
-}
-
-dma_addr_t
-pcibr_dma_map_consistent(struct pci_dev * hwdev, unsigned long phys_addr,
-			 size_t size, int dma_flags)
-{
-	dma_addr_t dma_handle;
-	struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev);
-
-	if (hwdev->dev.coherent_dma_mask == ~0UL) {
-		dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr,
-					    PCI64_ATTR_BAR, dma_flags);
-	} else {
-		dma_handle = (dma_addr_t) pcibr_dmamap_ate32(pcidev_info,
-						    phys_addr, size,
-						    PCI32_ATE_BAR, dma_flags);
-	}
-
-	return dma_handle;
-}
-
-EXPORT_SYMBOL(sn_dma_flush);
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
deleted file mode 100644
index 7195df1da121..000000000000
--- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001-2004, 2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/pci.h>
-#include <linux/export.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/geo.h>
-#include <asm/sn/pcibr_provider.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/pic.h>
-#include <asm/sn/sn2/sn_hwperf.h>
-#include "xtalk/xwidgetdev.h"
-#include "xtalk/hubdev.h"
-
-int
-sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp,
-                      char **ssdt)
-{
-	struct ia64_sal_retval ret_stuff;
-	u64 busnum;
-	u64 segment;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	segment = soft->pbi_buscommon.bs_persist_segment;
-	busnum = soft->pbi_buscommon.bs_persist_busnum;
-	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
-			busnum, (u64) device, (u64) resp, (u64)ia64_tpa(ssdt),
-			0, 0);
-
-	return (int)ret_stuff.v0;
-}
-
-int
-sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
-		       void *resp)
-{
-	struct ia64_sal_retval ret_stuff;
-	u64 busnum;
-	u64 segment;
-
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	segment = soft->pbi_buscommon.bs_persist_segment;
-	busnum = soft->pbi_buscommon.bs_persist_busnum;
-	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
-			segment, busnum, (u64) device, (u64) action,
-			(u64) resp, 0, 0);
-
-	return (int)ret_stuff.v0;
-}
-
-static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
-{
-	struct ia64_sal_retval ret_stuff;
-	u64 busnum;
-	int segment;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	segment = soft->pbi_buscommon.bs_persist_segment;
-	busnum = soft->pbi_buscommon.bs_persist_busnum;
-	SAL_CALL_NOLOCK(ret_stuff,
-			(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
-			(u64) segment, (u64) busnum, 0, 0, 0, 0, 0);
-
-	return (int)ret_stuff.v0;
-}
-
-u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus)
-{
-	long rc;
-	u16 uninitialized_var(ioboard);		/* GCC be quiet */
-	nasid_t nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);
-
-	rc = ia64_sn_sysctl_ioboard_get(nasid, &ioboard);
-	if (rc) {
-		printk(KERN_WARNING "ia64_sn_sysctl_ioboard_get failed: %ld\n",
-		       rc);
-		return 0;
-	}
-
-	return ioboard;
-}
-
-/* 
- * PCI Bridge Error interrupt handler.  Gets invoked whenever a PCI 
- * bridge sends an error interrupt.
- */
-static irqreturn_t
-pcibr_error_intr_handler(int irq, void *arg)
-{
-	struct pcibus_info *soft = arg;
-
-	if (sal_pcibr_error_interrupt(soft) < 0)
-		panic("pcibr_error_intr_handler(): Fatal Bridge Error");
-
-	return IRQ_HANDLED;
-}
-
-void *
-pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
-{
-	int nasid, cnode, j;
-	struct hubdev_info *hubdev_info;
-	struct pcibus_info *soft;
-	struct sn_flush_device_kernel *sn_flush_device_kernel;
-	struct sn_flush_device_common *common;
-
-	if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
-		return NULL;
-	}
-
-	/*
-	 * Allocate kernel bus soft and copy from prom.
-	 */
-
-	soft = kmemdup(prom_bussoft, sizeof(struct pcibus_info), GFP_KERNEL);
-	if (!soft) {
-		return NULL;
-	}
-
-	soft->pbi_buscommon.bs_base = (unsigned long)
-		ioremap(REGION_OFFSET(soft->pbi_buscommon.bs_base),
-			sizeof(struct pic));
-
-	spin_lock_init(&soft->pbi_lock);
-
-	/*
-	 * register the bridge's error interrupt handler
-	 */
-	if (request_irq(SGI_PCIASIC_ERROR, pcibr_error_intr_handler,
-			IRQF_SHARED, "PCIBR error", (void *)(soft))) {
-		printk(KERN_WARNING
-		       "pcibr cannot allocate interrupt for error handler\n");
-	}
-	irq_set_handler(SGI_PCIASIC_ERROR, handle_level_irq);
-	sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
-
-	/* 
-	 * Update the Bridge with the "kernel" pagesize 
-	 */
-	if (PAGE_SIZE < 16384) {
-		pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
-	} else {
-		pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
-	}
-
-	nasid = NASID_GET(soft->pbi_buscommon.bs_base);
-	cnode = nasid_to_cnodeid(nasid);
-	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
-
-	if (hubdev_info->hdi_flush_nasid_list.widget_p) {
-		sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
-		    widget_p[(int)soft->pbi_buscommon.bs_xid];
-		if (sn_flush_device_kernel) {
-			for (j = 0; j < DEV_PER_WIDGET;
-			     j++, sn_flush_device_kernel++) {
-				common = sn_flush_device_kernel->common;
-				if (common->sfdl_slot == -1)
-					continue;
-				if ((common->sfdl_persistent_segment ==
-				     soft->pbi_buscommon.bs_persist_segment) &&
-				     (common->sfdl_persistent_busnum ==
-				     soft->pbi_buscommon.bs_persist_busnum))
-					common->sfdl_pcibus_info =
-					    soft;
-			}
-		}
-	}
-
-	/* Setup the PMU ATE map */
-	soft->pbi_int_ate_resource.lowest_free_index = 0;
-	soft->pbi_int_ate_resource.ate =
-	    kcalloc(soft->pbi_int_ate_size, sizeof(u64), GFP_KERNEL);
-
-	if (!soft->pbi_int_ate_resource.ate) {
-		kfree(soft);
-		return NULL;
-	}
-
-	return soft;
-}
-
-void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
-{
-	struct pcidev_info *pcidev_info;
-	struct pcibus_info *pcibus_info;
-	int bit = sn_irq_info->irq_int_bit;
-
-	if (! sn_irq_info->irq_bridge)
-		return;
-
-	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
-	if (pcidev_info) {
-		pcibus_info =
-		    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
-		    pdi_pcibus_info;
-		pcireg_force_intr_set(pcibus_info, bit);
-	}
-}
-
-void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
-{
-	struct pcidev_info *pcidev_info;
-	struct pcibus_info *pcibus_info;
-	int bit = sn_irq_info->irq_int_bit;
-	u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
-
-	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
-	if (pcidev_info) {
-		pcibus_info =
-		    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
-		    pdi_pcibus_info;
-
-		/* Disable the device's IRQ   */
-		pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));
-
-		/* Change the device's IRQ    */
-		pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
-
-		/* Re-enable the device's IRQ */
-		pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));
-
-		pcibr_force_interrupt(sn_irq_info);
-	}
-}
-
-/*
- * Provider entries for PIC/CP
- */
-
-struct sn_pcibus_provider pcibr_provider = {
-	.dma_map = pcibr_dma_map,
-	.dma_map_consistent = pcibr_dma_map_consistent,
-	.dma_unmap = pcibr_dma_unmap,
-	.bus_fixup = pcibr_bus_fixup,
-	.force_interrupt = pcibr_force_interrupt,
-	.target_interrupt = pcibr_target_interrupt
-};
-
-int
-pcibr_init_provider(void)
-{
-	sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
-	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
-EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);
-EXPORT_SYMBOL_GPL(sn_ioboard_to_pci_bus);
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
deleted file mode 100644
index 8b8bbd51d433..000000000000
--- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
- */
-
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <asm/sn/io.h>
-#include <asm/sn/pcibr_provider.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/pic.h>
-#include <asm/sn/tiocp.h>
-
-union br_ptr {
-	struct tiocp tio;
-	struct pic pic;
-};
-
-/*
- * Control Register Access -- Read/Write                            0000_0020
- */
-void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			__sn_clrq_relaxed(&ptr->tio.cp_control, bits);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			__sn_clrq_relaxed(&ptr->pic.p_wid_control, bits);
-			break;
-		default:
-			panic
-			    ("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-}
-
-void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u64 bits)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			__sn_setq_relaxed(&ptr->tio.cp_control, bits);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			__sn_setq_relaxed(&ptr->pic.p_wid_control, bits);
-			break;
-		default:
-			panic
-			    ("pcireg_control_bit_set: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-}
-
-/*
- * PCI/PCIX Target Flush Register Access -- Read Only		    0000_0050
- */
-u64 pcireg_tflush_get(struct pcibus_info *pcibus_info)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-	u64 ret = 0;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			ret = __sn_readq_relaxed(&ptr->tio.cp_tflush);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			ret = __sn_readq_relaxed(&ptr->pic.p_wid_tflush);
-			break;
-		default:
-			panic
-			    ("pcireg_tflush_get: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-
-	/* Read of the Target Flush should always return zero */
-	if (ret != 0)
-		panic("pcireg_tflush_get:Target Flush failed\n");
-
-	return ret;
-}
-
-/*
- * Interrupt Status Register Access -- Read Only		    0000_0100
- */
-u64 pcireg_intr_status_get(struct pcibus_info * pcibus_info)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-	u64 ret = 0;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			ret = __sn_readq_relaxed(&ptr->tio.cp_int_status);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			ret = __sn_readq_relaxed(&ptr->pic.p_int_status);
-			break;
-		default:
-			panic
-			    ("pcireg_intr_status_get: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-	return ret;
-}
-
-/*
- * Interrupt Enable Register Access -- Read/Write                   0000_0108
- */
-void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			__sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			__sn_clrq_relaxed(&ptr->pic.p_int_enable, bits);
-			break;
-		default:
-			panic
-			    ("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-}
-
-void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u64 bits)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			__sn_setq_relaxed(&ptr->tio.cp_int_enable, bits);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			__sn_setq_relaxed(&ptr->pic.p_int_enable, bits);
-			break;
-		default:
-			panic
-			    ("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-}
-
-/*
- * Intr Host Address Register (int_addr) -- Read/Write  0000_0130 - 0000_0168
- */
-void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
-			       u64 addr)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			__sn_clrq_relaxed(&ptr->tio.cp_int_addr[int_n],
-			    TIOCP_HOST_INTR_ADDR);
-			__sn_setq_relaxed(&ptr->tio.cp_int_addr[int_n],
-			    (addr & TIOCP_HOST_INTR_ADDR));
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			__sn_clrq_relaxed(&ptr->pic.p_int_addr[int_n],
-			    PIC_HOST_INTR_ADDR);
-			__sn_setq_relaxed(&ptr->pic.p_int_addr[int_n],
-			    (addr & PIC_HOST_INTR_ADDR));
-			break;
-		default:
-			panic
-			    ("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-}
-
-/*
- * Force Interrupt Register Access -- Write Only	0000_01C0 - 0000_01F8
- */
-void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			writeq(1, &ptr->tio.cp_force_pin[int_n]);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			writeq(1, &ptr->pic.p_force_pin[int_n]);
-			break;
-		default:
-			panic
-			    ("pcireg_force_intr_set: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-}
-
-/*
- * Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
- */
-u64 pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-	u64 ret = 0;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			ret =
-			    __sn_readq_relaxed(&ptr->tio.cp_wr_req_buf[device]);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			ret =
-			    __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);
-			break;
-		default:
-		      panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr);
-		}
-
-	}
-	/* Read of the Write Buffer Flush should always return zero */
-	return ret;
-}
-
-void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
-			u64 val)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			writeq(val, &ptr->tio.cp_int_ate_ram[ate_index]);
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			writeq(val, &ptr->pic.p_int_ate_ram[ate_index]);
-			break;
-		default:
-			panic
-			    ("pcireg_int_ate_set: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-}
-
-u64 __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
-{
-	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-	u64 __iomem *ret = NULL;
-
-	if (pcibus_info) {
-		switch (pcibus_info->pbi_bridge_type) {
-		case PCIBR_BRIDGETYPE_TIOCP:
-			ret = &ptr->tio.cp_int_ate_ram[ate_index];
-			break;
-		case PCIBR_BRIDGETYPE_PIC:
-			ret = &ptr->pic.p_int_ate_ram[ate_index];
-			break;
-		default:
-			panic
-			    ("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p",
-			     ptr);
-		}
-	}
-	return ret;
-}
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
deleted file mode 100644
index a70b11fd57d6..000000000000
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ /dev/null
@@ -1,677 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003-2005 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/bitmap.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/io.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/tioca_provider.h>
-
-u32 tioca_gart_found;
-EXPORT_SYMBOL(tioca_gart_found);	/* used by agp-sgi */
-
-LIST_HEAD(tioca_list);
-EXPORT_SYMBOL(tioca_list);	/* used by agp-sgi */
-
-static int tioca_gart_init(struct tioca_kernel *);
-
-/**
- * tioca_gart_init - Initialize SGI TIOCA GART
- * @tioca_common: ptr to common prom/kernel struct identifying the 
- *
- * If the indicated tioca has devices present, initialize its associated
- * GART MMR's and kernel memory.
- */
-static int
-tioca_gart_init(struct tioca_kernel *tioca_kern)
-{
-	u64 ap_reg;
-	u64 offset;
-	struct page *tmp;
-	struct tioca_common *tioca_common;
-	struct tioca __iomem *ca_base;
-
-	tioca_common = tioca_kern->ca_common;
-	ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
-
-	if (list_empty(tioca_kern->ca_devices))
-		return 0;
-
-	ap_reg = 0;
-
-	/*
-	 * Validate aperature size
-	 */
-
-	switch (CA_APERATURE_SIZE >> 20) {
-	case 4:
-		ap_reg |= (0x3ff << CA_GART_AP_SIZE_SHFT);	/* 4MB */
-		break;
-	case 8:
-		ap_reg |= (0x3fe << CA_GART_AP_SIZE_SHFT);	/* 8MB */
-		break;
-	case 16:
-		ap_reg |= (0x3fc << CA_GART_AP_SIZE_SHFT);	/* 16MB */
-		break;
-	case 32:
-		ap_reg |= (0x3f8 << CA_GART_AP_SIZE_SHFT);	/* 32 MB */
-		break;
-	case 64:
-		ap_reg |= (0x3f0 << CA_GART_AP_SIZE_SHFT);	/* 64 MB */
-		break;
-	case 128:
-		ap_reg |= (0x3e0 << CA_GART_AP_SIZE_SHFT);	/* 128 MB */
-		break;
-	case 256:
-		ap_reg |= (0x3c0 << CA_GART_AP_SIZE_SHFT);	/* 256 MB */
-		break;
-	case 512:
-		ap_reg |= (0x380 << CA_GART_AP_SIZE_SHFT);	/* 512 MB */
-		break;
-	case 1024:
-		ap_reg |= (0x300 << CA_GART_AP_SIZE_SHFT);	/* 1GB */
-		break;
-	case 2048:
-		ap_reg |= (0x200 << CA_GART_AP_SIZE_SHFT);	/* 2GB */
-		break;
-	case 4096:
-		ap_reg |= (0x000 << CA_GART_AP_SIZE_SHFT);	/* 4 GB */
-		break;
-	default:
-		printk(KERN_ERR "%s:  Invalid CA_APERATURE_SIZE "
-		       "0x%lx\n", __func__, (ulong) CA_APERATURE_SIZE);
-		return -1;
-	}
-
-	/*
-	 * Set up other aperature parameters
-	 */
-
-	if (PAGE_SIZE >= 16384) {
-		tioca_kern->ca_ap_pagesize = 16384;
-		ap_reg |= CA_GART_PAGE_SIZE;
-	} else {
-		tioca_kern->ca_ap_pagesize = 4096;
-	}
-
-	tioca_kern->ca_ap_size = CA_APERATURE_SIZE;
-	tioca_kern->ca_ap_bus_base = CA_APERATURE_BASE;
-	tioca_kern->ca_gart_entries =
-	    tioca_kern->ca_ap_size / tioca_kern->ca_ap_pagesize;
-
-	ap_reg |= (CA_GART_AP_ENB_AGP | CA_GART_AP_ENB_PCI);
-	ap_reg |= tioca_kern->ca_ap_bus_base;
-
-	/*
-	 * Allocate and set up the GART
-	 */
-
-	tioca_kern->ca_gart_size = tioca_kern->ca_gart_entries * sizeof(u64);
-	tmp =
-	    alloc_pages_node(tioca_kern->ca_closest_node,
-			     GFP_KERNEL | __GFP_ZERO,
-			     get_order(tioca_kern->ca_gart_size));
-
-	if (!tmp) {
-		printk(KERN_ERR "%s:  Could not allocate "
-		       "%llu bytes (order %d) for GART\n",
-		       __func__,
-		       tioca_kern->ca_gart_size,
-		       get_order(tioca_kern->ca_gart_size));
-		return -ENOMEM;
-	}
-
-	tioca_kern->ca_gart = page_address(tmp);
-	tioca_kern->ca_gart_coretalk_addr =
-	    PHYS_TO_TIODMA(virt_to_phys(tioca_kern->ca_gart));
-
-	/*
-	 * Compute PCI/AGP convenience fields 
-	 */
-
-	offset = CA_PCI32_MAPPED_BASE - CA_APERATURE_BASE;
-	tioca_kern->ca_pciap_base = CA_PCI32_MAPPED_BASE;
-	tioca_kern->ca_pciap_size = CA_PCI32_MAPPED_SIZE;
-	tioca_kern->ca_pcigart_start = offset / tioca_kern->ca_ap_pagesize;
-	tioca_kern->ca_pcigart_base =
-	    tioca_kern->ca_gart_coretalk_addr + offset;
-	tioca_kern->ca_pcigart =
-	    &tioca_kern->ca_gart[tioca_kern->ca_pcigart_start];
-	tioca_kern->ca_pcigart_entries =
-	    tioca_kern->ca_pciap_size / tioca_kern->ca_ap_pagesize;
-	tioca_kern->ca_pcigart_pagemap =
-	    kzalloc(tioca_kern->ca_pcigart_entries / 8, GFP_KERNEL);
-	if (!tioca_kern->ca_pcigart_pagemap) {
-		free_pages((unsigned long)tioca_kern->ca_gart,
-			   get_order(tioca_kern->ca_gart_size));
-		return -1;
-	}
-
-	offset = CA_AGP_MAPPED_BASE - CA_APERATURE_BASE;
-	tioca_kern->ca_gfxap_base = CA_AGP_MAPPED_BASE;
-	tioca_kern->ca_gfxap_size = CA_AGP_MAPPED_SIZE;
-	tioca_kern->ca_gfxgart_start = offset / tioca_kern->ca_ap_pagesize;
-	tioca_kern->ca_gfxgart_base =
-	    tioca_kern->ca_gart_coretalk_addr + offset;
-	tioca_kern->ca_gfxgart =
-	    &tioca_kern->ca_gart[tioca_kern->ca_gfxgart_start];
-	tioca_kern->ca_gfxgart_entries =
-	    tioca_kern->ca_gfxap_size / tioca_kern->ca_ap_pagesize;
-
-	/*
-	 * various control settings:
-	 *      use agp op-combining
-	 *      use GET semantics to fetch memory
-	 *      participate in coherency domain
-	 * 	DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029
-	 */
-
-	__sn_setq_relaxed(&ca_base->ca_control1,
-			CA_AGPDMA_OP_ENB_COMBDELAY);	/* PV895469 ? */
-	__sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
-	__sn_setq_relaxed(&ca_base->ca_control2,
-			(0x2ull << CA_GART_MEM_PARAM_SHFT));
-	tioca_kern->ca_gart_iscoherent = 1;
-	__sn_clrq_relaxed(&ca_base->ca_control2,
-	    		(CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB));
-
-	/*
-	 * Unmask GART fetch error interrupts.  Clear residual errors first.
-	 */
-
-	writeq(CA_GART_FETCH_ERR, &ca_base->ca_int_status_alias);
-	writeq(CA_GART_FETCH_ERR, &ca_base->ca_mult_error_alias);
-	__sn_clrq_relaxed(&ca_base->ca_int_mask, CA_GART_FETCH_ERR);
-
-	/*
-	 * Program the aperature and gart registers in TIOCA
-	 */
-
-	writeq(ap_reg, &ca_base->ca_gart_aperature);
-	writeq(tioca_kern->ca_gart_coretalk_addr|1, &ca_base->ca_gart_ptr_table);
-
-	return 0;
-}
-
-/**
- * tioca_fastwrite_enable - enable AGP FW for a tioca and its functions
- * @tioca_kernel: structure representing the CA
- *
- * Given a CA, scan all attached functions making sure they all support
- * FastWrite.  If so, enable FastWrite for all functions and the CA itself.
- */
-
-void
-tioca_fastwrite_enable(struct tioca_kernel *tioca_kern)
-{
-	int cap_ptr;
-	u32 reg;
-	struct tioca __iomem *tioca_base;
-	struct pci_dev *pdev;
-	struct tioca_common *common;
-
-	common = tioca_kern->ca_common;
-
-	/*
-	 * Scan all vga controllers on this bus making sure they all
-	 * support FW.  If not, return.
-	 */
-
-	list_for_each_entry(pdev, tioca_kern->ca_devices, bus_list) {
-		if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
-			continue;
-
-		cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
-		if (!cap_ptr)
-			return;	/* no AGP CAP means no FW */
-
-		pci_read_config_dword(pdev, cap_ptr + PCI_AGP_STATUS, &reg);
-		if (!(reg & PCI_AGP_STATUS_FW))
-			return;	/* function doesn't support FW */
-	}
-
-	/*
-	 * Set fw for all vga fn's
-	 */
-
-	list_for_each_entry(pdev, tioca_kern->ca_devices, bus_list) {
-		if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
-			continue;
-
-		cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
-		pci_read_config_dword(pdev, cap_ptr + PCI_AGP_COMMAND, &reg);
-		reg |= PCI_AGP_COMMAND_FW;
-		pci_write_config_dword(pdev, cap_ptr + PCI_AGP_COMMAND, reg);
-	}
-
-	/*
-	 * Set ca's fw to match
-	 */
-
-	tioca_base = (struct tioca __iomem*)common->ca_common.bs_base;
-	__sn_setq_relaxed(&tioca_base->ca_control1, CA_AGP_FW_ENABLE);
-}
-
-EXPORT_SYMBOL(tioca_fastwrite_enable);	/* used by agp-sgi */
-
-/**
- * tioca_dma_d64 - create a DMA mapping using 64-bit direct mode
- * @paddr: system physical address
- *
- * Map @paddr into 64-bit CA bus space.  No device context is necessary.
- * Bits 53:0 come from the coretalk address.  We just need to mask in the
- * following optional bits of the 64-bit pci address:
- *
- * 63:60 - Coretalk Packet Type -  0x1 for Mem Get/Put (coherent)
- *                                 0x2 for PIO (non-coherent)
- *                                 We will always use 0x1
- * 55:55 - Swap bytes		   Currently unused
- */
-static u64
-tioca_dma_d64(unsigned long paddr)
-{
-	dma_addr_t bus_addr;
-
-	bus_addr = PHYS_TO_TIODMA(paddr);
-
-	BUG_ON(!bus_addr);
-	BUG_ON(bus_addr >> 54);
-
-	/* Set upper nibble to Cache Coherent Memory op */
-	bus_addr |= (1UL << 60);
-
-	return bus_addr;
-}
-
-/**
- * tioca_dma_d48 - create a DMA mapping using 48-bit direct mode
- * @pdev: linux pci_dev representing the function
- * @paddr: system physical address
- *
- * Map @paddr into 64-bit bus space of the CA associated with @pcidev_info.
- *
- * The CA agp 48 bit direct address falls out as follows:
- *
- * When direct mapping AGP addresses, the 48 bit AGP address is
- * constructed as follows:
- *
- * [47:40] - Low 8 bits of the page Node ID extracted from coretalk
- *              address [47:40].  The upper 8 node bits are fixed
- *              and come from the xxx register bits [5:0]
- * [39:38] - Chiplet ID extracted from coretalk address [39:38]
- * [37:00] - node offset extracted from coretalk address [37:00]
- * 
- * Since the node id in general will be non-zero, and the chiplet id
- * will always be non-zero, it follows that the device must support
- * a dma mask of at least 0xffffffffff (40 bits) to target node 0
- * and in general should be 0xffffffffffff (48 bits) to target nodes
- * up to 255.  Nodes above 255 need the support of the xxx register,
- * and so a given CA can only directly target nodes in the range
- * xxx - xxx+255.
- */
-static u64
-tioca_dma_d48(struct pci_dev *pdev, u64 paddr)
-{
-	struct tioca_common *tioca_common;
-	struct tioca __iomem *ca_base;
-	u64 ct_addr;
-	dma_addr_t bus_addr;
-	u32 node_upper;
-	u64 agp_dma_extn;
-	struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
-
-	tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
-	ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
-
-	ct_addr = PHYS_TO_TIODMA(paddr);
-	if (!ct_addr)
-		return 0;
-
-	bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffffUL);
-	node_upper = ct_addr >> 48;
-
-	if (node_upper > 64) {
-		printk(KERN_ERR "%s:  coretalk addr 0x%p node id out "
-		       "of range\n", __func__, (void *)ct_addr);
-		return 0;
-	}
-
-	agp_dma_extn = __sn_readq_relaxed(&ca_base->ca_agp_dma_addr_extn);
-	if (node_upper != (agp_dma_extn >> CA_AGP_DMA_NODE_ID_SHFT)) {
-		printk(KERN_ERR "%s:  coretalk upper node (%u) "
-		       "mismatch with ca_agp_dma_addr_extn (%llu)\n",
-		       __func__,
-		       node_upper, (agp_dma_extn >> CA_AGP_DMA_NODE_ID_SHFT));
-		return 0;
-	}
-
-	return bus_addr;
-}
-
-/**
- * tioca_dma_mapped - create a DMA mapping using a CA GART 
- * @pdev: linux pci_dev representing the function
- * @paddr: host physical address to map
- * @req_size: len (bytes) to map
- *
- * Map @paddr into CA address space using the GART mechanism.  The mapped
- * dma_addr_t is guaranteed to be contiguous in CA bus space.
- */
-static dma_addr_t
-tioca_dma_mapped(struct pci_dev *pdev, unsigned long paddr, size_t req_size)
-{
-	int ps, ps_shift, entry, entries, mapsize;
-	u64 xio_addr, end_xio_addr;
-	struct tioca_common *tioca_common;
-	struct tioca_kernel *tioca_kern;
-	dma_addr_t bus_addr = 0;
-	struct tioca_dmamap *ca_dmamap;
-	void *map;
-	unsigned long flags;
-	struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
-
-	tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
-	tioca_kern = (struct tioca_kernel *)tioca_common->ca_kernel_private;
-
-	xio_addr = PHYS_TO_TIODMA(paddr);
-	if (!xio_addr)
-		return 0;
-
-	spin_lock_irqsave(&tioca_kern->ca_lock, flags);
-
-	/*
-	 * allocate a map struct
-	 */
-
-	ca_dmamap = kzalloc(sizeof(struct tioca_dmamap), GFP_ATOMIC);
-	if (!ca_dmamap)
-		goto map_return;
-
-	/*
-	 * Locate free entries that can hold req_size.  Account for
-	 * unaligned start/length when allocating.
-	 */
-
-	ps = tioca_kern->ca_ap_pagesize;	/* will be power of 2 */
-	ps_shift = ffs(ps) - 1;
-	end_xio_addr = xio_addr + req_size - 1;
-
-	entries = (end_xio_addr >> ps_shift) - (xio_addr >> ps_shift) + 1;
-
-	map = tioca_kern->ca_pcigart_pagemap;
-	mapsize = tioca_kern->ca_pcigart_entries;
-
-	entry = bitmap_find_next_zero_area(map, mapsize, 0, entries, 0);
-	if (entry >= mapsize) {
-		kfree(ca_dmamap);
-		goto map_return;
-	}
-
-	bitmap_set(map, entry, entries);
-
-	bus_addr = tioca_kern->ca_pciap_base + (entry * ps);
-
-	ca_dmamap->cad_dma_addr = bus_addr;
-	ca_dmamap->cad_gart_size = entries;
-	ca_dmamap->cad_gart_entry = entry;
-	list_add(&ca_dmamap->cad_list, &tioca_kern->ca_dmamaps);
-
-	if (xio_addr % ps) {
-		tioca_kern->ca_pcigart[entry] = tioca_paddr_to_gart(xio_addr);
-		bus_addr += xio_addr & (ps - 1);
-		xio_addr &= ~(ps - 1);
-		xio_addr += ps;
-		entry++;
-	}
-
-	while (xio_addr < end_xio_addr) {
-		tioca_kern->ca_pcigart[entry] = tioca_paddr_to_gart(xio_addr);
-		xio_addr += ps;
-		entry++;
-	}
-
-	tioca_tlbflush(tioca_kern);
-
-map_return:
-	spin_unlock_irqrestore(&tioca_kern->ca_lock, flags);
-	return bus_addr;
-}
-
-/**
- * tioca_dma_unmap - release CA mapping resources
- * @pdev: linux pci_dev representing the function
- * @bus_addr: bus address returned by an earlier tioca_dma_map
- * @dir: mapping direction (unused)
- *
- * Locate mapping resources associated with @bus_addr and release them.
- * For mappings created using the direct modes (64 or 48) there are no
- * resources to release.
- */
-static void
-tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
-{
-	int i, entry;
-	struct tioca_common *tioca_common;
-	struct tioca_kernel *tioca_kern;
-	struct tioca_dmamap *map;
-	struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
-	unsigned long flags;
-
-	tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
-	tioca_kern = (struct tioca_kernel *)tioca_common->ca_kernel_private;
-
-	/* return straight away if this isn't be a mapped address */
-
-	if (bus_addr < tioca_kern->ca_pciap_base ||
-	    bus_addr >= (tioca_kern->ca_pciap_base + tioca_kern->ca_pciap_size))
-		return;
-
-	spin_lock_irqsave(&tioca_kern->ca_lock, flags);
-
-	list_for_each_entry(map, &tioca_kern->ca_dmamaps, cad_list)
-	    if (map->cad_dma_addr == bus_addr)
-		break;
-
-	BUG_ON(map == NULL);
-
-	entry = map->cad_gart_entry;
-
-	for (i = 0; i < map->cad_gart_size; i++, entry++) {
-		clear_bit(entry, tioca_kern->ca_pcigart_pagemap);
-		tioca_kern->ca_pcigart[entry] = 0;
-	}
-	tioca_tlbflush(tioca_kern);
-
-	list_del(&map->cad_list);
-	spin_unlock_irqrestore(&tioca_kern->ca_lock, flags);
-	kfree(map);
-}
-
-/**
- * tioca_dma_map - map pages for PCI DMA
- * @pdev: linux pci_dev representing the function
- * @paddr: host physical address to map
- * @byte_count: bytes to map
- *
- * This is the main wrapper for mapping host physical pages to CA PCI space.
- * The mapping mode used is based on the devices dma_mask.  As a last resort
- * use the GART mapped mode.
- */
-static u64
-tioca_dma_map(struct pci_dev *pdev, unsigned long paddr, size_t byte_count, int dma_flags)
-{
-	u64 mapaddr;
-
-	/*
-	 * Not supported for now ...
-	 */
-	if (dma_flags & SN_DMA_MSI)
-		return 0;
-
-	/*
-	 * If card is 64 or 48 bit addressable, use a direct mapping.  32
-	 * bit direct is so restrictive w.r.t. where the memory resides that
-	 * we don't use it even though CA has some support.
-	 */
-
-	if (pdev->dma_mask == ~0UL)
-		mapaddr = tioca_dma_d64(paddr);
-	else if (pdev->dma_mask == 0xffffffffffffUL)
-		mapaddr = tioca_dma_d48(pdev, paddr);
-	else
-		mapaddr = 0;
-
-	/* Last resort ... use PCI portion of CA GART */
-
-	if (mapaddr == 0)
-		mapaddr = tioca_dma_mapped(pdev, paddr, byte_count);
-
-	return mapaddr;
-}
-
-/**
- * tioca_error_intr_handler - SGI TIO CA error interrupt handler
- * @irq: unused
- * @arg: pointer to tioca_common struct for the given CA
- *
- * Handle a CA error interrupt.  Simply a wrapper around a SAL call which
- * defers processing to the SGI prom.
- */
-static irqreturn_t
-tioca_error_intr_handler(int irq, void *arg)
-{
-	struct tioca_common *soft = arg;
-	struct ia64_sal_retval ret_stuff;
-	u64 segment;
-	u64 busnum;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	segment = soft->ca_common.bs_persist_segment;
-	busnum = soft->ca_common.bs_persist_busnum;
-
-	SAL_CALL_NOLOCK(ret_stuff,
-			(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
-			segment, busnum, 0, 0, 0, 0, 0);
-
-	return IRQ_HANDLED;
-}
-
-/**
- * tioca_bus_fixup - perform final PCI fixup for a TIO CA bus
- * @prom_bussoft: Common prom/kernel struct representing the bus
- *
- * Replicates the tioca_common pointed to by @prom_bussoft in kernel
- * space.  Allocates and initializes a kernel-only area for a given CA,
- * and sets up an irq for handling CA error interrupts.
- *
- * On successful setup, returns the kernel version of tioca_common back to
- * the caller.
- */
-static void *
-tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
-{
-	struct tioca_common *tioca_common;
-	struct tioca_kernel *tioca_kern;
-	struct pci_bus *bus;
-
-	/* sanity check prom rev */
-
-	if (is_shub1() && sn_sal_rev() < 0x0406) {
-		printk
-		    (KERN_ERR "%s:  SGI prom rev 4.06 or greater required "
-		     "for tioca support\n", __func__);
-		return NULL;
-	}
-
-	/*
-	 * Allocate kernel bus soft and copy from prom.
-	 */
-
-	tioca_common = kmemdup(prom_bussoft, sizeof(struct tioca_common),
-			       GFP_KERNEL);
-	if (!tioca_common)
-		return NULL;
-
-	tioca_common->ca_common.bs_base = (unsigned long)
-		ioremap(REGION_OFFSET(tioca_common->ca_common.bs_base),
-			sizeof(struct tioca_common));
-
-	/* init kernel-private area */
-
-	tioca_kern = kzalloc(sizeof(struct tioca_kernel), GFP_KERNEL);
-	if (!tioca_kern) {
-		kfree(tioca_common);
-		return NULL;
-	}
-
-	tioca_kern->ca_common = tioca_common;
-	spin_lock_init(&tioca_kern->ca_lock);
-	INIT_LIST_HEAD(&tioca_kern->ca_dmamaps);
-	tioca_kern->ca_closest_node =
-	    nasid_to_cnodeid(tioca_common->ca_closest_nasid);
-	tioca_common->ca_kernel_private = (u64) tioca_kern;
-
-	bus = pci_find_bus(tioca_common->ca_common.bs_persist_segment,
-		tioca_common->ca_common.bs_persist_busnum);
-	BUG_ON(!bus);
-	tioca_kern->ca_devices = &bus->devices;
-
-	/* init GART */
-
-	if (tioca_gart_init(tioca_kern) < 0) {
-		kfree(tioca_kern);
-		kfree(tioca_common);
-		return NULL;
-	}
-
-	tioca_gart_found++;
-	list_add(&tioca_kern->ca_list, &tioca_list);
-
-	if (request_irq(SGI_TIOCA_ERROR,
-			tioca_error_intr_handler,
-			IRQF_SHARED, "TIOCA error", (void *)tioca_common))
-		printk(KERN_WARNING
-		       "%s:  Unable to get irq %d.  "
-		       "Error interrupts won't be routed for TIOCA bus %d\n",
-		       __func__, SGI_TIOCA_ERROR,
-		       (int)tioca_common->ca_common.bs_persist_busnum);
-
-	irq_set_handler(SGI_TIOCA_ERROR, handle_level_irq);
-	sn_set_err_irq_affinity(SGI_TIOCA_ERROR);
-
-	/* Setup locality information */
-	controller->node = tioca_kern->ca_closest_node;
-	return tioca_common;
-}
-
-static struct sn_pcibus_provider tioca_pci_interfaces = {
-	.dma_map = tioca_dma_map,
-	.dma_map_consistent = tioca_dma_map,
-	.dma_unmap = tioca_dma_unmap,
-	.bus_fixup = tioca_bus_fixup,
-	.force_interrupt = NULL,
-	.target_interrupt = NULL
-};
-
-/**
- * tioca_init_provider - init SN PCI provider ops for TIO CA
- */
-int
-tioca_init_provider(void)
-{
-	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCA] = &tioca_pci_interfaces;
-	return 0;
-}
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
deleted file mode 100644
index 3bd9abc35485..000000000000
--- a/arch/ia64/sn/pci/tioce_provider.c
+++ /dev/null
@@ -1,1062 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/slab.h>
-#include <linux/pci.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/io.h>
-#include <asm/sn/pcidev.h>
-#include <asm/sn/pcibus_provider_defs.h>
-#include <asm/sn/tioce_provider.h>
-
-/*
- * 1/26/2006
- *
- * WAR for SGI PV 944642.  For revA TIOCE, need to use the following recipe
- * (taken from the above PV) before and after accessing tioce internal MMR's
- * to avoid tioce lockups.
- *
- * The recipe as taken from the PV:
- *
- *	if(mmr address < 0x45000) {
- *		if(mmr address == 0 or 0x80)
- *			mmr wrt or read address 0xc0
- *		else if(mmr address == 0x148 or 0x200)
- *			mmr wrt or read address 0x28
- *		else
- *			mmr wrt or read address 0x158
- *
- *		do desired mmr access (rd or wrt)
- *
- *		if(mmr address == 0x100)
- *			mmr wrt or read address 0x38
- *		mmr wrt or read address 0xb050
- *	} else
- *		do desired mmr access
- *
- * According to hw, we can use reads instead of writes to the above address
- *
- * Note this WAR can only to be used for accessing internal MMR's in the
- * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff.  This includes the
- * "Local CE Registers and Memories" and "PCI Compatible Config Space" address
- * spaces from table 2-1 of the "CE Programmer's Reference Overview" document.
- *
- * All registers defined in struct tioce will meet that criteria.
- */
-
-static inline void
-tioce_mmr_war_pre(struct tioce_kernel *kern, void __iomem *mmr_addr)
-{
-	u64 mmr_base;
-	u64 mmr_offset;
-
-	if (kern->ce_common->ce_rev != TIOCE_REV_A)
-		return;
-
-	mmr_base = kern->ce_common->ce_pcibus.bs_base;
-	mmr_offset = (unsigned long)mmr_addr - mmr_base;
-
-	if (mmr_offset < 0x45000) {
-		u64 mmr_war_offset;
-
-		if (mmr_offset == 0 || mmr_offset == 0x80)
-			mmr_war_offset = 0xc0;
-		else if (mmr_offset == 0x148 || mmr_offset == 0x200)
-			mmr_war_offset = 0x28;
-		else
-			mmr_war_offset = 0x158;
-
-		readq_relaxed((void __iomem *)(mmr_base + mmr_war_offset));
-	}
-}
-
-static inline void
-tioce_mmr_war_post(struct tioce_kernel *kern, void __iomem *mmr_addr)
-{
-	u64 mmr_base;
-	u64 mmr_offset;
-
-	if (kern->ce_common->ce_rev != TIOCE_REV_A)
-		return;
-
-	mmr_base = kern->ce_common->ce_pcibus.bs_base;
-	mmr_offset = (unsigned long)mmr_addr - mmr_base;
-
-	if (mmr_offset < 0x45000) {
-		if (mmr_offset == 0x100)
-			readq_relaxed((void __iomem *)(mmr_base + 0x38));
-		readq_relaxed((void __iomem *)(mmr_base + 0xb050));
-	}
-}
-
-/* load mmr contents into a variable */
-#define tioce_mmr_load(kern, mmrp, varp) do {\
-	tioce_mmr_war_pre(kern, mmrp); \
-	*(varp) = readq_relaxed(mmrp); \
-	tioce_mmr_war_post(kern, mmrp); \
-} while (0)
-
-/* store variable contents into mmr */
-#define tioce_mmr_store(kern, mmrp, varp) do {\
-	tioce_mmr_war_pre(kern, mmrp); \
-	writeq(*varp, mmrp); \
-	tioce_mmr_war_post(kern, mmrp); \
-} while (0)
-
-/* store immediate value into mmr */
-#define tioce_mmr_storei(kern, mmrp, val) do {\
-	tioce_mmr_war_pre(kern, mmrp); \
-	writeq(val, mmrp); \
-	tioce_mmr_war_post(kern, mmrp); \
-} while (0)
-
-/* set bits (immediate value) into mmr */
-#define tioce_mmr_seti(kern, mmrp, bits) do {\
-	u64 tmp; \
-	tioce_mmr_load(kern, mmrp, &tmp); \
-	tmp |= (bits); \
-	tioce_mmr_store(kern, mmrp, &tmp); \
-} while (0)
-
-/* clear bits (immediate value) into mmr */
-#define tioce_mmr_clri(kern, mmrp, bits) do { \
-	u64 tmp; \
-	tioce_mmr_load(kern, mmrp, &tmp); \
-	tmp &= ~(bits); \
-	tioce_mmr_store(kern, mmrp, &tmp); \
-} while (0)
-
-/**
- * Bus address ranges for the 5 flavors of TIOCE DMA
- */
-
-#define TIOCE_D64_MIN	0x8000000000000000UL
-#define TIOCE_D64_MAX	0xffffffffffffffffUL
-#define TIOCE_D64_ADDR(a)	((a) >= TIOCE_D64_MIN)
-
-#define TIOCE_D32_MIN	0x0000000080000000UL
-#define TIOCE_D32_MAX	0x00000000ffffffffUL
-#define TIOCE_D32_ADDR(a)	((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX)
-
-#define TIOCE_M32_MIN	0x0000000000000000UL
-#define TIOCE_M32_MAX	0x000000007fffffffUL
-#define TIOCE_M32_ADDR(a)	((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX)
-
-#define TIOCE_M40_MIN	0x0000004000000000UL
-#define TIOCE_M40_MAX	0x0000007fffffffffUL
-#define TIOCE_M40_ADDR(a)	((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX)
-
-#define TIOCE_M40S_MIN	0x0000008000000000UL
-#define TIOCE_M40S_MAX	0x000000ffffffffffUL
-#define TIOCE_M40S_ADDR(a)	((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX)
-
-/*
- * ATE manipulation macros.
- */
-
-#define ATE_PAGESHIFT(ps)	(__ffs(ps))
-#define ATE_PAGEMASK(ps)	((ps)-1)
-
-#define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps))
-#define ATE_NPAGES(start, len, pagesize) \
-	(ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1)
-
-#define ATE_VALID(ate)	((ate) & (1UL << 63))
-#define ATE_MAKE(addr, ps, msi) \
-	(((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63) | ((msi)?(1UL << 62):0))
-
-/*
- * Flavors of ate-based mapping supported by tioce_alloc_map()
- */
-
-#define TIOCE_ATE_M32	1
-#define TIOCE_ATE_M40	2
-#define TIOCE_ATE_M40S	3
-
-#define KB(x)	((u64)(x) << 10)
-#define MB(x)	((u64)(x) << 20)
-#define GB(x)	((u64)(x) << 30)
-
-/**
- * tioce_dma_d64 - create a DMA mapping using 64-bit direct mode
- * @ct_addr: system coretalk address
- *
- * Map @ct_addr into 64-bit CE bus space.  No device context is necessary
- * and no CE mapping are consumed.
- *
- * Bits 53:0 come from the coretalk address.  The remaining bits are set as
- * follows:
- *
- * 63    - must be 1 to indicate d64 mode to CE hardware
- * 62    - barrier bit ... controlled with tioce_dma_barrier()
- * 61    - msi bit ... specified through dma_flags
- * 60:54 - reserved, MBZ
- */
-static u64
-tioce_dma_d64(unsigned long ct_addr, int dma_flags)
-{
-	u64 bus_addr;
-
-	bus_addr = ct_addr | (1UL << 63);
-	if (dma_flags & SN_DMA_MSI)
-		bus_addr |= (1UL << 61);
-
-	return bus_addr;
-}
-
-/**
- * pcidev_to_tioce - return misc ce related pointers given a pci_dev
- * @pci_dev: pci device context
- * @base: ptr to store struct tioce_mmr * for the CE holding this device
- * @kernel: ptr to store struct tioce_kernel * for the CE holding this device
- * @port: ptr to store the CE port number that this device is on
- *
- * Return pointers to various CE-related structures for the CE upstream of
- * @pci_dev.
- */
-static inline void
-pcidev_to_tioce(struct pci_dev *pdev, struct tioce __iomem **base,
-		struct tioce_kernel **kernel, int *port)
-{
-	struct pcidev_info *pcidev_info;
-	struct tioce_common *ce_common;
-	struct tioce_kernel *ce_kernel;
-
-	pcidev_info = SN_PCIDEV_INFO(pdev);
-	ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
-	ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
-
-	if (base)
-		*base = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
-	if (kernel)
-		*kernel = ce_kernel;
-
-	/*
-	 * we use port as a zero-based value internally, even though the
-	 * documentation is 1-based.
-	 */
-	if (port)
-		*port =
-		    (pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1;
-}
-
-/**
- * tioce_alloc_map - Given a coretalk address, map it to pcie bus address
- * space using one of the various ATE-based address modes.
- * @ce_kern: tioce context
- * @type: map mode to use
- * @port: 0-based port that the requesting device is downstream of
- * @ct_addr: the coretalk address to map
- * @len: number of bytes to map
- *
- * Given the addressing type, set up various parameters that define the
- * ATE pool to use.  Search for a contiguous block of entries to cover the
- * length, and if enough resources exist, fill in the ATEs and construct a
- * tioce_dmamap struct to track the mapping.
- */
-static u64
-tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
-		u64 ct_addr, int len, int dma_flags)
-{
-	int i;
-	int j;
-	int first;
-	int last;
-	int entries;
-	int nates;
-	u64 pagesize;
-	int msi_capable, msi_wanted;
-	u64 *ate_shadow;
-	u64 __iomem *ate_reg;
-	u64 addr;
-	struct tioce __iomem *ce_mmr;
-	u64 bus_base;
-	struct tioce_dmamap *map;
-
-	ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
-
-	switch (type) {
-	case TIOCE_ATE_M32:
-		/*
-		 * The first 64 entries of the ate3240 pool are dedicated to
-		 * super-page (TIOCE_ATE_M40S) mode.
-		 */
-		first = 64;
-		entries = TIOCE_NUM_M3240_ATES - 64;
-		ate_shadow = ce_kern->ce_ate3240_shadow;
-		ate_reg = ce_mmr->ce_ure_ate3240;
-		pagesize = ce_kern->ce_ate3240_pagesize;
-		bus_base = TIOCE_M32_MIN;
-		msi_capable = 1;
-		break;
-	case TIOCE_ATE_M40:
-		first = 0;
-		entries = TIOCE_NUM_M40_ATES;
-		ate_shadow = ce_kern->ce_ate40_shadow;
-		ate_reg = ce_mmr->ce_ure_ate40;
-		pagesize = MB(64);
-		bus_base = TIOCE_M40_MIN;
-		msi_capable = 0;
-		break;
-	case TIOCE_ATE_M40S:
-		/*
-		 * ate3240 entries 0-31 are dedicated to port1 super-page
-		 * mappings.  ate3240 entries 32-63 are dedicated to port2.
-		 */
-		first = port * 32;
-		entries = 32;
-		ate_shadow = ce_kern->ce_ate3240_shadow;
-		ate_reg = ce_mmr->ce_ure_ate3240;
-		pagesize = GB(16);
-		bus_base = TIOCE_M40S_MIN;
-		msi_capable = 0;
-		break;
-	default:
-		return 0;
-	}
-
-	msi_wanted = dma_flags & SN_DMA_MSI;
-	if (msi_wanted && !msi_capable)
-		return 0;
-
-	nates = ATE_NPAGES(ct_addr, len, pagesize);
-	if (nates > entries)
-		return 0;
-
-	last = first + entries - nates;
-	for (i = first; i <= last; i++) {
-		if (ATE_VALID(ate_shadow[i]))
-			continue;
-
-		for (j = i; j < i + nates; j++)
-			if (ATE_VALID(ate_shadow[j]))
-				break;
-
-		if (j >= i + nates)
-			break;
-	}
-
-	if (i > last)
-		return 0;
-
-	map = kzalloc(sizeof(struct tioce_dmamap), GFP_ATOMIC);
-	if (!map)
-		return 0;
-
-	addr = ct_addr;
-	for (j = 0; j < nates; j++) {
-		u64 ate;
-
-		ate = ATE_MAKE(addr, pagesize, msi_wanted);
-		ate_shadow[i + j] = ate;
-		tioce_mmr_storei(ce_kern, &ate_reg[i + j], ate);
-		addr += pagesize;
-	}
-
-	map->refcnt = 1;
-	map->nbytes = nates * pagesize;
-	map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize);
-	map->pci_start = bus_base + (i * pagesize);
-	map->ate_hw = &ate_reg[i];
-	map->ate_shadow = &ate_shadow[i];
-	map->ate_count = nates;
-
-	list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list);
-
-	return (map->pci_start + (ct_addr - map->ct_start));
-}
-
-/**
- * tioce_dma_d32 - create a DMA mapping using 32-bit direct mode
- * @pdev: linux pci_dev representing the function
- * @paddr: system physical address
- *
- * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
- */
-static u64
-tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr, int dma_flags)
-{
-	int dma_ok;
-	int port;
-	struct tioce __iomem *ce_mmr;
-	struct tioce_kernel *ce_kern;
-	u64 ct_upper;
-	u64 ct_lower;
-	dma_addr_t bus_addr;
-
-	if (dma_flags & SN_DMA_MSI)
-		return 0;
-
-	ct_upper = ct_addr & ~0x3fffffffUL;
-	ct_lower = ct_addr & 0x3fffffffUL;
-
-	pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
-
-	if (ce_kern->ce_port[port].dirmap_refcnt == 0) {
-		u64 tmp;
-
-		ce_kern->ce_port[port].dirmap_shadow = ct_upper;
-		tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port],
-				 ct_upper);
-		tmp = ce_mmr->ce_ure_dir_map[port];
-		dma_ok = 1;
-	} else
-		dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper);
-
-	if (dma_ok) {
-		ce_kern->ce_port[port].dirmap_refcnt++;
-		bus_addr = TIOCE_D32_MIN + ct_lower;
-	} else
-		bus_addr = 0;
-
-	return bus_addr;
-}
-
-/**
- * tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude
- * the barrier bit.
- * @bus_addr:  bus address to swizzle
- *
- * Given a TIOCE bus address, set the appropriate bit to indicate barrier
- * attributes.
- */
-static u64
-tioce_dma_barrier(u64 bus_addr, int on)
-{
-	u64 barrier_bit;
-
-	/* barrier not supported in M40/M40S mode */
-	if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr))
-		return bus_addr;
-
-	if (TIOCE_D64_ADDR(bus_addr))
-		barrier_bit = (1UL << 62);
-	else			/* must be m32 or d32 */
-		barrier_bit = (1UL << 30);
-
-	return (on) ? (bus_addr | barrier_bit) : (bus_addr & ~barrier_bit);
-}
-
-/**
- * tioce_dma_unmap - release CE mapping resources
- * @pdev: linux pci_dev representing the function
- * @bus_addr: bus address returned by an earlier tioce_dma_map
- * @dir: mapping direction (unused)
- *
- * Locate mapping resources associated with @bus_addr and release them.
- * For mappings created using the direct modes there are no resources
- * to release.
- */
-void
-tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
-{
-	int i;
-	int port;
-	struct tioce_kernel *ce_kern;
-	struct tioce __iomem *ce_mmr;
-	unsigned long flags;
-
-	bus_addr = tioce_dma_barrier(bus_addr, 0);
-	pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
-
-	/* nothing to do for D64 */
-
-	if (TIOCE_D64_ADDR(bus_addr))
-		return;
-
-	spin_lock_irqsave(&ce_kern->ce_lock, flags);
-
-	if (TIOCE_D32_ADDR(bus_addr)) {
-		if (--ce_kern->ce_port[port].dirmap_refcnt == 0) {
-			ce_kern->ce_port[port].dirmap_shadow = 0;
-			tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port],
-					 0);
-		}
-	} else {
-		struct tioce_dmamap *map;
-
-		list_for_each_entry(map, &ce_kern->ce_dmamap_list,
-				    ce_dmamap_list) {
-			u64 last;
-
-			last = map->pci_start + map->nbytes - 1;
-			if (bus_addr >= map->pci_start && bus_addr <= last)
-				break;
-		}
-
-		if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) {
-			printk(KERN_WARNING
-			       "%s:  %s - no map found for bus_addr 0x%llx\n",
-			       __func__, pci_name(pdev), bus_addr);
-		} else if (--map->refcnt == 0) {
-			for (i = 0; i < map->ate_count; i++) {
-				map->ate_shadow[i] = 0;
-				tioce_mmr_storei(ce_kern, &map->ate_hw[i], 0);
-			}
-
-			list_del(&map->ce_dmamap_list);
-			kfree(map);
-		}
-	}
-
-	spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
-}
-
-/**
- * tioce_do_dma_map - map pages for PCI DMA
- * @pdev: linux pci_dev representing the function
- * @paddr: host physical address to map
- * @byte_count: bytes to map
- *
- * This is the main wrapper for mapping host physical pages to CE PCI space.
- * The mapping mode used is based on the device's dma_mask.
- */
-static u64
-tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
-		 int barrier, int dma_flags)
-{
-	unsigned long flags;
-	u64 ct_addr;
-	u64 mapaddr = 0;
-	struct tioce_kernel *ce_kern;
-	struct tioce_dmamap *map;
-	int port;
-	u64 dma_mask;
-
-	dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask;
-
-	/* cards must be able to address at least 31 bits */
-	if (dma_mask < 0x7fffffffUL)
-		return 0;
-
-	if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
-		ct_addr = PHYS_TO_TIODMA(paddr);
-	else
-		ct_addr = paddr;
-
-	/*
-	 * If the device can generate 64 bit addresses, create a D64 map.
-	 */
-	if (dma_mask == ~0UL) {
-		mapaddr = tioce_dma_d64(ct_addr, dma_flags);
-		if (mapaddr)
-			goto dma_map_done;
-	}
-
-	pcidev_to_tioce(pdev, NULL, &ce_kern, &port);
-
-	spin_lock_irqsave(&ce_kern->ce_lock, flags);
-
-	/*
-	 * D64 didn't work ... See if we have an existing map that covers
-	 * this address range.  Must account for devices dma_mask here since
-	 * an existing map might have been done in a mode using more pci
-	 * address bits than this device can support.
-	 */
-	list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) {
-		u64 last;
-
-		last = map->ct_start + map->nbytes - 1;
-		if (ct_addr >= map->ct_start &&
-		    ct_addr + byte_count - 1 <= last &&
-		    map->pci_start <= dma_mask) {
-			map->refcnt++;
-			mapaddr = map->pci_start + (ct_addr - map->ct_start);
-			break;
-		}
-	}
-
-	/*
-	 * If we don't have a map yet, and the card can generate 40
-	 * bit addresses, try the M40/M40S modes.  Note these modes do not
-	 * support a barrier bit, so if we need a consistent map these
-	 * won't work.
-	 */
-	if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) {
-		/*
-		 * We have two options for 40-bit mappings:  16GB "super" ATEs
-		 * and 64MB "regular" ATEs.  We'll try both if needed for a
-		 * given mapping but which one we try first depends on the
-		 * size.  For requests >64MB, prefer to use a super page with
-		 * regular as the fallback. Otherwise, try in the reverse order.
-		 */
-
-		if (byte_count > MB(64)) {
-			mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
-						  port, ct_addr, byte_count,
-						  dma_flags);
-			if (!mapaddr)
-				mapaddr =
-				    tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
-						    ct_addr, byte_count,
-						    dma_flags);
-		} else {
-			mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
-						  ct_addr, byte_count,
-						  dma_flags);
-			if (!mapaddr)
-				mapaddr =
-				    tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
-						    port, ct_addr, byte_count,
-						    dma_flags);
-		}
-	}
-
-	/*
-	 * 32-bit direct is the next mode to try
-	 */
-	if (!mapaddr && dma_mask >= 0xffffffffUL)
-		mapaddr = tioce_dma_d32(pdev, ct_addr, dma_flags);
-
-	/*
-	 * Last resort, try 32-bit ATE-based map.
-	 */
-	if (!mapaddr)
-		mapaddr =
-		    tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr,
-				    byte_count, dma_flags);
-
-	spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
-
-dma_map_done:
-	if (mapaddr && barrier)
-		mapaddr = tioce_dma_barrier(mapaddr, 1);
-
-	return mapaddr;
-}
-
-/**
- * tioce_dma - standard pci dma map interface
- * @pdev: pci device requesting the map
- * @paddr: system physical address to map into pci space
- * @byte_count: # bytes to map
- *
- * Simply call tioce_do_dma_map() to create a map with the barrier bit clear
- * in the address.
- */
-static u64
-tioce_dma(struct pci_dev *pdev, unsigned long  paddr, size_t byte_count, int dma_flags)
-{
-	return tioce_do_dma_map(pdev, paddr, byte_count, 0, dma_flags);
-}
-
-/**
- * tioce_dma_consistent - consistent pci dma map interface
- * @pdev: pci device requesting the map
- * @paddr: system physical address to map into pci space
- * @byte_count: # bytes to map
- *
- * Simply call tioce_do_dma_map() to create a map with the barrier bit set
- * in the address.
- */
-static u64
-tioce_dma_consistent(struct pci_dev *pdev, unsigned long  paddr, size_t byte_count, int dma_flags)
-{
-	return tioce_do_dma_map(pdev, paddr, byte_count, 1, dma_flags);
-}
-
-/**
- * tioce_error_intr_handler - SGI TIO CE error interrupt handler
- * @irq: unused
- * @arg: pointer to tioce_common struct for the given CE
- *
- * Handle a CE error interrupt.  Simply a wrapper around a SAL call which
- * defers processing to the SGI prom.
- */
-static irqreturn_t
-tioce_error_intr_handler(int irq, void *arg)
-{
-	struct tioce_common *soft = arg;
-	struct ia64_sal_retval ret_stuff;
-	ret_stuff.status = 0;
-	ret_stuff.v0 = 0;
-
-	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
-			soft->ce_pcibus.bs_persist_segment,
-			soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0);
-
-	if (ret_stuff.v0)
-		panic("tioce_error_intr_handler:  Fatal TIOCE error");
-
-	return IRQ_HANDLED;
-}
-
-/**
- * tioce_reserve_m32 - reserve M32 ATEs for the indicated address range
- * @tioce_kernel: TIOCE context to reserve ATEs for
- * @base: starting bus address to reserve
- * @limit: last bus address to reserve
- *
- * If base/limit falls within the range of bus space mapped through the
- * M32 space, reserve the resources corresponding to the range.
- */
-static void
-tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
-{
-	int ate_index, last_ate, ps;
-	struct tioce __iomem *ce_mmr;
-
-	ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
-	ps = ce_kern->ce_ate3240_pagesize;
-	ate_index = ATE_PAGE(base, ps);
-	last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1;
-
-	if (ate_index < 64)
-		ate_index = 64;
-
-	if (last_ate >= TIOCE_NUM_M3240_ATES)
-		last_ate = TIOCE_NUM_M3240_ATES - 1;
-
-	while (ate_index <= last_ate) {
-		u64 ate;
-
-		ate = ATE_MAKE(0xdeadbeef, ps, 0);
-		ce_kern->ce_ate3240_shadow[ate_index] = ate;
-		tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_ate3240[ate_index],
-				 ate);
-		ate_index++;
-	}
-}
-
-/**
- * tioce_kern_init - init kernel structures related to a given TIOCE
- * @tioce_common: ptr to a cached tioce_common struct that originated in prom
- */
-static struct tioce_kernel *
-tioce_kern_init(struct tioce_common *tioce_common)
-{
-	int i;
-	int ps;
-	int dev;
-	u32 tmp;
-	unsigned int seg, bus;
-	struct tioce __iomem *tioce_mmr;
-	struct tioce_kernel *tioce_kern;
-
-	tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL);
-	if (!tioce_kern) {
-		return NULL;
-	}
-
-	tioce_kern->ce_common = tioce_common;
-	spin_lock_init(&tioce_kern->ce_lock);
-	INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list);
-	tioce_common->ce_kernel_private = (u64) tioce_kern;
-
-	/*
-	 * Determine the secondary bus number of the port2 logical PPB.
-	 * This is used to decide whether a given pci device resides on
-	 * port1 or port2.  Note:  We don't have enough plumbing set up
-	 * here to use pci_read_config_xxx() so use raw_pci_read().
-	 */
-
-	seg = tioce_common->ce_pcibus.bs_persist_segment;
-	bus = tioce_common->ce_pcibus.bs_persist_busnum;
-
-	raw_pci_read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp);
-	tioce_kern->ce_port1_secondary = (u8) tmp;
-
-	/*
-	 * Set PMU pagesize to the largest size available, and zero out
-	 * the ATEs.
-	 */
-
-	tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
-	tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map,
-		       CE_URE_PAGESIZE_MASK);
-	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map,
-		       CE_URE_256K_PAGESIZE);
-	ps = tioce_kern->ce_ate3240_pagesize = KB(256);
-
-	for (i = 0; i < TIOCE_NUM_M40_ATES; i++) {
-		tioce_kern->ce_ate40_shadow[i] = 0;
-		tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate40[i], 0);
-	}
-
-	for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) {
-		tioce_kern->ce_ate3240_shadow[i] = 0;
-		tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate3240[i], 0);
-	}
-
-	/*
-	 * Reserve ATEs corresponding to reserved address ranges.  These
-	 * include:
-	 *
-	 *	Memory space covered by each PPB mem base/limit register
-	 * 	Memory space covered by each PPB prefetch base/limit register
-	 *
-	 * These bus ranges are for pio (downstream) traffic only, and so
-	 * cannot be used for DMA.
-	 */
-
-	for (dev = 1; dev <= 2; dev++) {
-		u64 base, limit;
-
-		/* mem base/limit */
-
-		raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
-				  PCI_MEMORY_BASE, 2, &tmp);
-		base = (u64)tmp << 16;
-
-		raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
-				  PCI_MEMORY_LIMIT, 2, &tmp);
-		limit = (u64)tmp << 16;
-		limit |= 0xfffffUL;
-
-		if (base < limit)
-			tioce_reserve_m32(tioce_kern, base, limit);
-
-		/*
-		 * prefetch mem base/limit.  The tioce ppb's have 64-bit
-		 * decoders, so read the upper portions w/o checking the
-		 * attributes.
-		 */
-
-		raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
-				  PCI_PREF_MEMORY_BASE, 2, &tmp);
-		base = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
-
-		raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
-				  PCI_PREF_BASE_UPPER32, 4, &tmp);
-		base |= (u64)tmp << 32;
-
-		raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
-				  PCI_PREF_MEMORY_LIMIT, 2, &tmp);
-
-		limit = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
-		limit |= 0xfffffUL;
-
-		raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
-				  PCI_PREF_LIMIT_UPPER32, 4, &tmp);
-		limit |= (u64)tmp << 32;
-
-		if ((base < limit) && TIOCE_M32_ADDR(base))
-			tioce_reserve_m32(tioce_kern, base, limit);
-	}
-
-	return tioce_kern;
-}
-
-/**
- * tioce_force_interrupt - implement altix force_interrupt() backend for CE
- * @sn_irq_info: sn asic irq that we need an interrupt generated for
- *
- * Given an sn_irq_info struct, set the proper bit in ce_adm_force_int to
- * force a secondary interrupt to be generated.  This is to work around an
- * asic issue where there is a small window of opportunity for a legacy device
- * interrupt to be lost.
- */
-static void
-tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
-{
-	struct pcidev_info *pcidev_info;
-	struct tioce_common *ce_common;
-	struct tioce_kernel *ce_kern;
-	struct tioce __iomem *ce_mmr;
-	u64 force_int_val;
-
-	if (!sn_irq_info->irq_bridge)
-		return;
-
-	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE)
-		return;
-
-	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
-	if (!pcidev_info)
-		return;
-
-	ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
-	ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
-	ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
-
-	/*
-	 * TIOCE Rev A workaround (PV 945826), force an interrupt by writing
-	 * the TIO_INTx register directly (1/26/2006)
-	 */
-	if (ce_common->ce_rev == TIOCE_REV_A) {
-		u64 int_bit_mask = (1ULL << sn_irq_info->irq_int_bit);
-		u64 status;
-
-		tioce_mmr_load(ce_kern, &ce_mmr->ce_adm_int_status, &status);
-		if (status & int_bit_mask) {
-			u64 force_irq = (1 << 8) | sn_irq_info->irq_irq;
-			u64 ctalk = sn_irq_info->irq_xtalkaddr;
-			u64 nasid, offset;
-
-			nasid = (ctalk & CTALK_NASID_MASK) >> CTALK_NASID_SHFT;
-			offset = (ctalk & CTALK_NODE_OFFSET);
-			HUB_S(TIO_IOSPACE_ADDR(nasid, offset), force_irq);
-		}
-
-		return;
-	}
-
-	/*
-	 * irq_int_bit is originally set up by prom, and holds the interrupt
-	 * bit shift (not mask) as defined by the bit definitions in the
-	 * ce_adm_int mmr.  These shifts are not the same for the
-	 * ce_adm_force_int register, so do an explicit mapping here to make
-	 * things clearer.
-	 */
-
-	switch (sn_irq_info->irq_int_bit) {
-	case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT:
-		force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT;
-		break;
-	case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT:
-		force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT;
-		break;
-	case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT:
-		force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT;
-		break;
-	case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT:
-		force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT;
-		break;
-	case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT:
-		force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT;
-		break;
-	case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT:
-		force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT;
-		break;
-	case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT:
-		force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT;
-		break;
-	case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT:
-		force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT;
-		break;
-	default:
-		return;
-	}
-	tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_force_int, force_int_val);
-}
-
-/**
- * tioce_target_interrupt - implement set_irq_affinity for tioce resident
- * functions.  Note:  only applies to line interrupts, not MSI's.
- *
- * @sn_irq_info: SN IRQ context
- *
- * Given an sn_irq_info, set the associated CE device's interrupt destination
- * register.  Since the interrupt destination registers are on a per-ce-slot
- * basis, this will retarget line interrupts for all functions downstream of
- * the slot.
- */
-static void
-tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
-{
-	struct pcidev_info *pcidev_info;
-	struct tioce_common *ce_common;
-	struct tioce_kernel *ce_kern;
-	struct tioce __iomem *ce_mmr;
-	int bit;
-	u64 vector;
-
-	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
-	if (!pcidev_info)
-		return;
-
-	ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
-	ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
-	ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
-
-	bit = sn_irq_info->irq_int_bit;
-
-	tioce_mmr_seti(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit));
-	vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT;
-	vector |= sn_irq_info->irq_xtalkaddr;
-	tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_int_dest[bit], vector);
-	tioce_mmr_clri(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit));
-
-	tioce_force_interrupt(sn_irq_info);
-}
-
-/**
- * tioce_bus_fixup - perform final PCI fixup for a TIO CE bus
- * @prom_bussoft: Common prom/kernel struct representing the bus
- *
- * Replicates the tioce_common pointed to by @prom_bussoft in kernel
- * space.  Allocates and initializes a kernel-only area for a given CE,
- * and sets up an irq for handling CE error interrupts.
- *
- * On successful setup, returns the kernel version of tioce_common back to
- * the caller.
- */
-static void *
-tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
-{
-	struct tioce_common *tioce_common;
-	struct tioce_kernel *tioce_kern;
-	struct tioce __iomem *tioce_mmr;
-
-	/*
-	 * Allocate kernel bus soft and copy from prom.
-	 */
-
-	tioce_common = kzalloc(sizeof(struct tioce_common), GFP_KERNEL);
-	if (!tioce_common)
-		return NULL;
-
-	memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common));
-	tioce_common->ce_pcibus.bs_base = (unsigned long)
-		ioremap(REGION_OFFSET(tioce_common->ce_pcibus.bs_base),
-			sizeof(struct tioce_common));
-
-	tioce_kern = tioce_kern_init(tioce_common);
-	if (tioce_kern == NULL) {
-		kfree(tioce_common);
-		return NULL;
-	}
-
-	/*
-	 * Clear out any transient errors before registering the error
-	 * interrupt handler.
-	 */
-
-	tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
-	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL);
-	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias,
-		       ~0ULL);
-	tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_dre_comp_err_addr, 0ULL);
-
-	if (request_irq(SGI_PCIASIC_ERROR,
-			tioce_error_intr_handler,
-			IRQF_SHARED, "TIOCE error", (void *)tioce_common))
-		printk(KERN_WARNING
-		       "%s:  Unable to get irq %d.  "
-		       "Error interrupts won't be routed for "
-		       "TIOCE bus %04x:%02x\n",
-		       __func__, SGI_PCIASIC_ERROR,
-		       tioce_common->ce_pcibus.bs_persist_segment,
-		       tioce_common->ce_pcibus.bs_persist_busnum);
-
-	irq_set_handler(SGI_PCIASIC_ERROR, handle_level_irq);
-	sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
-	return tioce_common;
-}
-
-static struct sn_pcibus_provider tioce_pci_interfaces = {
-	.dma_map = tioce_dma,
-	.dma_map_consistent = tioce_dma_consistent,
-	.dma_unmap = tioce_dma_unmap,
-	.bus_fixup = tioce_bus_fixup,
-	.force_interrupt = tioce_force_interrupt,
-	.target_interrupt = tioce_target_interrupt
-};
-
-/**
- * tioce_init_provider - init SN PCI provider ops for TIO CE
- */
-int
-tioce_init_provider(void)
-{
-	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCE] = &tioce_pci_interfaces;
-	return 0;
-}
diff --git a/arch/ia64/uv/kernel/Makefile b/arch/ia64/uv/kernel/Makefile
index 124e441d383d..297196578d19 100644
--- a/arch/ia64/uv/kernel/Makefile
+++ b/arch/ia64/uv/kernel/Makefile
@@ -10,4 +10,3 @@
 ccflags-y := -Iarch/ia64/sn/include
 
 obj-y				+= setup.o
-obj-$(CONFIG_IA64_GENERIC)      += machvec.o
diff --git a/arch/ia64/uv/kernel/machvec.c b/arch/ia64/uv/kernel/machvec.c
deleted file mode 100644
index 50737a9dca74..000000000000
--- a/arch/ia64/uv/kernel/machvec.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2008 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#define MACHVEC_PLATFORM_NAME	uv
-#define MACHVEC_PLATFORM_HEADER	<asm/machvec_uv.h>
-#include <asm/machvec_init.h>
diff --git a/arch/ia64/uv/kernel/setup.c b/arch/ia64/uv/kernel/setup.c
index f1490657bafc..bb025486d791 100644
--- a/arch/ia64/uv/kernel/setup.c
+++ b/arch/ia64/uv/kernel/setup.c
@@ -8,25 +8,20 @@
  * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/acpi.h>
+#include <linux/efi.h>
 #include <linux/module.h>
 #include <linux/percpu.h>
-#include <asm/sn/simulator.h>
+#include <asm/uv/uv.h>
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
 
+bool ia64_is_uv;
+EXPORT_SYMBOL_GPL(ia64_is_uv);
+
 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 
-#ifdef CONFIG_IA64_SGI_UV
-int sn_prom_type;
-long sn_partition_id;
-EXPORT_SYMBOL(sn_partition_id);
-long sn_coherency_id;
-EXPORT_SYMBOL_GPL(sn_coherency_id);
-long sn_region_size;
-EXPORT_SYMBOL(sn_region_size);
-#endif
-
 struct redir_addr {
 	unsigned long redirect;
 	unsigned long alias;
@@ -58,6 +53,34 @@ static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 	BUG();
 }
 
+void __init uv_probe_system_type(void)
+{
+	struct acpi_table_rsdp *rsdp;
+	struct acpi_table_xsdt *xsdt;
+
+	if (efi.acpi20 == EFI_INVALID_TABLE_ADDR) {
+		pr_err("ACPI 2.0 RSDP not found.\n");
+		return;
+	}
+
+	rsdp = (struct acpi_table_rsdp *)__va(efi.acpi20);
+	if (strncmp(rsdp->signature, ACPI_SIG_RSDP, sizeof(ACPI_SIG_RSDP) - 1)) {
+		pr_err("ACPI 2.0 RSDP signature incorrect.\n");
+		return;
+	}
+
+	xsdt = (struct acpi_table_xsdt *)__va(rsdp->xsdt_physical_address);
+	if (strncmp(xsdt->header.signature, ACPI_SIG_XSDT,
+			sizeof(ACPI_SIG_XSDT) - 1)) {
+		pr_err("ACPI 2.0 XSDT signature incorrect.\n");
+		return;
+	}
+
+	if (!strcmp(xsdt->header.oem_id, "SGI") &&
+	    !strcmp(xsdt->header.oem_table_id + 4, "UV"))
+		ia64_is_uv = true;
+}
+
 void __init uv_setup(char **cmdline_p)
 {
 	union uvh_si_addr_map_config_u m_n_config;
@@ -66,30 +89,11 @@ void __init uv_setup(char **cmdline_p)
 	int nid, cpu, m_val, n_val;
 	unsigned long mmr_base, lowmem_redir_base, lowmem_redir_size;
 
-	if (IS_MEDUSA()) {
-		lowmem_redir_base = 0;
-		lowmem_redir_size = 0;
-		node_id.v = 0;
-		m_n_config.s.m_skt = 37;
-		m_n_config.s.n_skt = 0;
-		mmr_base = 0;
-#if 0
-		/* Need BIOS calls - TDB */
-		if (!ia64_sn_is_fake_prom())
-			sn_prom_type = 1;
-		else
-#endif
-			sn_prom_type = 2;
-		printk(KERN_INFO "Running on medusa with %s PROM\n",
-					(sn_prom_type == 1) ? "real" : "fake");
-	} else {
-		get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
-		node_id.v = uv_read_local_mmr(UVH_NODE_ID);
-		m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
-		mmr_base =
-			uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
-				~UV_MMR_ENABLE;
-	}
+	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
+	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
+	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
+	mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
+			~UV_MMR_ENABLE;
 
 	m_val = m_n_config.s.m_skt;
 	n_val = m_n_config.s.n_skt;