diff options
| author | Hirokazu Takata <takata@linux-m32r.org> | 2006-02-24 13:03:51 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-02-24 14:31:36 -0800 |
| commit | 6ced13cdcab440931b87829b0f2d0dedacfb3f2d (patch) | |
| tree | 8bdd7a80685a7069b30a0e03d32892a81ea8ca9c /arch/m32r/lib | |
| parent | cde05cf2145b0aa06dd61277060bfba5d38acb0b (diff) | |
| download | linux-stable-6ced13cdcab440931b87829b0f2d0dedacfb3f2d.tar.gz linux-stable-6ced13cdcab440931b87829b0f2d0dedacfb3f2d.tar.bz2 linux-stable-6ced13cdcab440931b87829b0f2d0dedacfb3f2d.zip | |
[PATCH] m32r: fix and update for gcc-4.0
Fix and update for gcc-4.0.
- arch/m32r/kernel/signal.c:
Change type of the 8th parameter of sys_rt_sigsuspend() from
'struct pt_regs' to 'struct pt_regs *'.
This functions make use of the 'regs' parameter to return status value,
but gcc-4.0 optimizes and removes it as a dead code.
Functions, sys_sigaltstack() and sys_rt_sigreturn(), have also modified.
- arch/m32r/lib/usercopy.c, include/asm-m32r/uaccess.h:
Add early-clobber constraints('&') to output values of asm statements;
these constraints seems to be required for gcc-4.0 register assignment.
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/m32r/lib')
| -rw-r--r-- | arch/m32r/lib/usercopy.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/m32r/lib/usercopy.c b/arch/m32r/lib/usercopy.c index ce16bbe26a52..2d1dd2106c4d 100644 --- a/arch/m32r/lib/usercopy.c +++ b/arch/m32r/lib/usercopy.c @@ -64,7 +64,7 @@ do { \ " .balign 4\n" \ " .long 0b,3b\n" \ ".previous" \ - : "=r"(res), "=r"(count), "=&r" (__d0), "=&r" (__d1), \ + : "=&r"(res), "=&r"(count), "=&r" (__d0), "=&r" (__d1), \ "=&r" (__d2) \ : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), \ "4"(dst) \ @@ -101,7 +101,7 @@ do { \ " .balign 4\n" \ " .long 0b,3b\n" \ ".previous" \ - : "=r"(res), "=r"(count), "=&r" (__d0), "=&r" (__d1), \ + : "=&r"(res), "=&r"(count), "=&r" (__d0), "=&r" (__d1), \ "=&r" (__d2) \ : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), \ "4"(dst) \ |