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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-03-14 21:51:26 +0900
committerRalf Baechle <ralf@linux-mips.org>2007-04-27 16:20:23 +0100
commit252161eccd1a44f32a506d0fedb424d4ff84e4dc (patch)
tree39c4c46d69b653b20047a0af7175f477ce54913e /arch/mips/cobalt
parent2a9effc67804102d6d5182eb0116520588ae2256 (diff)
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[MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routines
This patch has merged GT64111 PCI routines and GT64120 PCI_0 routines. GT64111 PCI is almost the same as GT64120's PCI_0. This patch don't change GT64120 PCI routines. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cobalt')
-rw-r--r--arch/mips/cobalt/pci.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c
index d01600639546..d91027f43de6 100644
--- a/arch/mips/cobalt/pci.c
+++ b/arch/mips/cobalt/pci.c
@@ -14,7 +14,7 @@
#include <asm/gt64120.h>
-extern struct pci_ops gt64111_pci_ops;
+extern struct pci_ops gt64xxx_pci0_ops;
static struct resource cobalt_mem_resource = {
.start = GT_DEF_PCI0_MEM0_BASE,
@@ -31,7 +31,7 @@ static struct resource cobalt_io_resource = {
};
static struct pci_controller cobalt_pci_controller = {
- .pci_ops = &gt64111_pci_ops,
+ .pci_ops = &gt64xxx_pci0_ops,
.mem_resource = &cobalt_mem_resource,
.io_resource = &cobalt_io_resource,
.io_offset = 0 - GT_DEF_PCI0_IO_BASE,