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| author | Steven J. Hill <sjhill@mips.com> | 2012-12-07 04:31:36 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-02-15 23:07:38 +0100 |
| commit | a96102be700f87283f168942cd09a2b30f86f324 (patch) | |
| tree | 65537d4868587037e25f2ae648ebfceb31274f36 /arch/mips/include/asm/cpu-features.h | |
| parent | 0e49caf661fbba12c9a38eca13b64d6680259018 (diff) | |
| download | linux-stable-a96102be700f87283f168942cd09a2b30f86f324.tar.gz linux-stable-a96102be700f87283f168942cd09a2b30f86f324.tar.bz2 linux-stable-a96102be700f87283f168942cd09a2b30f86f324.zip | |
MIPS: Add printing of ISA version in cpuinfo.
Display the MIPS ISA version release in the /proc/cpuinfo file.
[ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture
revisions. Also differenciate between MIPS32 and MIPS64 versions instead
of lumping them together as just r1 and r2.
Note to application programmers: this indicates the CPU's ISA level
It does not imply the current execution environment does support it. For
example an O32 application seeing "mips64r2" would still be restricted by
by the execution environment to 32-bit - but the kernel could run mips64r2
code. The same for a 32-bit kernel running on a 64-bit processor. This
field doesn't include ASEs or optional architecture modules nor other
detailed flags such as the availability of an FPU.]
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4714/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index e0ac24759d92..1e83b24fa461 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -130,6 +130,19 @@ #endif #endif +# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I) +#ifndef cpu_has_mips_2 +# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) +#endif +#ifndef cpu_has_mips_3 +# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) +#endif +#ifndef cpu_has_mips_4 +# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) +#endif +#ifndef cpu_has_mips_5 +# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) +#endif # ifndef cpu_has_mips32r1 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) # endif |