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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-01-05 12:48:25 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-01-05 12:48:25 -0800 |
| commit | 47f3f4eb7834ea424b0704bffd0d3e3c8ffbc3a1 (patch) | |
| tree | 14bb595d5bdc86fc94a8d780c72a5ee8583f4c49 /arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h | |
| parent | f1c2f8857c5aa6c92aa903bc06437503422e5925 (diff) | |
| parent | edefae94b7b9f10d5efe32dece5a36e9d9ecc29e (diff) | |
| download | linux-stable-47f3f4eb7834ea424b0704bffd0d3e3c8ffbc3a1.tar.gz linux-stable-47f3f4eb7834ea424b0704bffd0d3e3c8ffbc3a1.tar.bz2 linux-stable-47f3f4eb7834ea424b0704bffd0d3e3c8ffbc3a1.zip | |
Merge tag 'mips_fixes_4.21_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS fixes from Paul Burton:
"A few early MIPS fixes for 4.21:
- The Broadcom BCM63xx platform sees a fix for resetting the BCM6368
ethernet switch, and the removal of a platform device we've never
had a driver for.
- The Alchemy platform sees a few fixes for bitrot that occurred
within the past few cycles.
- We now enable vectored interrupt support for the MediaTek MT7620
SoC, which makes sense since they're supported by the SoC but in
this case also works around a bug relating to the location of
exception vectors when using a recent version of U-Boot.
- The atomic64_fetch_*_relaxed() family of functions see a fix for a
regression in MIPS64 kernels since v4.19.
- Cavium Octeon III CN7xxx systems will now disable their RGMII
interfaces rather than attempt to enable them & warn about the lack
of support for doing so, as they did since initial CN7xxx ethernet
support was added in v4.7.
- The Microsemi/Microchip MSCC SoCs gain a MAINTAINERS entry.
- .mailmap now provides consistency for Dengcheng Zhu's name &
current email address"
* tag 'mips_fixes_4.21_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: OCTEON: mark RGMII interface disabled on OCTEON III
MIPS: Fix a R10000_LLSC_WAR logic in atomic.h
MIPS: BCM63XX: drop unused and broken DSP platform device
mailmap: Update name spelling and email for Dengcheng Zhu
MIPS: ralink: Select CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8
MAINTAINERS: Add a maintainer for MSCC MIPS SoCs
MIPS: Alchemy: update dma masks for devboard devices
MIPS: Alchemy: update cpu-feature-overrides
MIPS: Alchemy: drop DB1000 IrDA support bits
MIPS: alchemy: cpu_all_mask is forbidden for clock event devices
MIPS: BCM63XX: fix switch core reset on BCM6368
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h')
| -rw-r--r-- | arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h index f439cf9cf9d1..ecfbb5aeada3 100644 --- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h @@ -75,10 +75,12 @@ #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 0 +#define cpu_tcache_line_size() 0 #define cpu_has_perf_cntr_intr_bit 0 #define cpu_has_vz 0 #define cpu_has_msa 0 +#define cpu_has_ufr 0 #define cpu_has_fre 0 #define cpu_has_cdmm 0 #define cpu_has_small_pages 0 @@ -88,5 +90,6 @@ #define cpu_has_badinstr 0 #define cpu_has_badinstrp 0 #define cpu_has_contextconfig 0 +#define cpu_has_perf 0 #endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */ |