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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2015-04-03 23:27:26 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-08 01:10:25 +0200 |
| commit | f684362689ddc4a4e055be438d6416cc280a1372 (patch) | |
| tree | b361a8218e4e52f4ffeb243fc8e34d4b2b8555e1 /arch/mips/kernel/cpu-probe.c | |
| parent | 9cb60e202631d71b7b8d38fa84ae7663805244b6 (diff) | |
| download | linux-stable-f684362689ddc4a4e055be438d6416cc280a1372.tar.gz linux-stable-f684362689ddc4a4e055be438d6416cc280a1372.tar.bz2 linux-stable-f684362689ddc4a4e055be438d6416cc280a1372.zip | |
MIPS: math-emu: Set FIR feature flags for full emulation
Implement FIR feature flags in the FPU emulator according to features
supported and architecture level requirements. The W, L and F64 bits
have only been added at level #2 even though the features they refer to
were also included with the MIPS64r1 ISA and the W fixed-point format
also with the MIPS32r1 ISA.
This is only relevant for the full emulation mode and the emulated CFC1
instruction as well as ptrace(2) accesses.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9707/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f8481ce7bbb1..ca9b9c62c6ea 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -20,6 +20,7 @@ #include <asm/bugs.h> #include <asm/cpu.h> +#include <asm/cpu-features.h> #include <asm/cpu-type.h> #include <asm/fpu.h> #include <asm/mipsregs.h> @@ -31,11 +32,30 @@ #include <asm/spram.h> #include <asm/uaccess.h> +/* + * Set the FIR feature flags for the FPU emulator. + */ +static void cpu_set_nofpu_id(struct cpuinfo_mips *c) +{ + u32 value; + + value = 0; + if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | + MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | + MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) + value |= MIPS_FPIR_D | MIPS_FPIR_S; + if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | + MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) + value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; + c->fpu_id = value; +} + static int mips_fpu_disabled; static int __init fpu_disable(char *s) { - cpu_data[0].options &= ~MIPS_CPU_FPU; + boot_cpu_data.options &= ~MIPS_CPU_FPU; + cpu_set_nofpu_id(&boot_cpu_data); mips_fpu_disabled = 1; return 1; @@ -1382,7 +1402,8 @@ void cpu_probe(void) if (c->fpu_id & MIPS_FPIR_FREP) c->options |= MIPS_CPU_FRE; } - } + } else + cpu_set_nofpu_id(c); if (cpu_has_mips_r2_r6) { c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |