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| author | Andrea Gelmini <andrea.gelmini@gelma.net> | 2016-05-21 14:00:11 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-28 12:35:07 +0200 |
| commit | 87fd4e2692a2add7726fb5a497c617c99071de34 (patch) | |
| tree | 12c3acd76fd651e28f4911ebcede2233c7db534e /arch/mips | |
| parent | e904b94a06c77a4241df7ba239c3b5fd1ddb1809 (diff) | |
| download | linux-stable-87fd4e2692a2add7726fb5a497c617c99071de34.tar.gz linux-stable-87fd4e2692a2add7726fb5a497c617c99071de34.tar.bz2 linux-stable-87fd4e2692a2add7726fb5a497c617c99071de34.zip | |
MIPS: IP27: Fix typo
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net>
Cc: trivial@kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13320/
Patchwork: https://patchwork.linux-mips.org/patch/13335/
Patchwork: https://patchwork.linux-mips.org/patch/13336/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/mach-ip27/dma-coherence.h | 2 | ||||
| -rw-r--r-- | arch/mips/pci/ops-bridge.c | 4 | ||||
| -rw-r--r-- | arch/mips/sgi-ip27/ip27-hubio.c | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h index 1daa64412569..04d862020ac9 100644 --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h @@ -64,7 +64,7 @@ static inline void plat_post_dma_flush(struct device *dev) static inline int plat_device_is_coherent(struct device *dev) { - return 1; /* IP27 non-cohernet mode is unsupported */ + return 1; /* IP27 non-coherent mode is unsupported */ } #endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */ diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c index 438319465cb4..57e1463fcd02 100644 --- a/arch/mips/pci/ops-bridge.c +++ b/arch/mips/pci/ops-bridge.c @@ -33,9 +33,9 @@ static u32 emulate_ioc3_cfg(int where, int size) * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is * not really documented, so right now I can't write code which uses it. * Therefore we use type 0 accesses for now even though they won't work - * correcly for PCI-to-PCI bridges. + * correctly for PCI-to-PCI bridges. * - * The function is complicated by the ultimate brokeness of the IOC3 chip + * The function is complicated by the ultimate brokenness of the IOC3 chip * which is used in SGI systems. The IOC3 can only handle 32-bit PCI * accesses and does only decode parts of it's address space. */ diff --git a/arch/mips/sgi-ip27/ip27-hubio.c b/arch/mips/sgi-ip27/ip27-hubio.c index 328ceb3c86ec..2abe016a0ffc 100644 --- a/arch/mips/sgi-ip27/ip27-hubio.c +++ b/arch/mips/sgi-ip27/ip27-hubio.c @@ -105,7 +105,7 @@ static void hub_setup_prb(nasid_t nasid, int prbnum, int credits) prb.iprb_ff = force_fire_and_forget ? 1 : 0; /* - * Set the appropriate number of PIO cresits for the widget. + * Set the appropriate number of PIO credits for the widget. */ prb.iprb_xtalkctr = credits; |