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| author | Florian Fainelli <florian@openwrt.org> | 2014-01-14 09:54:40 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-24 22:39:55 +0100 |
| commit | af2418be63b4e994cfe4b625939d65b9afdfdf6c (patch) | |
| tree | 1b01cc2cab2f2fa6ed2c8316df447a68e8ff38b9 /arch/mips | |
| parent | a4c0201e2306b12354776158ae91fa7d2129c12f (diff) | |
| download | linux-stable-af2418be63b4e994cfe4b625939d65b9afdfdf6c.tar.gz linux-stable-af2418be63b4e994cfe4b625939d65b9afdfdf6c.tar.bz2 linux-stable-af2418be63b4e994cfe4b625939d65b9afdfdf6c.zip | |
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.
Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index db8fae3341e2..9a05292cfae7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -138,6 +138,7 @@ config BCM63XX select SWAP_IO_SPACE select ARCH_REQUIRE_GPIOLIB select HAVE_CLK + select MIPS_L1_CACHE_SHIFT_4 help Support for BCM63XX based boards |