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| author | James Hogan <james.hogan@imgtec.com> | 2015-01-27 21:45:48 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-03-31 12:04:12 +0200 |
| commit | 3ba5040af01fb06a36198f5f6065e25b0655ca0d (patch) | |
| tree | 48cd02c7cc11074f3ee78d9ede5d3399fdf81f65 /arch/mips | |
| parent | 19971c0bcb45f264c83cb2fd2bce50457bd17cc4 (diff) | |
| download | linux-stable-3ba5040af01fb06a36198f5f6065e25b0655ca0d.tar.gz linux-stable-3ba5040af01fb06a36198f5f6065e25b0655ca0d.tar.bz2 linux-stable-3ba5040af01fb06a36198f5f6065e25b0655ca0d.zip | |
MIPS: cevt-r4k: Use CAUSEF_TI, CAUSEF_PCI constants
Use CAUSEF_TI and CAUSEF_PCI constants from asm/mipsregs.h rather than
the magic values (1 << 30) and (1 << 26).
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9124/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/kernel/cevt-r4k.c | 2 | ||||
| -rw-r--r-- | arch/mips/oprofile/op_model_mipsxx.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 623f0bcfcaf1..43ae71870797 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -75,7 +75,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id) * above we now know that the reason we got here must be a timer * interrupt. Being the paranoiacs we are we check anyway. */ - if (!r2 || (read_c0_cause() & (1 << 30))) { + if (!r2 || (read_c0_cause() & CAUSEF_TI)) { /* Clear Count/Compare Interrupt */ write_c0_compare(read_c0_compare()); cd = &per_cpu(mips_clockevent_device, cpu); diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 01f721a85c5b..faf0d4ad0cc2 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -246,7 +246,7 @@ static int mipsxx_perfcount_handler(void) unsigned int counter; int handled = IRQ_NONE; - if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) + if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI)) return handled; switch (counters) { |