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author | Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | 2013-11-27 10:07:53 +0000 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-22 20:19:01 +0100 |
commit | 26ab96dfa9f98d74ef38efbe830d356547a292c1 (patch) | |
tree | 3789a48dbf291811980cde03016eed2dfcde419a /arch/mips | |
parent | 0ce7d58ee0d814622bf7b4700925455dd4960ddd (diff) | |
download | linux-stable-26ab96dfa9f98d74ef38efbe830d356547a292c1.tar.gz linux-stable-26ab96dfa9f98d74ef38efbe830d356547a292c1.tar.bz2 linux-stable-26ab96dfa9f98d74ef38efbe830d356547a292c1.zip |
MIPS: Add support for interAptiv cores
The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6163/
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/include/asm/cpu-type.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/cpu.h | 2 | ||||
-rw-r--r-- | arch/mips/kernel/idle.c | 1 | ||||
-rw-r--r-- | arch/mips/kernel/spram.c | 1 | ||||
-rw-r--r-- | arch/mips/kernel/traps.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/c-r4k.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/sc-mips.c | 1 | ||||
-rw-r--r-- | arch/mips/oprofile/common.c | 1 | ||||
-rw-r--r-- | arch/mips/oprofile/op_model_mipsxx.c | 4 |
9 files changed, 12 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index 00413508da99..02f591bd95ca 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -44,6 +44,7 @@ static inline int __pure __get_cpu_type(const int cpu_type) case CPU_74K: case CPU_M14KC: case CPU_M14KEC: + case CPU_INTERAPTIV: case CPU_PROAPTIV: #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 60adaad6d5d5..a0ec93054636 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -295,7 +295,7 @@ enum cpu_type_enum { CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, - CPU_M14KEC, CPU_PROAPTIV, + CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV, /* * MIPS64 class processors diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index cb2c94f13d01..3553243bf9d6 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -184,6 +184,7 @@ void __init check_wait(void) case CPU_24K: case CPU_34K: case CPU_1004K: + case CPU_INTERAPTIV: case CPU_PROAPTIV: cpu_wait = r4k_wait; if (read_c0_config7() & MIPS_CONF7_WII) diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index fb72b803b754..dfed8a41c696 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -206,6 +206,7 @@ void spram_config(void) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_INTERAPTIV: case CPU_PROAPTIV: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 39370e1d4362..e0b499694d18 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1337,6 +1337,7 @@ static inline void parity_protection_init(void) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_INTERAPTIV: case CPU_PROAPTIV: { #define ERRCTL_PE 0x80000000 diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index eded642e1fef..13b549a67a1e 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1106,6 +1106,7 @@ static void probe_pcache(void) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_INTERAPTIV: case CPU_PROAPTIV: if (current_cpu_type() == CPU_74K) alias_74k_erratum(c); diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 317c2497a75c..7a56aee5fce7 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -76,6 +76,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_BMIPS5000: if (config2 & (1 << 12)) diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index efd2eb3d92e3..2a86e38872a7 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -86,6 +86,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_34K: case CPU_1004K: case CPU_74K: + case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_LOONGSON1: case CPU_SB1: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 3e28aaa39bc9..4d94d75ec6f9 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -376,6 +376,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/74K"; break; + case CPU_INTERAPTIV: + op_model_mipsxx_ops.cpu_type = "mips/interAptiv"; + break; + case CPU_PROAPTIV: op_model_mipsxx_ops.cpu_type = "mips/proAptiv"; break; |