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| author | Mathias Kresin <dev@kresin.me> | 2017-05-11 08:18:24 +0200 |
|---|---|---|
| committer | James Hogan <jhogan@kernel.org> | 2018-03-14 15:18:41 +0000 |
| commit | 05454c1bde91fb013c0431801001da82947e6b5a (patch) | |
| tree | 0f523be3abb3d8c36debf8669915f6dddb4f7e98 /arch/mips | |
| parent | 60c5d8932f069901e34c816a97332b1b2b982955 (diff) | |
| download | linux-stable-05454c1bde91fb013c0431801001da82947e6b5a.tar.gz linux-stable-05454c1bde91fb013c0431801001da82947e6b5a.tar.bz2 linux-stable-05454c1bde91fb013c0431801001da82947e6b5a.zip | |
MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset
According to the QCA u-boot source the "PCIE Phase Lock Loop
Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the
QCA955X and QCA956X at offset 0x10.
Since the PCIE PLL config register is only defined for the AR724x fix
only this value. The value is wrong since the day it was added and isn't
used by any driver yet.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16048/
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index aa3800c82332..d99ca862dae3 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -167,7 +167,7 @@ #define AR71XX_AHB_DIV_MASK 0x7 #define AR724X_PLL_REG_CPU_CONFIG 0x00 -#define AR724X_PLL_REG_PCIE_CONFIG 0x18 +#define AR724X_PLL_REG_PCIE_CONFIG 0x10 #define AR724X_PLL_FB_SHIFT 0 #define AR724X_PLL_FB_MASK 0x3ff |