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authorAndrea Gelmini <andrea.gelmini@gelma.net>2016-05-21 14:01:12 +0200
committerRalf Baechle <ralf@linux-mips.org>2016-05-28 12:35:08 +0200
commita9e7e4518c5152023b9ddebf1d47ee0473f3fab4 (patch)
tree12196e7a9897d264e38d92b9ce18d3a2c36cb06a /arch/mips
parentda66f8e637b1d9fbe285d9f3d1ea37e4b3029978 (diff)
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MIPS: IP22/IP28: Fix typo
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: adam.buchbinder@gmail.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13328/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/sgi/hpc3.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/sgi/hpc3.h b/arch/mips/include/asm/sgi/hpc3.h
index 4a9c99050c13..c0e3dc0293a7 100644
--- a/arch/mips/include/asm/sgi/hpc3.h
+++ b/arch/mips/include/asm/sgi/hpc3.h
@@ -39,7 +39,7 @@ struct hpc3_pbus_dmacregs {
volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 pbdma_ctrl; /* pbus dma channel control register has
- * copletely different meaning for read
+ * completely different meaning for read
* compared with write */
/* read */
#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */