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author | Kumar Gala <galak@kernel.crashing.org> | 2011-12-07 09:08:03 -0600 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2013-03-12 15:59:32 -0500 |
commit | 3d7419714bc956a047a192a152e608a3fbb7e2b1 (patch) | |
tree | 00a8973fff6a717fd01b135f5277ececc7e79c13 /arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | |
parent | cd66cc2ee52bca82f1b06e2fbc1ce63f33700190 (diff) | |
download | linux-stable-3d7419714bc956a047a192a152e608a3fbb7e2b1.tar.gz linux-stable-3d7419714bc956a047a192a152e608a3fbb7e2b1.tar.bz2 linux-stable-3d7419714bc956a047a192a152e608a3fbb7e2b1.zip |
powerpc/fsl-booke: Add initial silicon device tree for T4240
Enable a baseline T4240 SoC to boot. There are several things missing
from the device trees for T4240:
* Proper PAMU topology information
* DPAA related nodes (Qman, Bman, Fman, Rman, DCE)
* Prefetch Manager
* Thermal monitor unit
* Interlaken
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi')
-rw-r--r-- | arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi new file mode 100644 index 000000000000..12af298a9aa0 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi @@ -0,0 +1,127 @@ +/* + * T4240 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/include/ "e6500_power_isa.dtsi" + +/ { + compatible = "fsl,T4240"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + aliases { + ccsr = &soc; + + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + crypto = &crypto; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + pci3 = &pci3; + dma0 = &dma0; + dma1 = &dma1; + sdhc = &sdhc; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,e6500@0 { + device_type = "cpu"; + reg = <0 1>; + next-level-cache = <&L2_1>; + }; + PowerPC,e6500@1 { + device_type = "cpu"; + reg = <2 3>; + next-level-cache = <&L2_1>; + }; + PowerPC,e6500@2 { + device_type = "cpu"; + reg = <4 5>; + next-level-cache = <&L2_1>; + }; + PowerPC,e6500@3 { + device_type = "cpu"; + reg = <6 7>; + next-level-cache = <&L2_1>; + }; + PowerPC,e6500@4 { + device_type = "cpu"; + reg = <8 9>; + next-level-cache = <&L2_2>; + }; + PowerPC,e6500@5 { + device_type = "cpu"; + reg = <10 11>; + next-level-cache = <&L2_2>; + }; + PowerPC,e6500@6 { + device_type = "cpu"; + reg = <12 13>; + next-level-cache = <&L2_2>; + }; + PowerPC,e6500@7 { + device_type = "cpu"; + reg = <14 15>; + next-level-cache = <&L2_2>; + }; + PowerPC,e6500@8 { + device_type = "cpu"; + reg = <16 17>; + next-level-cache = <&L2_3>; + }; + PowerPC,e6500@9 { + device_type = "cpu"; + reg = <18 19>; + next-level-cache = <&L2_3>; + }; + PowerPC,e6500@10 { + device_type = "cpu"; + reg = <20 21>; + next-level-cache = <&L2_3>; + }; + PowerPC,e6500@11 { + device_type = "cpu"; + reg = <22 23>; + next-level-cache = <&L2_3>; + }; + }; +}; |