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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-06-14 10:19:25 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-06-15 23:29:39 +1000 |
| commit | 25642705b2359a705784bbbf1655c25a8f8efde2 (patch) | |
| tree | 9bf28359bbc21c224f1eabdb3a6fce68e4eb271c /arch/powerpc/sysdev/xive | |
| parent | 377aa6b0efbaa29cfeecd8b9244641217f9544ca (diff) | |
| download | linux-stable-25642705b2359a705784bbbf1655c25a8f8efde2.tar.gz linux-stable-25642705b2359a705784bbbf1655c25a8f8efde2.tar.bz2 linux-stable-25642705b2359a705784bbbf1655c25a8f8efde2.zip | |
powerpc/xive: Fix offset for store EOI MMIOs
Architecturally we should apply a 0x400 offset for these. Not doing
it will break future HW implementations.
The offset of 0 is supposed to remain for "triggers" though not all
sources support both trigger and store EOI, and in P9 specifically,
some sources will treat 0 as a store EOI. But future chips will not.
So this makes us use the properly architected offset which should work
always.
Fixes: 243e25112d06 ("powerpc/xive: Native exploitation of the XIVE interrupt controller")
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/sysdev/xive')
| -rw-r--r-- | arch/powerpc/sysdev/xive/common.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c index 913825086b8d..8f5e3035483b 100644 --- a/arch/powerpc/sysdev/xive/common.c +++ b/arch/powerpc/sysdev/xive/common.c @@ -297,7 +297,7 @@ void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd) { /* If the XIVE supports the new "store EOI facility, use it */ if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) - out_be64(xd->eoi_mmio, 0); + out_be64(xd->eoi_mmio + XIVE_ESB_STORE_EOI, 0); else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) { /* * The FW told us to call it. This happens for some |