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| author | Conor Dooley <conor.dooley@microchip.com> | 2022-08-25 19:04:18 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-08-31 16:57:51 +0100 |
| commit | 0dec364ffeb6149aae572ded1e34d4b444c23be6 (patch) | |
| tree | 574c75c06166a8978967d3fd91d6ce608d2fc996 /arch/riscv/boot | |
| parent | 17e4732d1d8a859fbb56e5f050e05d3142b88f96 (diff) | |
| download | linux-stable-0dec364ffeb6149aae572ded1e34d4b444c23be6.tar.gz linux-stable-0dec364ffeb6149aae572ded1e34d4b444c23be6.tar.bz2 linux-stable-0dec364ffeb6149aae572ded1e34d4b444c23be6.zip | |
riscv: dts: microchip: use an mpfs specific l2 compatible
PolarFire SoC does not have the same l2 cache controller as the fu540,
featuring an extra interrupt. Appease the devicetree checker overlords
by adding a PolarFire SoC specific compatible to fix the below sort of
warnings:
mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 74493344ea41..6d9d455fa160 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -185,7 +185,7 @@ ranges; cctrllr: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; + compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; reg = <0x0 0x2010000 0x0 0x1000>; cache-block-size = <64>; cache-level = <2>; |