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| author | Anup Patel <apatel@ventanamicro.com> | 2023-03-28 09:22:17 +0530 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2023-04-08 11:26:23 +0100 |
| commit | 3ee92565b83ecc08e5b0c878dd87a2973eaca2ea (patch) | |
| tree | e1ed67069e6835bec9825cc9e5d9425770e71f07 /arch/riscv/kernel/smp.c | |
| parent | 197b6b60ae7bc51dd0814953c562833143b292aa (diff) | |
| download | linux-stable-3ee92565b83ecc08e5b0c878dd87a2973eaca2ea.tar.gz linux-stable-3ee92565b83ecc08e5b0c878dd87a2973eaca2ea.tar.bz2 linux-stable-3ee92565b83ecc08e5b0c878dd87a2973eaca2ea.zip | |
RISC-V: Clear SIP bit only when using SBI IPI operations
The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230328035223.1480939-2-apatel@ventanamicro.com
Diffstat (limited to 'arch/riscv/kernel/smp.c')
| -rw-r--r-- | arch/riscv/kernel/smp.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 8c3b59f1f9b8..8a12768c09ee 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -112,8 +112,6 @@ void riscv_clear_ipi(void) { if (ipi_ops && ipi_ops->ipi_clear) ipi_ops->ipi_clear(); - - csr_clear(CSR_IP, IE_SIE); } EXPORT_SYMBOL_GPL(riscv_clear_ipi); |