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| author | Zong Li <zong@andestech.com> | 2018-03-15 16:50:44 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-04-02 20:00:54 -0700 |
| commit | e1910c72bdc405b5028510ccc3ed42f0ed25cc6c (patch) | |
| tree | 7a4a2f38c8bc30bcb3fe237afa71f10099e5bf99 /arch/riscv | |
| parent | da975dd4818cf42a181910789c096eb6997ed663 (diff) | |
| download | linux-stable-e1910c72bdc405b5028510ccc3ed42f0ed25cc6c.tar.gz linux-stable-e1910c72bdc405b5028510ccc3ed42f0ed25cc6c.tar.bz2 linux-stable-e1910c72bdc405b5028510ccc3ed42f0ed25cc6c.zip | |
RISC-V: Support CALL relocation type in kernel module
Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/kernel/module.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index be717bd7cea7..3f2730840c25 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -141,6 +141,27 @@ static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_call_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + s64 offset = (void *)v - (void *)location; + s32 fill_v = offset; + u32 hi20, lo12; + + if (offset != fill_v) { + pr_err( + "%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n", + me->name, v, location); + return -EINVAL; + } + + hi20 = (offset + 0x800) & 0xfffff000; + lo12 = (offset - hi20) & 0xfff; + *location = (*location & 0xfff) | hi20; + *(location + 1) = (*(location + 1) & 0xfffff) | (lo12 << 20); + return 0; +} + static int apply_r_riscv_relax_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -157,6 +178,7 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, + [R_RISCV_CALL] = apply_r_riscv_call_rela, [R_RISCV_RELAX] = apply_r_riscv_relax_rela, }; |