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| author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2015-08-20 12:57:33 +0200 |
|---|---|---|
| committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2015-10-14 14:32:06 +0200 |
| commit | acdc9fc9a8121ce2ebcd7533bd72852c20b353f3 (patch) | |
| tree | b1d501fa146502365256a02ac6aa3352ced890fa /arch/s390/kernel/ipl.c | |
| parent | 5614dd920a02a524c9abc9573374d81f0535f18a (diff) | |
| download | linux-stable-acdc9fc9a8121ce2ebcd7533bd72852c20b353f3.tar.gz linux-stable-acdc9fc9a8121ce2ebcd7533bd72852c20b353f3.tar.bz2 linux-stable-acdc9fc9a8121ce2ebcd7533bd72852c20b353f3.zip | |
s390/bitops: implement cache friendly test_and_set_bit_lock
The generic implementation for test_and_set_bit_lock in include/asm-generic
uses the standard test_and_set_bit operation. This is done with either a
'csg' or a 'loag' instruction. For both version the cache line is fetched
exclusively, even if the bit is already set. The result is an increase in
cache traffic, for a contented lock this is a bad idea.
Acked-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'arch/s390/kernel/ipl.c')
0 files changed, 0 insertions, 0 deletions