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| author | Rich Felker <dalias@libc.org> | 2016-03-22 22:02:23 +0000 |
|---|---|---|
| committer | Rich Felker <dalias@libc.org> | 2016-07-31 03:33:32 +0000 |
| commit | 57155c6523074dd937b8feafcfaa98c82218faa6 (patch) | |
| tree | 4ea86ec76b955599269de0963ed4851406997cfc /arch/sh/kernel | |
| parent | bbe6c77857c38f4acbdc4fc70399515226d1859a (diff) | |
| download | linux-stable-57155c6523074dd937b8feafcfaa98c82218faa6.tar.gz linux-stable-57155c6523074dd937b8feafcfaa98c82218faa6.tar.bz2 linux-stable-57155c6523074dd937b8feafcfaa98c82218faa6.zip | |
sh: disable aliased page logic on NOMMU models
SH3/4 (with MMU) have a virtually indexed cache, requiring explicit
work to avoid consistency problems arising from having the same
physical address range cached in multiple cache lines. This is
unneeded for the NOMMU case, and some of the resulting code paths
(kmap_coherent) don't work. SH2 only avoided this problem by having a
4-way associative cache with way size equal to the page size (4k),
yielding no cache index bits outside of the page offset and thus no
aliases.
Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to 'arch/sh/kernel')
| -rw-r--r-- | arch/sh/kernel/cpu/init.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 0d7360d549c1..bfd9e2798008 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -323,9 +323,13 @@ asmlinkage void cpu_init(void) cache_init(); if (raw_smp_processor_id() == 0) { +#ifdef CONFIG_MMU shm_align_mask = max_t(unsigned long, current_cpu_data.dcache.way_size - 1, PAGE_SIZE - 1); +#else + shm_align_mask = PAGE_SIZE - 1; +#endif /* Boot CPU sets the cache shape */ detect_cache_shape(); |