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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2017-12-04 16:09:04 +0100 |
|---|---|---|
| committer | Rich Felker <dalias@libc.org> | 2018-04-12 19:47:56 -0400 |
| commit | d62e9bf5dd4c0298465dd70b78b5532ea6708d63 (patch) | |
| tree | 288382a18f7a41df93da129f576b673e29aa696d /arch/sh | |
| parent | 7dd7f69809b4e3bed5c28dd8600a3a8b20f6441c (diff) | |
| download | linux-stable-d62e9bf5dd4c0298465dd70b78b5532ea6708d63.tar.gz linux-stable-d62e9bf5dd4c0298465dd70b78b5532ea6708d63.tar.bz2 linux-stable-d62e9bf5dd4c0298465dd70b78b5532ea6708d63.zip | |
arch/sh: pcie-sh7786: exclude unusable PCI MEM areas
Depending on the physical memory layout, some PCI MEM areas are not
usable. According to the SH7786 datasheet, the PCI MEM area from
1000_0000 to 13FF_FFFF is only usable if the physical memory layout
(in MMSELR) is 1, 2, 5 or 6. In all other configurations, this PCI MEM
area is not usable (because it overlaps with DRAM).
Therefore, this commit adjusts the PCI SH7786 initialization to mark
the relevant PCI resource as IORESOURCE_DISABLED if we can't use it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/drivers/pci/pcie-sh7786.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index e713c398a6b9..72a1d794a7ba 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -19,6 +19,7 @@ #include <linux/clk.h> #include <linux/sh_clk.h> #include <linux/sh_intc.h> +#include <cpu/sh7786.h> #include "pcie-sh7786.h" #include <asm/sizes.h> @@ -530,6 +531,7 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { static int __init sh7786_pcie_init(void) { struct clk *platclk; + u32 mm_sel; int i; printk(KERN_NOTICE "PCI: Starting initialization.\n"); @@ -563,6 +565,16 @@ static int __init sh7786_pcie_init(void) clk_enable(platclk); + mm_sel = sh7786_mm_sel(); + + /* + * Depending on the MMSELR register value, the PCIe0 MEM 1 + * area may not be available. See Table 13.11 of the SH7786 + * datasheet. + */ + if (mm_sel != 1 && mm_sel != 2 && mm_sel != 5 && mm_sel != 6) + sh7786_pci0_resources[2].flags |= IORESOURCE_DISABLED; + printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports); for (i = 0; i < nr_ports; i++) { |