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| author | Chris Metcalf <cmetcalf@tilera.com> | 2012-06-13 14:46:40 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2012-07-18 16:40:05 -0400 |
| commit | bbaa22c3a0d0be4406d26e5a73d1e8e504787986 (patch) | |
| tree | 4d00f1bda85d9735c60d7db1cdbdd215d5317ae4 /arch/tile/include/asm/homecache.h | |
| parent | 3e219b91533058e242b78ac08aaa91024dd6f369 (diff) | |
| download | linux-stable-bbaa22c3a0d0be4406d26e5a73d1e8e504787986.tar.gz linux-stable-bbaa22c3a0d0be4406d26e5a73d1e8e504787986.tar.bz2 linux-stable-bbaa22c3a0d0be4406d26e5a73d1e8e504787986.zip | |
tilegx pci: support I/O to arbitrarily-cached pages
The tilegx PCI root complex support (currently only in linux-next)
is limited to pages that are homed on cached in the default manner,
i.e. "hash-for-home". This change supports delivery of I/O data to
pages that are cached in other ways (locally on a particular core,
uncached, user-managed incoherent, etc.).
A large part of the change is supporting flushing pages from cache
on particular homes so that we can transition the data that we are
delivering to or from the device appropriately. The new homecache_finv*
routines handle this.
Some changes to page_table_range_init() were also required to make
the fixmap code work correctly on tilegx; it hadn't been used there
before.
We also remove some stub mark_caches_evicted_*() routines that
were just no-ops anyway.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm/homecache.h')
| -rw-r--r-- | arch/tile/include/asm/homecache.h | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/arch/tile/include/asm/homecache.h b/arch/tile/include/asm/homecache.h index a8243865d49e..7b7771328642 100644 --- a/arch/tile/include/asm/homecache.h +++ b/arch/tile/include/asm/homecache.h @@ -79,10 +79,17 @@ extern void homecache_change_page_home(struct page *, int order, int home); /* * Flush a page out of whatever cache(s) it is in. * This is more than just finv, since it properly handles waiting - * for the data to reach memory on tilepro, but it can be quite - * heavyweight, particularly on hash-for-home memory. + * for the data to reach memory, but it can be quite + * heavyweight, particularly on incoherent or immutable memory. */ -extern void homecache_flush_cache(struct page *, int order); +extern void homecache_finv_page(struct page *); + +/* + * Flush a page out of the specified home cache. + * Note that the specified home need not be the actual home of the page, + * as for example might be the case when coordinating with I/O devices. + */ +extern void homecache_finv_map_page(struct page *, int home); /* * Allocate a page with the given GFP flags, home, and optionally @@ -104,10 +111,10 @@ extern struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask, * routines use homecache_change_page_home() to reset the home * back to the default before returning the page to the allocator. */ +void __homecache_free_pages(struct page *, unsigned int order); void homecache_free_pages(unsigned long addr, unsigned int order); -#define homecache_free_page(page) \ - homecache_free_pages((page), 0) - +#define __homecache_free_page(page) __homecache_free_pages((page), 0) +#define homecache_free_page(page) homecache_free_pages((page), 0) /* |