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author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-08-02 14:44:50 -0500 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-08-02 14:53:16 -0500 |
commit | ecf677c8dcaa7bf13eee31b4d9e4639d559984ad (patch) | |
tree | f831c3251c69bd7b0cb49fecc549ab56846927fd /arch/tile | |
parent | bccf90d6e063d278b9ddc78dd266d0adef29886c (diff) | |
download | linux-stable-ecf677c8dcaa7bf13eee31b4d9e4639d559984ad.tar.gz linux-stable-ecf677c8dcaa7bf13eee31b4d9e4639d559984ad.tar.bz2 linux-stable-ecf677c8dcaa7bf13eee31b4d9e4639d559984ad.zip |
PCI: Add a generic weak pcibios_align_resource()
Multiple architectures define this as a trivial function, and I'm adding
another one as part of the RISC-V port. Add a __weak version of
pcibios_align_resource() and delete the now-obselete ones in a handful of
ports.
The only functional change should be that a handful of ports used to export
pcibios_fixup_bus(). Only some architectures export this, so I just
dropped it.
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'arch/tile')
-rw-r--r-- | arch/tile/kernel/pci.c | 10 | ||||
-rw-r--r-- | arch/tile/kernel/pci_gx.c | 9 |
2 files changed, 0 insertions, 19 deletions
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index 3113d4d5c329..8999a20ed9d1 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -67,16 +67,6 @@ static struct pci_ops tile_cfg_ops; /* - * We don't need to worry about the alignment of resources. - */ -resource_size_t pcibios_align_resource(void *data, const struct resource *res, - resource_size_t size, resource_size_t align) -{ - return res->start; -} -EXPORT_SYMBOL(pcibios_align_resource); - -/* * Open a FD to the hypervisor PCI device. * * controller_id is the controller number, config type is 0 or 1 for diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index b89172b592cc..0a7642184a9a 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c @@ -108,15 +108,6 @@ static struct pci_ops tile_cfg_ops; /* Mask of CPUs that should receive PCIe interrupts. */ static struct cpumask intr_cpus_map; -/* We don't need to worry about the alignment of resources. */ -resource_size_t pcibios_align_resource(void *data, const struct resource *res, - resource_size_t size, - resource_size_t align) -{ - return res->start; -} -EXPORT_SYMBOL(pcibios_align_resource); - /* * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #. * For now, we simply send interrupts to non-dataplane CPUs. |