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| author | Kan Liang <kan.liang@linux.intel.com> | 2021-04-12 07:31:03 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-04-19 20:03:29 +0200 |
| commit | 19d3a81fd92dc9b73950564955164ecfd0dfbea1 (patch) | |
| tree | 3ef4175a09fde7073d7472cea9910eeb6d9a28de /arch/x86/events/msr.c | |
| parent | 772ed05f3c5ce722b9de6c4c2dd87538a33fb8d3 (diff) | |
| download | linux-stable-19d3a81fd92dc9b73950564955164ecfd0dfbea1.tar.gz linux-stable-19d3a81fd92dc9b73950564955164ecfd0dfbea1.tar.bz2 linux-stable-19d3a81fd92dc9b73950564955164ecfd0dfbea1.zip | |
perf/x86/msr: Add Alder Lake CPU support
PPERF and SMI_COUNT MSRs are also supported on Alder Lake.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1618237865-33448-24-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events/msr.c')
| -rw-r--r-- | arch/x86/events/msr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 680404c58cb1..c853b28efa33 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -100,6 +100,8 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_TIGERLAKE_L: case INTEL_FAM6_TIGERLAKE: case INTEL_FAM6_ROCKETLAKE: + case INTEL_FAM6_ALDERLAKE: + case INTEL_FAM6_ALDERLAKE_L: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break; |