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| author | Kan Liang <kan.liang@linux.intel.com> | 2020-10-19 08:35:27 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2020-10-29 11:00:40 +0100 |
| commit | 907a196fbc70a48338ee8512da32f70fd33c97eb (patch) | |
| tree | a9216e2d879c328ff9768c49ea40ce72b36bd000 /arch/x86/events/msr.c | |
| parent | cbea56395cba13173fffb9251cb23f146b51c792 (diff) | |
| download | linux-stable-907a196fbc70a48338ee8512da32f70fd33c97eb.tar.gz linux-stable-907a196fbc70a48338ee8512da32f70fd33c97eb.tar.bz2 linux-stable-907a196fbc70a48338ee8512da32f70fd33c97eb.zip | |
perf/x86/msr: Add Rocket Lake CPU support
Like Ice Lake and Tiger Lake, PPERF and SMI_COUNT MSRs are also
supported by Rocket Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20201019153528.13850-3-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events/msr.c')
| -rw-r--r-- | arch/x86/events/msr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 4be8f9cabd07..680404c58cb1 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -99,6 +99,7 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ICELAKE_D: case INTEL_FAM6_TIGERLAKE_L: case INTEL_FAM6_TIGERLAKE: + case INTEL_FAM6_ROCKETLAKE: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break; |