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| author | Marc Zyngier <maz@kernel.org> | 2019-09-05 14:56:47 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-10-05 13:13:54 +0200 |
| commit | 6e2056c4424cf006443bd26f3a208e851c0a6dc3 (patch) | |
| tree | d7a22b3a1983011770b7aae43ae34aba7f2d9da8 /arch/x86/include | |
| parent | 74a94a7e0a01bb678db17282dfecb13d56984de5 (diff) | |
| download | linux-stable-6e2056c4424cf006443bd26f3a208e851c0a6dc3.tar.gz linux-stable-6e2056c4424cf006443bd26f3a208e851c0a6dc3.tar.bz2 linux-stable-6e2056c4424cf006443bd26f3a208e851c0a6dc3.zip | |
irqchip/gic-v3-its: Fix LPI release for Multi-MSI devices
[ Upstream commit c9c96e30ecaa0aafa225aa1a5392cb7db17c7a82 ]
When allocating a range of LPIs for a Multi-MSI capable device,
this allocation extended to the closest power of 2.
But on the release path, the interrupts are released one by
one. This results in not releasing the "extra" range, leaking
the its_device. Trying to reprobe the device will then fail.
Fix it by releasing the LPIs the same way we allocate them.
Fixes: 8208d1708b88 ("irqchip/gic-v3-its: Align PCI Multi-MSI allocation on their size")
Reported-by: Jiaxing Luo <luojiaxing@huawei.com>
Tested-by: John Garry <john.garry@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/f5e948aa-e32f-3f74-ae30-31fee06c2a74@huawei.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/x86/include')
0 files changed, 0 insertions, 0 deletions