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| author | Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> | 2019-06-18 08:37:05 +0000 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2019-06-22 11:45:57 +0200 |
| commit | 761fdd5e3327db6c646a09bab5ad48cd42680cd2 (patch) | |
| tree | 51593895ddb1c28b59fb1223ab1e732f50c7b4df /arch/x86/kernel/cpu/Makefile | |
| parent | 0a05fa67e62c73baad2a7d0fa20e8f96896c1093 (diff) | |
| download | linux-stable-761fdd5e3327db6c646a09bab5ad48cd42680cd2.tar.gz linux-stable-761fdd5e3327db6c646a09bab5ad48cd42680cd2.tar.bz2 linux-stable-761fdd5e3327db6c646a09bab5ad48cd42680cd2.zip | |
x86/cpu: Create Zhaoxin processors architecture support file
Add x86 architecture support for new Zhaoxin processors.
Carve out initialization code needed by Zhaoxin processors into
a separate compilation unit.
To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN
for system recognition.
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/01042674b2f741b2aed1f797359bdffb@zhaoxin.com
Diffstat (limited to 'arch/x86/kernel/cpu/Makefile')
| -rw-r--r-- | arch/x86/kernel/cpu/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 5102bf7c8192..a7d9a4cb3ab6 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o +obj-$(CONFIG_CPU_SUP_ZHAOXIN) += zhaoxin.o obj-$(CONFIG_X86_MCE) += mce/ obj-$(CONFIG_MTRR) += mtrr/ |