diff options
| author | Peter Zijlstra <a.p.zijlstra@chello.nl> | 2010-03-06 19:49:06 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-03-10 13:23:38 +0100 |
| commit | ad0e6cfe2a2a61d7b5530188e571d508146cb43b (patch) | |
| tree | f225acbab7f61c0a0d710ac1740f6bcaa409fdb9 /arch/x86/kernel/cpu | |
| parent | 12ab854d744f04bfc5c6c4db723b7e31fc03eb29 (diff) | |
| download | linux-stable-ad0e6cfe2a2a61d7b5530188e571d508146cb43b.tar.gz linux-stable-ad0e6cfe2a2a61d7b5530188e571d508146cb43b.tar.bz2 linux-stable-ad0e6cfe2a2a61d7b5530188e571d508146cb43b.zip | |
perf, x86: Fix silly bug in intel_pmu_pebs_{enable,disable}
We need to use the actual cpuc->pebs_enabled value, not a local copy for
the changes to take effect.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel_ds.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index b4680daecf19..242369488e72 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -333,11 +333,10 @@ static void intel_pmu_pebs_enable(struct perf_event *event) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; - u64 val = cpuc->pebs_enabled; hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; - val |= 1ULL << hwc->idx; + cpuc->pebs_enabled |= 1ULL << hwc->idx; WARN_ON_ONCE(cpuc->enabled); if (x86_pmu.intel_cap.pebs_trap) @@ -348,11 +347,10 @@ static void intel_pmu_pebs_disable(struct perf_event *event) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; - u64 val = cpuc->pebs_enabled; - val &= ~(1ULL << hwc->idx); + cpuc->pebs_enabled &= ~(1ULL << hwc->idx); if (cpuc->enabled) - wrmsrl(MSR_IA32_PEBS_ENABLE, val); + wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); hwc->config |= ARCH_PERFMON_EVENTSEL_INT; |