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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-06-28 12:06:25 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-06-28 12:06:25 -0700 |
| commit | ab8aadbda7d59d4674ef614cba2a67c50667a6af (patch) | |
| tree | 836c91ed751ec6e93209a1bfdd46ce36f96ce80e /arch/x86/kernel/pci-calgary_64.c | |
| parent | 8b7231a9c76a321ecf907c1c7beaa8ce1aad3be0 (diff) | |
| parent | 499a00e92dd9a75395081f595e681629eb1eebad (diff) | |
| download | linux-stable-ab8aadbda7d59d4674ef614cba2a67c50667a6af.tar.gz linux-stable-ab8aadbda7d59d4674ef614cba2a67c50667a6af.tar.bz2 linux-stable-ab8aadbda7d59d4674ef614cba2a67c50667a6af.zip | |
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
x86, Calgary: Increase max PHB number
x86: Fix rebooting on Dell Precision WorkStation T7400
x86: Fix vsyscall on gcc 4.5 with -Os
x86, pat: Proper init of memtype subtree_max_end
um, hweight: Fix UML boot crash due to x86 optimized hweight
x86, setup: Set ax register in boot vga query
percpu, x86: Avoid warnings of unused variables in per cpu
x86, irq: Rename gsi_end gsi_top, and fix off by one errors
x86: use __ASSEMBLY__ rather than __ASSEMBLER__
Diffstat (limited to 'arch/x86/kernel/pci-calgary_64.c')
| -rw-r--r-- | arch/x86/kernel/pci-calgary_64.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c index fb99f7edb341..0b96b5589f08 100644 --- a/arch/x86/kernel/pci-calgary_64.c +++ b/arch/x86/kernel/pci-calgary_64.c @@ -103,11 +103,16 @@ int use_calgary __read_mostly = 0; #define PMR_SOFTSTOPFAULT 0x40000000 #define PMR_HARDSTOP 0x20000000 -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ -#define MAX_NUM_CHASSIS 8 /* max number of chassis */ -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) -#define PHBS_PER_CALGARY 4 +/* + * The maximum PHB bus number. + * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384 + * x3950M2: 4 chassis, 48 PHBs per chassis = 192 + * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 + * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 + */ +#define MAX_PHB_BUS_NUM 384 + +#define PHBS_PER_CALGARY 4 /* register offsets in Calgary's internal register space */ static const unsigned long tar_offsets[] = { |