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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-09-07 15:39:55 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2016-09-08 08:03:58 +0200 |
| commit | bda7b072de999280ef78aaea4335ec58afc4bdb2 (patch) | |
| tree | 57b48f6f54d942066930831c725f05aa7d8a71b9 /arch/x86/platform | |
| parent | 3976b0380b315651137ce4321b1171ac0a1d26ed (diff) | |
| download | linux-stable-bda7b072de999280ef78aaea4335ec58afc4bdb2.tar.gz linux-stable-bda7b072de999280ef78aaea4335ec58afc4bdb2.tar.bz2 linux-stable-bda7b072de999280ef78aaea4335ec58afc4bdb2.zip | |
x86/platform/intel-mid: Implement power off sequence
Tell SCU that we are about powering off the device.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20160907123955.21228-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/platform')
| -rw-r--r-- | arch/x86/platform/intel-mid/intel-mid.c | 5 | ||||
| -rw-r--r-- | arch/x86/platform/intel-mid/pwr.c | 24 |
2 files changed, 28 insertions, 1 deletions
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c index ce119d2ba0d0..7850128f0026 100644 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -70,6 +70,11 @@ EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); static void intel_mid_power_off(void) { + /* Shut down South Complex via PWRMU */ + intel_mid_pwr_power_off(); + + /* Only for Tangier, the rest will ignore this command */ + intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1); }; static void intel_mid_reboot(void) diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c index 0548741b6894..2dfe998a5afd 100644 --- a/arch/x86/platform/intel-mid/pwr.c +++ b/arch/x86/platform/intel-mid/pwr.c @@ -48,7 +48,15 @@ #define PM_CMD_CM_IMMEDIATE (1 << 9) #define PM_CMD_CM_DELAY (2 << 9) #define PM_CMD_CM_TRIGGER (3 << 9) -#define PM_CMD_D3cold (1 << 21) + +/* System states */ +#define PM_CMD_SYS_STATE_S5 (5 << 16) + +/* Trigger variants */ +#define PM_CMD_CFG_TRIGGER_NC (3 << 19) + +/* Message to wait for TRIGGER_NC case */ +#define TRIGGER_NC_MSG_2 (2 << 22) /* List of commands */ #define CMD_SET_CFG 0x01 @@ -264,6 +272,20 @@ int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) } EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state); +void intel_mid_pwr_power_off(void) +{ + struct mid_pwr *pwr = midpwr; + u32 cmd = PM_CMD_SYS_STATE_S5 | + PM_CMD_CMD(CMD_SET_CFG) | + PM_CMD_CM_TRIGGER | + PM_CMD_CFG_TRIGGER_NC | + TRIGGER_NC_MSG_2; + + /* Send command to SCU */ + writel(cmd, pwr->regs + PM_CMD); + mid_pwr_wait(pwr); +} + int intel_mid_pwr_get_lss_id(struct pci_dev *pdev) { int vndr; |