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| author | Max Filippov <jcmvbkbc@gmail.com> | 2021-02-16 22:39:41 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2021-04-04 15:39:03 -0700 |
| commit | 4f22ca7e192ee313a83f8093ba5b5b2ca72d10e4 (patch) | |
| tree | e6732ce400847258d0c6820d787ac3c1a6420dd6 /arch/xtensa | |
| parent | 2da7559452504f8f8d9950708f293b636e483b21 (diff) | |
| download | linux-stable-4f22ca7e192ee313a83f8093ba5b5b2ca72d10e4.tar.gz linux-stable-4f22ca7e192ee313a83f8093ba5b5b2ca72d10e4.tar.bz2 linux-stable-4f22ca7e192ee313a83f8093ba5b5b2ca72d10e4.zip | |
xtensa: simplify coherent_kvaddr logic
Functions coherent_kvaddr, clear_page_alias and copy_page_alias use
physical address 0 as a special value that means 'this page is in the
KSEG mapping and its existing virtual address has the same color as the
virtual address of its future mapping, so don't map it to the
TLBTEMP_BASE area'.
Simplify this logic and drop special handling of low memory pages/pages
with coherent mapping and always use TLBTEMP_BASE area.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa')
| -rw-r--r-- | arch/xtensa/mm/cache.c | 9 | ||||
| -rw-r--r-- | arch/xtensa/mm/misc.S | 36 |
2 files changed, 7 insertions, 38 deletions
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c index 085b8c77b9d9..19e5a478a7e8 100644 --- a/arch/xtensa/mm/cache.c +++ b/arch/xtensa/mm/cache.c @@ -81,13 +81,8 @@ static inline void kmap_invalidate_coherent(struct page *page, static inline void *coherent_kvaddr(struct page *page, unsigned long base, unsigned long vaddr, unsigned long *paddr) { - if (PageHighMem(page) || !DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) { - *paddr = page_to_phys(page); - return (void *)(base + (vaddr & DCACHE_ALIAS_MASK)); - } else { - *paddr = 0; - return page_to_virt(page); - } + *paddr = page_to_phys(page); + return (void *)(base + (vaddr & DCACHE_ALIAS_MASK)); } void clear_user_highpage(struct page *page, unsigned long vaddr) diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S index 25cd67debee6..0527bf6e3211 100644 --- a/arch/xtensa/mm/misc.S +++ b/arch/xtensa/mm/misc.S @@ -118,20 +118,13 @@ ENTRY(clear_page_alias) abi_entry_default - /* Skip setting up a temporary DTLB if not aliased low page. */ - movi a5, PAGE_OFFSET - movi a6, 0 - beqz a3, 1f - - /* Setup a temporary DTLB for the addr. */ - addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) mov a4, a2 wdtlb a6, a2 dsync -1: movi a3, 0 + movi a3, 0 __loopi a2, a7, PAGE_SIZE, 32 s32i a3, a2, 0 s32i a3, a2, 4 @@ -143,12 +136,9 @@ ENTRY(clear_page_alias) s32i a3, a2, 28 __endla a2, a7, 32 - bnez a6, 1f - abi_ret_default - - /* We need to invalidate the temporary idtlb entry, if any. */ + /* We need to invalidate the temporary dtlb entry. */ -1: idtlb a4 + idtlb a4 dsync abi_ret_default @@ -166,22 +156,12 @@ ENTRY(copy_page_alias) abi_entry_default - /* Skip setting up a temporary DTLB for destination if not aliased. */ - - movi a6, 0 - movi a7, 0 - beqz a4, 1f - /* Setup a temporary DTLB for destination. */ addi a6, a4, (PAGE_KERNEL | _PAGE_HW_WRITE) wdtlb a6, a2 dsync - /* Skip setting up a temporary DTLB for source if not aliased. */ - -1: beqz a5, 1f - /* Setup a temporary DTLB for source. */ addi a7, a5, PAGE_KERNEL @@ -219,17 +199,11 @@ ENTRY(copy_page_alias) /* We need to invalidate any temporary mapping! */ - bnez a6, 1f - bnez a7, 2f - abi_ret_default - -1: addi a2, a2, -PAGE_SIZE + addi a2, a2, -PAGE_SIZE idtlb a2 dsync - bnez a7, 2f - abi_ret_default -2: addi a3, a3, -PAGE_SIZE+1 + addi a3, a3, -PAGE_SIZE+1 idtlb a3 dsync |