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| author | H. Peter Anvin <hpa@zytor.com> | 2009-01-26 09:40:58 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2009-01-26 09:40:58 -0800 |
| commit | 30a0fb947a68ad3ab8a7184e3b3d79dce10e3688 (patch) | |
| tree | 1c2d4059264b71b36d00dcc96c333a47e28ae18a /arch | |
| parent | e88a0faae5baaaa3bdc6f23a55ad6bc7a7b4aa77 (diff) | |
| download | linux-stable-30a0fb947a68ad3ab8a7184e3b3d79dce10e3688.tar.gz linux-stable-30a0fb947a68ad3ab8a7184e3b3d79dce10e3688.tar.bz2 linux-stable-30a0fb947a68ad3ab8a7184e3b3d79dce10e3688.zip | |
x86: correct the CPUID pattern for MSR_IA32_MISC_ENABLE availability
Impact: re-enable CPUID unmasking on affected processors
As far as I am capable of discerning from the documentation,
MSR_IA32_MISC_ENABLE should be available for all family 0xf CPUs, as
well as family 6 for model >= 0xd (newer Pentium M).
The documentation on this isn't ideal, so we need to be on the lookout
for errors, still.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 549f2ada55f5..430e5c38a544 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -30,7 +30,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) { /* Unmask CPUID levels if masked: */ - if (c->x86 == 6 && c->x86_model >= 15) { + if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { u64 misc_enable; rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); |