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| author | Thierry Reding <treding@nvidia.com> | 2015-01-23 16:25:12 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-01-23 16:25:12 +0100 |
| commit | 005510ae7e9d3f8434cf8f79274bdb80aaa5592f (patch) | |
| tree | dbc08541aa9608ba4da691c7d00d174107abfc13 /arch | |
| parent | 97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff) | |
| parent | 3568df3d31d62b4368830cc6aac868cecdefd187 (diff) | |
| download | linux-stable-005510ae7e9d3f8434cf8f79274bdb80aaa5592f.tar.gz linux-stable-005510ae7e9d3f8434cf8f79274bdb80aaa5592f.tar.bz2 linux-stable-005510ae7e9d3f8434cf8f79274bdb80aaa5592f.zip | |
Merge branch 'for-3.20/soc' into for-3.20/arm64
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/tegra124-jetson-tk1.dts | 7 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/Kconfig | 4 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 4eb540be368f..dbfaba09703a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1673,6 +1673,13 @@ nvidia,core-pwr-off-time = <61036>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x40>; + nvidia,reg-addr = <0x36>; + nvidia,reg-data = <0x2>; + }; }; /* Serial ATA */ diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index d0be9a1ef6b8..5d1a318f1302 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -27,6 +27,7 @@ config ARCH_TEGRA_2x_SOC select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 + select TEGRA_TIMER help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -37,6 +38,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_764369 if SMP select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 + select TEGRA_TIMER help Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -47,6 +49,7 @@ config ARCH_TEGRA_114_SOC select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 + select TEGRA_TIMER help Support for NVIDIA Tegra T114 processor family, based on the ARM CortexA15MP CPU @@ -56,6 +59,7 @@ config ARCH_TEGRA_124_SOC select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 + select TEGRA_TIMER help Support for NVIDIA Tegra T124 processor family, based on the ARM CortexA15MP CPU |