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author | David Gibson <david@gibson.dropbear.id.au> | 2007-05-08 14:09:18 +1000 |
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committer | Paul Mackerras <paulus@samba.org> | 2007-05-08 14:43:59 +1000 |
commit | ea20ff5d0338a0fbd78783df657f94ffa7967dd9 (patch) | |
tree | ecfc819439de45b220e094f06f10a1b716e6607e /arch | |
parent | 2cd976477035716af52a6eff6625f32e5813c02b (diff) | |
download | linux-stable-ea20ff5d0338a0fbd78783df657f94ffa7967dd9.tar.gz linux-stable-ea20ff5d0338a0fbd78783df657f94ffa7967dd9.tar.bz2 linux-stable-ea20ff5d0338a0fbd78783df657f94ffa7967dd9.zip |
[POWERPC] Add device tree for Ebony
Add a device tree for the Ebony evaluation board (440GP based). This
tree is not complete or finalized. This tree needs a version of dtc
recent enough to include reference-to-labels to process.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/boot/dts/ebony.dts | 307 |
1 files changed, 307 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts new file mode 100644 index 000000000000..b67918651c48 --- /dev/null +++ b/arch/powerpc/boot/dts/ebony.dts @@ -0,0 +1,307 @@ +/* + * Device Tree Source for IBM Ebony + * + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> + * + * FIXME: Draft only! + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * To build: + * dtc -I dts -O asm -o ebony.S -b 0 ebony.dts + * dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,ebony"; + compatible = "ibm,ebony"; + dcr-parent = <&/cpus/PowerPC,440GP@0>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,440GP@0 { + device_type = "cpu"; + reg = <0>; + clock-frequency = <0>; // Filled in by zImage + timebase-frequency = <0>; // Filled in by zImage + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <0>; + d-cache-size = <0>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0>; // Filled in by zImage + }; + + UIC0: interrupt-controller0 { + device_type = "ibm,uic"; + compatible = "ibm,uic-440gp", "ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + + }; + + UIC1: interrupt-controller1 { + device_type = "ibm,uic"; + compatible = "ibm,uic-440gp", "ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0d0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1e 4 1f 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + CPC0: cpc { + device_type = "ibm,cpc"; + compatible = "ibm,cpc-440gp"; + dcr-reg = <0b0 003 0e0 010>; + // FIXME: anything else? + }; + + plb { + device_type = "ibm,plb"; + compatible = "ibm,plb-440gp", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + + SDRAM0: sdram { + device_type = "memory-controller"; + compatible = "ibm,sdram-440gp", "ibm,sdram"; + dcr-reg = <010 2>; + // FIXME: anything else? + }; + + DMA0: dma { + // FIXME: ??? + device_type = "ibm,dma-4xx"; + compatible = "ibm,dma-440gp", "ibm,dma-4xx"; + dcr-reg = <100 027>; + }; + + MAL0: mcmal { + device_type = "mcmal-dma"; + compatible = "ibm,mcmal-440gp", "ibm,mcmal"; + dcr-reg = <180 62>; + num-tx-chans = <4>; + num-rx-chans = <4>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 + /*RXEOB*/ 1 &UIC0 b 4 + /*SERR*/ 2 &UIC1 0 4 + /*TXDE*/ 3 &UIC1 1 4 + /*RXDE*/ 4 &UIC1 2 4>; + interrupt-map-mask = <ffffffff>; + }; + + POB0: opb { + device_type = "ibm,opb"; + compatible = "ibm,opb-440gp", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <00000000 1 00000000 80000000 + 80000000 1 80000000 80000000>; + dcr-reg = <090 00b>; + interrupt-parent = <&UIC1>; + interrupts = <7 4>; + clock-frequency = <0>; // Filled in by zImage + + EBC0: ebc { + device_type = "ibm,ebc"; + compatible = "ibm,ebc-440gp"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; // Filled in by zImage + ranges = <0 00000000 fff00000 100000 + 1 00000000 48000000 100000 + 2 00000000 ff800000 400000 + 3 00000000 48200000 100000 + 7 00000000 48300000 100000>; + interrupts = <5 4>; + interrupt-parent = <&UIC1>; + + small-flash@0,0 { + device_type = "rom"; + compatible = "direct-mapped"; + probe-type = "JEDEC"; + bank-width = <1>; + partitions = <0 80000>; + partition-names = "OpenBIOS"; + reg = <0 80000 80000>; + }; + + ds1743@1,0 { + /* NVRAM & RTC */ + device_type = "nvram"; + compatible = "ds1743"; + reg = <1 0 2000>; + }; + + large-flash@2,0 { + device_type = "rom"; + compatible = "direct-mapped"; + probe-type = "JEDEC"; + bank-width = <1>; + partitions = <0 380000 + 280000 80000>; + partition-names = "fs", "firmware"; + reg = <2 0 400000>; + }; + + ir@3,0 { + reg = <3 0 10>; + }; + + fpga@7,0 { + compatible = "Ebony-FPGA"; + reg = <7 0 10>; + }; + }; + + UART0: serial@40000200 { + device_type = "serial"; + compatible = "ns16550"; + reg = <40000200 8>; + virtual-reg = <e0000200>; + clock-frequency = <A8C000>; + current-speed = <2580>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@40000300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <40000300 8>; + virtual-reg = <e0000300>; + clock-frequency = <A8C000>; + current-speed = <2580>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + IIC0: i2c@40000400 { + /* FIXME */ + device_type = "i2c"; + compatible = "ibm,iic-440gp", "ibm,iic"; + reg = <40000400 14>; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + IIC1: i2c@40000500 { + /* FIXME */ + device_type = "i2c"; + compatible = "ibm,iic-440gp", "ibm,iic"; + reg = <40000500 14>; + interrupt-parent = <&UIC0>; + interrupts = <3 4>; + }; + + GPIO0: gpio@40000700 { + /* FIXME */ + device_type = "gpio"; + compatible = "ibm,gpio-440gp"; + reg = <40000700 20>; + }; + + ZMII0: emac-zmii@40000780 { + device_type = "emac-zmii"; + compatible = "ibm,zmii-440gp", "ibm,zmii"; + reg = <40000780 c>; + }; + + EMAC0: ethernet@40000800 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-440gp", "ibm,emac"; + interrupt-parent = <&UIC1>; + interrupts = <1c 4 1d 4>; + reg = <40000800 70>; + local-mac-address = [000000000000]; // Filled in by zImage + mal-device = <&MAL0>; + mal-tx-channel = <0 1>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000001>; + zmii-device = <&ZMII0>; + zmii-channel = <0>; + }; + EMAC1: ethernet@40000900 { + linux,network-index = <1>; + device_type = "network"; + compatible = "ibm,emac-440gp", "ibm,emac"; + interrupt-parent = <&UIC1>; + interrupts = <1e 4 1f 4>; + reg = <40000900 70>; + local-mac-address = [000000000000]; // Filled in by zImage + mal-device = <&MAL0>; + mal-tx-channel = <2 3>; + mal-rx-channel = <1>; + cell-index = <1>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000001>; + zmii-device = <&ZMII0>; + zmii-channel = <1>; + }; + + + GPT0: gpt@40000a00 { + /* FIXME */ + reg = <40000a00 d4>; + interrupt-parent = <&UIC0>; + interrupts = <12 4 13 4 14 4 15 4 16 4>; + }; + + }; + + PCIX0: pci@1234 { + device_type = "pci"; + /* FIXME */ + reg = <2 0ec00000 8 + 2 0ec80000 f0 + 2 0ec80100 fc>; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@40000200"; +// linux,initrd-start = <0>; /* FIXME */ +// linux,initrd-end = <0>; +// bootargs = ""; + }; +}; + |