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| author | Will Deacon <will@kernel.org> | 2019-08-22 15:03:45 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-10-05 13:14:07 +0200 |
| commit | ef2fa63bbe95f6d658c30c7a0cb7dc0004e7ac4d (patch) | |
| tree | ebaae0f6d1c6331e1b435c75e3578b1d5eb75f1c /arch | |
| parent | 516d6291476680c53760f49f5a37c9cb2514fad5 (diff) | |
| download | linux-stable-ef2fa63bbe95f6d658c30c7a0cb7dc0004e7ac4d.tar.gz linux-stable-ef2fa63bbe95f6d658c30c7a0cb7dc0004e7ac4d.tar.bz2 linux-stable-ef2fa63bbe95f6d658c30c7a0cb7dc0004e7ac4d.zip | |
arm64: tlb: Ensure we execute an ISB following walk cache invalidation
commit 51696d346c49c6cf4f29e9b20d6e15832a2e3408 upstream.
05f2d2f83b5a ("arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable")
added a new TLB invalidation helper which is used when freeing
intermediate levels of page table used for kernel mappings, but is
missing the required ISB instruction after completion of the TLBI
instruction.
Add the missing barrier.
Cc: <stable@vger.kernel.org>
Fixes: 05f2d2f83b5a ("arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable")
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/include/asm/tlbflush.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 8af7a85f76bd..bc3949064725 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -251,6 +251,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) dsb(ishst); __tlbi(vaae1is, addr); dsb(ish); + isb(); } #endif |