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| author | Peter Zijlstra <peterz@infradead.org> | 2017-04-11 10:10:28 +0200 |
|---|---|---|
| committer | Ben Hutchings <ben@decadent.org.uk> | 2017-07-18 18:40:35 +0100 |
| commit | 5b423b8e9d13db20ab02d43f20568b0af4665104 (patch) | |
| tree | 109bd4ffe088189cf0b937a06473b602c865e3f9 /arch | |
| parent | 12c51886903fa1841f34ee2eabed363389f9e757 (diff) | |
| download | linux-stable-5b423b8e9d13db20ab02d43f20568b0af4665104.tar.gz linux-stable-5b423b8e9d13db20ab02d43f20568b0af4665104.tar.bz2 linux-stable-5b423b8e9d13db20ab02d43f20568b0af4665104.zip | |
perf/x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32()
commit f2200ac311302fcdca6556fd0c5127eab6c65a3e upstream.
When the perf_branch_entry::{in_tx,abort,cycles} fields were added,
intel_pmu_lbr_read_32() wasn't updated to initialize them.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Fixes: 135c5612c460 ("perf/x86/intel: Support Haswell/v4 LBR format")
Signed-off-by: Ingo Molnar <mingo@kernel.org>
[bwh: Backported to 3.16:
- There's no perf_branch_entry::cycles field
- Adjust filename]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel_lbr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c index 9dd2459a4c73..32a14fe2a65c 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c @@ -268,6 +268,8 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) cpuc->lbr_entries[i].to = msr_lastbranch.to; cpuc->lbr_entries[i].mispred = 0; cpuc->lbr_entries[i].predicted = 0; + cpuc->lbr_entries[i].in_tx = 0; + cpuc->lbr_entries[i].abort = 0; cpuc->lbr_entries[i].reserved = 0; } cpuc->lbr_stack.nr = i; |