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| author | Kevin Cernekee <cernekee@gmail.com> | 2010-10-16 14:22:33 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-07-25 17:26:54 +0100 |
| commit | 273f2d7e64f9fd22192b4cd31e7408284a721e69 (patch) | |
| tree | fcfc44b3b5c650c5d923e9cf428c7b3e82d43852 /arch | |
| parent | 565b60de325070ccc54b18346a1238d4fae17954 (diff) | |
| download | linux-stable-273f2d7e64f9fd22192b4cd31e7408284a721e69.tar.gz linux-stable-273f2d7e64f9fd22192b4cd31e7408284a721e69.tar.bz2 linux-stable-273f2d7e64f9fd22192b4cd31e7408284a721e69.zip | |
MIPS: Install handlers for software IRQs
BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/irq_cpu.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 6e71b284f6c9..191eb52228c4 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -103,14 +103,12 @@ void __init mips_cpu_irq_init(void) clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - /* - * Only MT is using the software interrupts currently, so we just - * leave them uninitialized for other processors. - */ - if (cpu_has_mipsmt) - for (i = irq_base; i < irq_base + 2; i++) - irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller, - handle_percpu_irq); + /* Software interrupts are used for MT/CMT IPI */ + for (i = irq_base; i < irq_base + 2; i++) + irq_set_chip_and_handler(i, cpu_has_mipsmt ? + &mips_mt_cpu_irq_controller : + &mips_cpu_irq_controller, + handle_percpu_irq); for (i = irq_base + 2; i < irq_base + 8; i++) irq_set_chip_and_handler(i, &mips_cpu_irq_controller, |