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authorIvan T. Ivanov <ivan.ivanov@linaro.org>2015-09-18 16:18:53 +0300
committerAndy Gross <agross@codeaurora.org>2015-12-08 14:34:22 -0600
commit806c765ee9da58ca0ade34345f1b114dc0be97fd (patch)
treedd3f3fc530c9287e316b1e1aa13c6b8b07dcbf4a /arch
parent8005c49d9aea74d382f474ce11afbbc7d7130bec (diff)
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arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations
Add devicetree bindings for UART1 CTS_N and RTS_N pins. Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pins.dtsi13
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 49ec55a37614..d656e892fd52 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -16,10 +16,13 @@
blsp1_uart1_default: blsp1_uart1_default {
pinmux {
function = "blsp_uart1";
- pins = "gpio0", "gpio1";
+ // TX, RX, CTS_N, RTS_N
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
};
pinconf {
- pins = "gpio0", "gpio1";
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
drive-strength = <16>;
bias-disable;
};
@@ -28,10 +31,12 @@
blsp1_uart1_sleep: blsp1_uart1_sleep {
pinmux {
function = "gpio";
- pins = "gpio0", "gpio1";
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
};
pinconf {
- pins = "gpio0", "gpio1";
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
drive-strength = <2>;
bias-pull-down;
};